Use the PDI REPEAT instruction in the PDI programmer code to reduce protocol overhead...

diff --git a/Projects/AVRISP/Lib/NVMTarget.c b/Projects/AVRISP/Lib/NVMTarget.c
index a23ccf2..b57cf6d 100644 (file)
--- a/Projects/AVRISP/Lib/NVMTarget.c
+++ b/Projects/AVRISP/Lib/NVMTarget.c
@@ -40,8 +40,10 @@
 \r
 void NVMTarget_SendNVMRegAddress(uint8_t Register)\r
 {\r
+       /* Determine the absolute register address from the NVM base memory address and the NVM register address */\r
        uint32_t Address = XPROG_Param_NVMBase | Register;\r
 \r
+       /* Send the calculated 32-bit address to the target, LSB first */\r
        PDITarget_SendByte(Address &  0xFF);\r
        PDITarget_SendByte(Address >> 8);\r
        PDITarget_SendByte(Address >> 16);\r
@@ -50,38 +52,30 @@ void NVMTarget_SendNVMRegAddress(uint8_t Register)
 \r
 void NVMTarget_SendAddress(uint32_t AbsoluteAddress)\r
 {\r
+       /* Send the given 32-bit address to the target, LSB first */\r
        PDITarget_SendByte(AbsoluteAddress &  0xFF);\r
        PDITarget_SendByte(AbsoluteAddress >> 8);\r
        PDITarget_SendByte(AbsoluteAddress >> 16);\r
        PDITarget_SendByte(AbsoluteAddress >> 24);\r
 }\r
 \r
-bool NVMTarget_WaitWhileNVMBusBusy(void)\r
+bool NVMTarget_WaitWhileNVMControllerBusy(void)\r
 {\r
-       uint8_t AttemptsRemaining = 255;\r
+       TCNT0 = 0;\r
 \r
-       /* Poll the STATUS register to check to see if NVM access has been enabled */\r
-       while (AttemptsRemaining--)\r
-       {\r
-               PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
-               if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
-                 return true;\r
-       }\r
-       \r
-       return false;\r
-}\r
-\r
-void NVMTarget_WaitWhileNVMControllerBusy(void)\r
-{\r
        /* Poll the NVM STATUS register while the NVM controller is busy */\r
-       for (;;)\r
+       while (TCNT0 < NVM_BUSY_TIMEOUT_MS)\r
        {\r
+               /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
                PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
                NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
                \r
+               /* Check to see if the BUSY flag is still set */\r
                if (!(PDITarget_ReceiveByte() & (1 << 7)))\r
-                 return;\r
+                 return true;\r
        }\r
+       \r
+       return false;\r
 }\r
 \r
 uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)\r
@@ -101,18 +95,20 @@ uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)
        PDITarget_SendByte(1 << 0);\r
 \r
        /* Wait until the NVM bus and controller is no longer busy */\r
-       NVMTarget_WaitWhileNVMBusBusy();\r
+       PDITarget_WaitWhileNVMBusBusy();\r
        NVMTarget_WaitWhileNVMControllerBusy();\r
        \r
-       /* Read the three bytes generated CRC value */\r
+       /* Read the first generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);\r
        MemoryCRC  = PDITarget_ReceiveByte();\r
 \r
+       /* Read the second generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);\r
        MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
 \r
+       /* Read the third generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);\r
        MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
@@ -123,17 +119,33 @@ uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)
 void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)\r
 {\r
        NVMTarget_WaitWhileNVMControllerBusy();\r
-\r
+       \r
+       /* Send the READNVM command to the NVM controller for reading of an aribtrary location */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
        PDITarget_SendByte(NVM_CMD_READNVM);\r
 \r
-       /* TODO: Optimize via REPEAT and buffer orientated commands */\r
-       for (uint16_t i = 0; i < ReadSize; i++)\r
+       /* Send the address of the first location to read from - this also primes the internal address\r
+        * counters so that we can use the REPEAT command later to save on overhead for multiple bytes */\r
+       PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
+       NVMTarget_SendAddress(ReadAddress);\r
+       *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+\r
+       /* Check to see if we are reading more than a single byte */\r
+       if (ReadSize > 1)\r
        {\r
-               PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
-               NVMTarget_SendAddress(ReadAddress++);\r
-               *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+               /* Decrement the ReadSize counter as we have already read once byte of memory */\r
+               ReadSize--;\r
+       \r
+               /* Send the REPEAT command with the specified number of bytes remaining to read */\r
+               PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);\r
+               PDITarget_SendByte(ReadSize &  0xFF);\r
+               PDITarget_SendByte(ReadSize >> 8);\r
+               \r
+               /* Send a LD command with indirect access and postincrement to read out the remaining bytes */\r
+               PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
+               for (uint16_t i = 1; i < ReadSize; i++)\r
+                 *(ReadBuffer++) = PDITarget_ReceiveByte();\r
        }\r
 }\r
 \r
@@ -145,6 +157,7 @@ void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
        NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
        PDITarget_SendByte(EraseCommand);\r
        \r
+       /* Chip erase is handled seperately, since it's procedure is different to other erase types */\r
        if (EraseCommand == NVM_CMD_CHIPERASE)\r
        {\r
                /* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
@@ -160,7 +173,8 @@ void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
                PDITarget_SendByte(0x00);\r
        }\r
        \r
-       NVMTarget_WaitWhileNVMBusBusy();\r
+       /* Wait until both the NVM bus and NVM controller are ready again */\r
+       PDITarget_WaitWhileNVMBusBusy();\r
        NVMTarget_WaitWhileNVMControllerBusy();\r
 }\r
 \r

diff --git a/Projects/AVRISP/Lib/NVMTarget.h b/Projects/AVRISP/Lib/NVMTarget.h
index bd9296f..7fde845 100644 (file)
--- a/Projects/AVRISP/Lib/NVMTarget.h
+++ b/Projects/AVRISP/Lib/NVMTarget.h
@@ -56,12 +56,7 @@
                #endif\r
 \r
        /* Defines: */\r
-               #define FLASH_BASE                     0x00800000\r
-               #define EPPROM_BASE                    0x008C0000\r
-               #define FUSE_BASE                      0x008F0020\r
-               #define DATAMEM_BASE                   0x01000000\r
-               #define PROD_SIGNATURE_BASE            0x008E0200\r
-               #define USER_SIGNATURE_BASE            0x008E0400\r
+               #define NVM_BUSY_TIMEOUT_MS            200\r
                \r
                #define NVM_REG_ADDR0                  0x00\r
                #define NVM_REG_ADDR1                  0x01\r
@@ -113,8 +108,7 @@
        /* Function Prototypes: */\r
                void     NVMTarget_SendNVMRegAddress(uint8_t Register);\r
                void     NVMTarget_SendAddress(uint32_t AbsoluteAddress);\r
-               bool     NVMTarget_WaitWhileNVMBusBusy(void);\r
-               void     NVMTarget_WaitWhileNVMControllerBusy(void);\r
+               bool     NVMTarget_WaitWhileNVMControllerBusy(void);\r
                uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand);\r
                void     NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize);\r
                void     NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address);\r

diff --git a/Projects/AVRISP/Lib/PDIProtocol.c b/Projects/AVRISP/Lib/PDIProtocol.c
index 39f33cf..af6fbea 100644 (file)
--- a/Projects/AVRISP/Lib/PDIProtocol.c
+++ b/Projects/AVRISP/Lib/PDIProtocol.c
@@ -114,7 +114,7 @@ static void PDIProtocol_EnterXPROGMode(void)
          PDITarget_SendByte(PDI_NVMENABLE_KEY[i - 1]);\r
 \r
        /* Wait until the NVM bus becomes active */\r
-       bool NVMBusEnabled = NVMTarget_WaitWhileNVMBusBusy();\r
+       bool NVMBusEnabled = PDITarget_WaitWhileNVMBusBusy();\r
        \r
        Endpoint_Write_Byte(CMD_XPROG);\r
        Endpoint_Write_Byte(XPRG_CMD_ENTER_PROGMODE);\r

diff --git a/Projects/AVRISP/Lib/PDITarget.c b/Projects/AVRISP/Lib/PDITarget.c
index e1b77f0..9f2bea8 100644 (file)
--- a/Projects/AVRISP/Lib/PDITarget.c
+++ b/Projects/AVRISP/Lib/PDITarget.c
@@ -44,7 +44,7 @@ volatile bool     IsSending;
 volatile uint16_t SoftUSART_Data;\r
 volatile uint8_t  SoftUSART_BitCount;\r
 \r
-ISR(TIMER0_COMPA_vect, ISR_BLOCK)\r
+ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
        BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
@@ -112,11 +112,10 @@ void PDITarget_EnableTargetPDI(void)
        asm volatile ("NOP"::);\r
        asm volatile ("NOP"::);\r
 \r
-       /* Fire timer compare ISR every 50 cycles to manage the software USART */\r
-       OCR0A   = 50;\r
-       TCCR0A  = (1 << WGM01);\r
-       TCCR0B  = (1 << CS00);\r
-       TIMSK0  = (1 << OCIE0A);\r
+       /* Fire timer compare ISR every 100 cycles to manage the software USART */\r
+       OCR1A   = 100;\r
+       TCCR1B  = (1 << WGM12) | (1 << CS10);\r
+       TIMSK1  = (1 << OCIE1A);\r
        \r
        PDITarget_SendBreak();\r
        PDITarget_SendBreak();\r
@@ -275,4 +274,20 @@ void PDITarget_SendBreak(void)
 #endif\r
 }\r
 \r
+bool PDITarget_WaitWhileNVMBusBusy(void)\r
+{\r
+       TCNT0 = 0;\r
+\r
+       /* Poll the STATUS register to check to see if NVM access has been enabled */\r
+       while (TCNT0 < PDI_NVM_TIMEOUT_MS)\r
+       {\r
+               /* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */\r
+               PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
+               if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
+                 return true;\r
+       }\r
+       \r
+       return false;\r
+}\r
+\r
 #endif\r

diff --git a/Projects/AVRISP/Lib/PDITarget.h b/Projects/AVRISP/Lib/PDITarget.h
index 2a2af6e..03083fc 100644 (file)
--- a/Projects/AVRISP/Lib/PDITarget.h
+++ b/Projects/AVRISP/Lib/PDITarget.h
@@ -69,6 +69,8 @@
                \r
                #define BITS_IN_FRAME            12\r
                \r
+               #define PDI_NVM_TIMEOUT_MS       200\r
+               \r
                #define PDI_CMD_LDS              0x00\r
                #define PDI_CMD_LD               0x20\r
                #define PDI_CMD_STS              0x40\r
@@ -102,5 +104,6 @@
                void    PDITarget_SendByte(uint8_t Byte);\r
                uint8_t PDITarget_ReceiveByte(void);\r
                void    PDITarget_SendBreak(void);\r
+               bool    PDITarget_WaitWhileNVMBusBusy(void);\r
 \r
 #endif\r