Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 void NVMTarget_SendNVMRegAddress(uint8_t Register)
  42 {
  43         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  44         uint32_t Address = XPROG_Param_NVMBase | Register;
  45
  46         /* Send the calculated 32-bit address to the target, LSB first */
  47         PDITarget_SendByte(Address &  0xFF);
  48         PDITarget_SendByte(Address >> 8);
  49         PDITarget_SendByte(Address >> 16);
  50         PDITarget_SendByte(Address >> 24);
  51 }
  52
  53 void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
  54 {
  55         /* Send the given 32-bit address to the target, LSB first */
  56         PDITarget_SendByte(AbsoluteAddress &  0xFF);
  57         PDITarget_SendByte(AbsoluteAddress >> 8);
  58         PDITarget_SendByte(AbsoluteAddress >> 16);
  59         PDITarget_SendByte(AbsoluteAddress >> 24);
  60 }
  61
  62 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  63 {
  64         TCNT0 = 0;
  65
  66         /* Poll the NVM STATUS register while the NVM controller is busy */
  67         while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
  68         {
  69                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  70                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  71                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  72
  73                 /* Check to see if the BUSY flag is still set */
  74                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  75                   return true;
  76         }
  77
  78         return false;
  79 }
  80
  81 uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)
  82 {
  83         uint32_t MemoryCRC;
  84
  85         NVMTarget_WaitWhileNVMControllerBusy();
  86
  87         /* Set the NVM command to the correct CRC read command */
  88         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
  89         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
  90         PDITarget_SendByte(MemoryCommand);
  91
  92         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
  93         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
  94         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
  95         PDITarget_SendByte(1 << 0);
  96
  97         /* Wait until the NVM bus and controller is no longer busy */
  98         PDITarget_WaitWhileNVMBusBusy();
  99         NVMTarget_WaitWhileNVMControllerBusy();
 100
 101         /* Read the first generated CRC byte value */
 102         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 103         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 104         MemoryCRC  = PDITarget_ReceiveByte();
 105
 106         /* Read the second generated CRC byte value */
 107         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 108         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 109         MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 110
 111         /* Read the third generated CRC byte value */
 112         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 113         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 114         MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 115
 116         return MemoryCRC;
 117 }
 118
 119 void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
 120 {
 121         NVMTarget_WaitWhileNVMControllerBusy();
 122
 123         /* Send the READNVM command to the NVM controller for reading of an aribtrary location */
 124         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 125         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 126         PDITarget_SendByte(NVM_CMD_READNVM);
 127
 128         /* Send the address of the first location to read from - this also primes the internal address
 129          * counters so that we can use the REPEAT command later to save on overhead for multiple bytes */
 130         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 131         NVMTarget_SendAddress(ReadAddress);
 132         *(ReadBuffer++) = PDITarget_ReceiveByte();
 133
 134         /* Check to see if we are reading more than a single byte */
 135         if (ReadSize > 1)
 136         {
 137                 /* Decrement the ReadSize counter as we have already read once byte of memory */
 138                 ReadSize--;
 139
 140                 /* Send the REPEAT command with the specified number of bytes remaining to read */
 141                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);
 142                 PDITarget_SendByte(ReadSize &  0xFF);
 143                 PDITarget_SendByte(ReadSize >> 8);
 144
 145                 /* Send a LD command with indirect access and postincrement to read out the remaining bytes */
 146                 PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 147                 for (uint16_t i = 1; i < ReadSize; i++)
 148                   *(ReadBuffer++) = PDITarget_ReceiveByte();
 149         }
 150 }
 151
 152 void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
 153 {
 154         NVMTarget_WaitWhileNVMControllerBusy();
 155
 156         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 157         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 158         PDITarget_SendByte(EraseCommand);
 159
 160         /* Chip erase is handled seperately, since it's procedure is different to other erase types */
 161         if (EraseCommand == NVM_CMD_CHIPERASE)
 162         {
 163                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 164                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 165                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 166                 PDITarget_SendByte(1 << 0);
 167         }
 168         else
 169         {
 170                 /* Other erase modes just need us to address a byte within the target memory space */
 171                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 172                 NVMTarget_SendAddress(Address);
 173                 PDITarget_SendByte(0x00);
 174         }
 175
 176         /* Wait until both the NVM bus and NVM controller are ready again */
 177         PDITarget_WaitWhileNVMBusBusy();
 178         NVMTarget_WaitWhileNVMControllerBusy();
 179 }
 180
 181 #endif