\r
#if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)\r
\r
-/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC\r
- * calculation.\r
+/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read.\r
*\r
* \return Boolean true if the NVM controller became ready within the timeout period, false otherwise\r
*/\r
-bool XMEGANVM_WaitWhileNVMBusBusy(void)\r
+bool TINYNVM_WaitWhileNVMBusBusy(void)\r
{\r
- // TODO\r
+ TCNT0 = 0;\r
+ TIFR0 = (1 << OCF1A);\r
+ \r
+ uint8_t TimeoutMS = TINY_NVM_BUSY_TIMEOUT_MS;\r
\r
- return false;\r
-}\r
+ /* Poll the STATUS register to check to see if NVM access has been enabled */\r
+ while (TimeoutMS)\r
+ {\r
+ /* Send the SLDCS command to read the TPI STATUS register to see the NVM bus is active */\r
+ XPROGTarget_SendByte(TPI_CMD_SLDCS | TPI_STATUS_REG);\r
+ if (XPROGTarget_ReceiveByte() & TPI_STATUS_NVM)\r
+ return true;\r
\r
-/** Waits while the target's NVM controller is busy performing an operation, exiting if the\r
- * timeout period expires.\r
- *\r
- * \return Boolean true if the NVM controller became ready within the timeout period, false otherwise\r
- */\r
-bool XMEGANVM_WaitWhileNVMControllerBusy(void)\r
-{\r
- // TODO\r
+ if (TIFR0 & (1 << OCF1A))\r
+ {\r
+ TIFR0 = (1 << OCF1A);\r
+ TimeoutMS--;\r
+ }\r
+ }\r
\r
return false;\r
}\r
\r
-/** Retrieves the CRC value of the given memory space.\r
- *\r
- * \param[in] CRCCommand NVM CRC command to issue to the target\r
- * \param[out] CRCDest CRC Destination when read from the target\r
- *\r
- * \return Boolean true if the command sequence complete successfully\r
- */\r
-bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)\r
-{\r
- // TODO\r
-\r
- return true;\r
-}\r
-\r
/** Reads memory from the target's memory spaces.\r
*\r
* \param[in] ReadAddress Start address to read from within the target's address space\r
*\r
* \return Boolean true if the command sequence complete successfully\r
*/\r
-bool XMEGANVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)\r
+bool TINYNVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)\r
{\r
// TODO\r
\r
*\r
* \return Boolean true if the command sequence complete successfully\r
*/\r
-bool XMEGANVM_WriteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)\r
+bool TINYNVM_WriteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)\r
{\r
// TODO\r
\r
*\r
* \return Boolean true if the command sequence complete successfully\r
*/\r
-bool XMEGANVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)\r
+bool TINYNVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)\r
{\r
// TODO\r
\r
#define TINY_NVM_BUSY_TIMEOUT_MS 100\r
\r
/* Function Prototypes: */\r
- bool TINYNVM_WaitWhileNVMControllerBusy(void);\r
+ bool TINYNVM_WaitWhileNVMBusBusy(void);\r
bool TINYNVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize);\r
bool TINYNVM_WriteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer);\r
bool TINYNVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address);\r
- bool TINYNVM_WaitWhileNVMBusBusy(void);\r
\r
#endif\r
/* Function Prototypes: */\r
void XMEGANVM_SendNVMRegAddress(const uint8_t Register);\r
void XMEGANVM_SendAddress(const uint32_t AbsoluteAddress);\r
+ bool XMEGANVM_WaitWhileNVMBusBusy(void);\r
bool XMEGANVM_WaitWhileNVMControllerBusy(void);\r
bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest);\r
bool XMEGANVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize);\r
const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,\r
const uint8_t* WriteBuffer, const uint16_t WriteSize);\r
bool XMEGANVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address);\r
- bool XMEGANVM_WaitWhileNVMBusBusy(void);\r
\r
#endif\r
/* Enable TPI programming mode with the attached target */\r
XPROGTarget_EnableTargetTPI();\r
\r
- // TODO - enable NVM bus via KEY \r
+ /* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */\r
+ XPROGTarget_SendByte(TPI_CMD_SKEY); \r
+ for (uint8_t i = sizeof(TPI_NVMENABLE_KEY); i > 0; i--)\r
+ XPROGTarget_SendByte(TPI_NVMENABLE_KEY[i - 1]);\r
+\r
+ /* Wait until the NVM bus becomes active */\r
+ NVMBusEnabled = TINYNVM_WaitWhileNVMBusBusy();\r
}\r
\r
Endpoint_Write_Byte(CMD_XPROG);\r
}\r
else\r
{\r
- // TODO - Disable TPI via register\r
+ /* Clear the NVMEN bit in the TPI CONTROL register to disable TPI mode */\r
+ XPROGTarget_SendByte(TPI_CMD_SSTCS | TPI_CTRL_REG); \r
+ XPROGTarget_SendByte(0x00);\r
\r
XPROGTarget_DisableTargetTPI();\r
}\r