* The following is a list of known AVR USB development boards, which recommend using LUFA for the USB stack. Some of these\r
* are open design, and all are available for purchase as completed development boards suitable for project development.\r
*\r
- * - Micropendous, an open design/source set of AVR USB development boards: http://micropendous.org/\r
* - Benito #7, a no-frills USB board: http://www.dorkbotpdx.org/wiki/benito\r
* - Bumble-B, yet another AT90USB162 development board: http://fletchtronics.net/bumble-b\r
+ * - Micropendous, an open design/source set of AVR USB development boards: http://micropendous.org/\r
+ * - Nanduino, a do-it-yourself AT90USB162 board: http://www.makestuff.eu/wordpress/?page_id=569\r
+ * - Teensy and Teensy++, two other AVR USB development boards: http://www.pjrc.com/teensy/index.html\r
* - USB10 AKA "The Ferret", a AT90USB162 development board: http://www.soc-machines.com\r
* - USBFoo, an AT90USB162 based development board: http://shop.kernelconcepts.de/product_info.php?products_id=102\r
- * - Teensy and Teensy++, two other AVR USB development boards: http://www.pjrc.com/teensy/index.html\r
* \r
* \section Sec_LUFAProjects Projects Using LUFA (Hobbyist)\r
*\r
* The following are known hobbyist projects using LUFA. Most are open source, and show off interesting ways that the LUFA library\r
* can be incorporated into many different applications.\r
*\r
+ * - Arcade Controller: http://fletchtronics.net/arcade-controller-made-petunia\r
* - Bicycle POV: http://www.code.google.com/p/bicycleledpov/\r
* - CAMTRIG, a remote Camera Trigger device: http://code.astraw.com/projects/motmot/camtrig\r
* - "Fingerlicking Wingdinger" (WARNING: Bad Language if no Javascript), a MIDI controller - http://noisybox.net/electronics/wingdinger/\r
* \param[in] CRCCommand NVM CRC command to issue to the target\r
* \param[out] CRCDest CRC Destination when read from the target\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)\r
{\r
* \param[out] ReadBuffer Buffer to store read data into\r
* \param[in] ReadSize Number of bytes to read\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)\r
{\r
if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
return false;\r
\r
- /* Send the READNVM command to the NVM controller for reading of an aribtrary location */\r
+ /* Send the READNVM command to the NVM controller for reading of an arbitrary location */\r
PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
PDITarget_SendByte(NVM_CMD_READNVM);\r
NVMTarget_SendAddress(ReadAddress);\r
\r
/* Send the REPEAT command with the specified number of bytes to read */\r
- PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);\r
- PDITarget_SendByte(ReadSize & 0xFF);\r
- PDITarget_SendByte(ReadSize >> 8);\r
+ PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+ PDITarget_SendByte(ReadSize - 1);\r
\r
/* Send a LD command with indirect access and postincrement to read out the bytes */\r
PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
* \param[in] WriteBuffer Buffer to source data from\r
* \param[in] WriteSize Number of bytes to write\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
-bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)\r
+bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer)\r
{\r
- for (uint16_t i = 0; i < WriteSize; i++)\r
- {\r
- /* Wait until the NVM controller is no longer busy */\r
- if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
- return false;\r
+ /* Wait until the NVM controller is no longer busy */\r
+ if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+ return false;\r
\r
- /* Send the memory write command to the target */\r
- PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
- PDITarget_SendByte(WriteCommand);\r
+ /* Send the memory write command to the target */\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+ NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+ PDITarget_SendByte(WriteCommand);\r
\r
- /* Send each new memory byte to the memory to the target */\r
- PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendAddress(WriteAddress++);\r
- PDITarget_SendByte(*(WriteBuffer++));\r
- }\r
+ /* Send new memory byte to the memory to the target */\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+ NVMTarget_SendAddress(WriteAddress++);\r
+ PDITarget_SendByte(*(WriteBuffer++));\r
\r
return true;\r
}\r
* \param[in] WriteBuffer Buffer to source data from\r
* \param[in] WriteSize Number of bytes to write\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,\r
uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)\r
NVMTarget_SendAddress(WriteAddress);\r
\r
/* Send the REPEAT command with the specified number of bytes to write */\r
- PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);\r
- PDITarget_SendByte(WriteSize & 0xFF);\r
- PDITarget_SendByte(WriteSize >> 8);\r
+ PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+ PDITarget_SendByte(WriteSize - 1);\r
\r
/* Send a ST command with indirect access and postincrement to write the bytes */\r
PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
for (uint16_t i = 0; i < WriteSize; i++)\r
PDITarget_SendByte(*(WriteBuffer++));\r
-\r
- // TEMP\r
- PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
- GPIOR0 = PDITarget_ReceiveByte();\r
- if (!(GPIOR0 & (1 << 0)))\r
- JTAG_DEBUG_POINT();\r
- // END TEMP\r
}\r
\r
if (PageMode & XPRG_PAGEMODE_WRITE)\r
* \param[in] EraseCommand NVM erase command to send to the device\r
* \param[in] Address Address inside the memory space to erase\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)\r
{\r
NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
PDITarget_SendByte(EraseCommand);\r
\r
- /* Chip erase is handled seperately, since it's procedure is different to other erase types */\r
+ /* Chip erase is handled separately, since it's procedure is different to other erase types */\r
if (EraseCommand == NVM_CMD_CHIPERASE)\r
{\r
/* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
#define NVM_CMD_LOADFLASHPAGEBUFF 0x23\r
#define NVM_CMD_ERASEFLASHPAGEBUFF 0x26\r
#define NVM_CMD_ERASEFLASHPAGE 0x2B\r
- #define NVM_CMD_FLASHPAGEWRITE 0x2E\r
+ #define NVM_CMD_WRITEFLASHPAGE 0x2E\r
#define NVM_CMD_ERASEWRITEFLASH 0x2F\r
#define NVM_CMD_FLASHCRC 0x78\r
#define NVM_CMD_ERASEAPPSEC 0x20\r
bool NVMTarget_WaitWhileNVMControllerBusy(void);\r
bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest);\r
bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize);\r
- bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer,\r
- uint16_t WriteSize);\r
+ bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer);\r
bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,\r
uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize);\r
bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address);\r
#include "PDIProtocol.h"\r
\r
#if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)\r
-#warning PDI Programming Protocol support is incomplete and not currently suitable for general use.\r
-\r
/** Base absolute address for the target's NVM controller */\r
uint32_t XPROG_Param_NVMBase;\r
\r
\r
uint8_t EraseCommand = NVM_CMD_NOOP;\r
\r
+ /* Determine which NVM command to send to the device depending on the memory to erase */\r
if (Erase_XPROG_Params.MemoryType == XPRG_ERASE_CHIP)\r
EraseCommand = NVM_CMD_CHIPERASE;\r
else if (Erase_XPROG_Params.MemoryType == XPRG_ERASE_APP)\r
else if (Erase_XPROG_Params.MemoryType == XPRG_ERASE_USERSIG)\r
EraseCommand = NVM_CMD_ERASEUSERSIG;\r
\r
+ /* Erase the target memory, indicate timeout if ocurred */\r
if (!(NVMTarget_EraseMemory(EraseCommand, Erase_XPROG_Params.Address)))\r
ReturnStatus = XPRG_ERR_TIMEOUT;\r
\r
Endpoint_ClearOUT();\r
Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);\r
\r
-\r
- uint8_t WriteCommand = NVM_CMD_NOOP;\r
- uint8_t WriteBuffCommand = NVM_CMD_NOOP;\r
- uint8_t EraseBuffCommand = NVM_CMD_NOOP;\r
- bool PagedMemory = false;\r
+ /* Assume FLASH page programming by default, as it is the common case */\r
+ uint8_t WriteCommand = NVM_CMD_WRITEFLASHPAGE;\r
+ uint8_t WriteBuffCommand = NVM_CMD_LOADFLASHPAGEBUFF;\r
+ uint8_t EraseBuffCommand = NVM_CMD_ERASEFLASHPAGEBUFF;\r
+ bool PagedMemory = true;\r
\r
if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_APPL)\r
{\r
- WriteCommand = NVM_CMD_ERASEWRITEFLASH;\r
- WriteBuffCommand = NVM_CMD_LOADFLASHPAGEBUFF;\r
- EraseBuffCommand = NVM_CMD_ERASEFLASHPAGEBUFF;\r
- PagedMemory = true;\r
+ WriteCommand = NVM_CMD_WRITEAPPSECPAGE;\r
}\r
else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_BOOT)\r
{\r
- WriteCommand = NVM_CMD_ERASEWRITEFLASH;\r
- WriteBuffCommand = NVM_CMD_LOADFLASHPAGEBUFF;\r
- EraseBuffCommand = NVM_CMD_ERASEFLASHPAGEBUFF;\r
- PagedMemory = true;\r
+ WriteCommand = NVM_CMD_WRITEBOOTSECPAGE;\r
}\r
else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_EEPROM)\r
{\r
- WriteCommand = NVM_CMD_ERASEWRITEEEPROMPAGE;\r
+ WriteCommand = NVM_CMD_WRITEEEPROMPAGE;\r
WriteBuffCommand = NVM_CMD_LOADEEPROMPAGEBUFF;\r
EraseBuffCommand = NVM_CMD_ERASEEEPROMPAGEBUFF;\r
- PagedMemory = true;\r
}\r
else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_USERSIG)\r
{\r
+ /* User signature is paged, but needs us to manually indicate the mode bits since the host doesn't set them */\r
+ WriteMemory_XPROG_Params.PageMode = (XPRG_PAGEMODE_ERASE | XPRG_PAGEMODE_WRITE);\r
WriteCommand = NVM_CMD_WRITEUSERSIG;\r
- WriteBuffCommand = NVM_CMD_LOADFLASHPAGEBUFF;\r
- EraseBuffCommand = NVM_CMD_ERASEFLASHPAGEBUFF;\r
- PagedMemory = true;\r
}\r
else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_FUSE)\r
{\r
- WriteCommand = NVM_CMD_WRITEFUSE;\r
+ WriteCommand = NVM_CMD_WRITEFUSE;\r
+ PagedMemory = false;\r
}\r
else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_LOCKBITS)\r
{\r
- WriteCommand = NVM_CMD_WRITELOCK;\r
+ WriteCommand = NVM_CMD_WRITELOCK;\r
+ PagedMemory = false;\r
}\r
\r
- if (PagedMemory)\r
- {\r
- if (!(NVMTarget_WritePageMemory(WriteBuffCommand, EraseBuffCommand, WriteCommand, \r
- WriteMemory_XPROG_Params.PageMode, WriteMemory_XPROG_Params.Address,\r
- WriteMemory_XPROG_Params.ProgData, WriteMemory_XPROG_Params.Length)))\r
- {\r
- ReturnStatus = XPRG_ERR_TIMEOUT;\r
- }\r
- }\r
- else\r
+ /* Send the appropriate memory write commands to the device, indicate timeout if occurred */\r
+ if ((PagedMemory && !NVMTarget_WritePageMemory(WriteBuffCommand, EraseBuffCommand, WriteCommand, \r
+ WriteMemory_XPROG_Params.PageMode, WriteMemory_XPROG_Params.Address,\r
+ WriteMemory_XPROG_Params.ProgData, WriteMemory_XPROG_Params.Length)) ||\r
+ (!PagedMemory && !NVMTarget_WriteByteMemory(WriteCommand, WriteMemory_XPROG_Params.Address,\r
+ WriteMemory_XPROG_Params.ProgData)))\r
{\r
- if (!(NVMTarget_WriteByteMemory(WriteCommand, WriteMemory_XPROG_Params.Address, WriteMemory_XPROG_Params.ProgData,\r
- WriteMemory_XPROG_Params.Length)))\r
- {\r
- ReturnStatus = XPRG_ERR_TIMEOUT;\r
- }\r
+ ReturnStatus = XPRG_ERR_TIMEOUT;\r
}\r
\r
Endpoint_Write_Byte(CMD_XPROG);\r
Endpoint_ClearOUT();\r
Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);\r
\r
- uint8_t ReadBuffer[ReadMemory_XPROG_Params.Length];\r
+ uint8_t ReadBuffer[256];\r
\r
+ /* Read the target's memory, indicate timeout if occurred */\r
if (!(NVMTarget_ReadMemory(ReadMemory_XPROG_Params.Address, ReadBuffer, ReadMemory_XPROG_Params.Length)))\r
ReturnStatus = XPRG_ERR_TIMEOUT;\r
\r
uint8_t CRCCommand = NVM_CMD_NOOP;\r
uint32_t MemoryCRC;\r
\r
+ /* Determine which NVM command to send to the device depending on the memory to CRC */\r
if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_APP)\r
CRCCommand = NVM_CMD_APPCRC;\r
else if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_BOOT)\r
else\r
CRCCommand = NVM_CMD_FLASHCRC;\r
\r
+ /* Perform and retrieve the memory CRC, indicate timeout if occurred */\r
if (!(NVMTarget_GetMemoryCRC(CRCCommand, &MemoryCRC)))\r
ReturnStatus = XPRG_ERR_TIMEOUT;\r
\r
\r
uint8_t XPROGParam = Endpoint_Read_Byte();\r
\r
+ /* Determine which parameter is being set, store the new parameter value */\r
if (XPROGParam == XPRG_PARAM_NVMBASE)\r
XPROG_Param_NVMBase = Endpoint_Read_DWord_BE();\r
else if (XPROGParam == XPRG_PARAM_EEPPAGESIZE)\r
#define XPRG_PROTOCOL_PDI 0x00\r
#define XPRG_PROTOCOL_JTAG 0x01\r
\r
- #define XPRG_PAGEMODE_WRITE (1 << 0)\r
- #define XPRG_PAGEMODE_ERASE (1 << 1)\r
+ #define XPRG_PAGEMODE_WRITE (1 << 1)\r
+ #define XPRG_PAGEMODE_ERASE (1 << 0)\r
\r
/* External Variables: */\r
extern uint32_t XPROG_Param_NVMBase;\r
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