Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Sends the given NVM register address to the target.
  42  *
  43  *  \param[in] Register  NVM register whose absolute address is to be sent
  44  */
  45 void NVMTarget_SendNVMRegAddress(uint8_t Register)
  46 {
  47         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  48         uint32_t Address = XPROG_Param_NVMBase | Register;
  49
  50         /* Send the calculated 32-bit address to the target, LSB first */
  51         PDITarget_SendByte(Address &  0xFF);
  52         PDITarget_SendByte(Address >> 8);
  53         PDITarget_SendByte(Address >> 16);
  54         PDITarget_SendByte(Address >> 24);
  55 }
  56
  57 /** Sends the given 32-bit absolute address to the target.
  58  *
  59  *  \param[in] AbsoluteAddress  Absolute address to send to the target
  60  */
  61 void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
  62 {
  63         /* Send the given 32-bit address to the target, LSB first */
  64         PDITarget_SendByte(AbsoluteAddress &  0xFF);
  65         PDITarget_SendByte(AbsoluteAddress >> 8);
  66         PDITarget_SendByte(AbsoluteAddress >> 16);
  67         PDITarget_SendByte(AbsoluteAddress >> 24);
  68 }
  69
  70 /** Waits while the target's NVM controller is busy performing an operation, exiting if the
  71  *  timeout period expires.
  72  *
  73  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
  74  */
  75 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  76 {
  77         TCNT0 = 0;
  78
  79         /* Poll the NVM STATUS register while the NVM controller is busy */
  80         while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
  81         {
  82                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  83                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  84                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  85
  86                 /* Check to see if the BUSY flag is still set */
  87                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  88                   return true;
  89         }
  90
  91         return false;
  92 }
  93
  94 /** Retrieves the CRC value of the given memory space.
  95  *
  96  *  \param[in]  CRCCommand  NVM CRC command to issue to the target
  97  *  \param[out] CRCDest     CRC Destination when read from the target
  98  *
  99  *  \return Boolean true if the command sequence complete successfully
 100  */
 101 bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)
 102 {
 103         /* Wait until the NVM controller is no longer busy */
 104         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 105           return false;
 106
 107         /* Set the NVM command to the correct CRC read command */
 108         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 109         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 110         PDITarget_SendByte(CRCCommand);
 111
 112         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
 113         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 114         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 115         PDITarget_SendByte(1 << 0);
 116
 117         /* Wait until the NVM bus is ready again */
 118         if (!(PDITarget_WaitWhileNVMBusBusy()))
 119           return false;
 120
 121         /* Wait until the NVM controller is no longer busy */
 122         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 123           return false;
 124
 125         *CRCDest = 0;
 126
 127         /* Read the first generated CRC byte value */
 128         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 129         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 130         *CRCDest  = PDITarget_ReceiveByte();
 131
 132         /* Read the second generated CRC byte value */
 133         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 134         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 135         *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 136
 137         /* Read the third generated CRC byte value */
 138         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 139         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 140         *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 141
 142         return true;
 143 }
 144
 145 /** Reads memory from the target's memory spaces.
 146  *
 147  *  \param[in]  ReadAddress  Start address to read from within the target's address space
 148  *  \param[out] ReadBuffer   Buffer to store read data into
 149  *  \param[in]  ReadSize     Number of bytes to read
 150  *
 151  *  \return Boolean true if the command sequence complete successfully
 152  */
 153 bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
 154 {
 155         /* Wait until the NVM controller is no longer busy */
 156         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 157           return false;
 158
 159         /* Send the READNVM command to the NVM controller for reading of an arbitrary location */
 160         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 161         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 162         PDITarget_SendByte(NVM_CMD_READNVM);
 163
 164         /* Load the PDI pointer register with the start address we want to read from */
 165         PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 166         NVMTarget_SendAddress(ReadAddress);
 167
 168         /* Send the REPEAT command with the specified number of bytes to read */
 169         PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 170         PDITarget_SendByte(ReadSize - 1);
 171
 172         /* Send a LD command with indirect access and postincrement to read out the bytes */
 173         PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 174         for (uint16_t i = 0; i < ReadSize; i++)
 175           *(ReadBuffer++) = PDITarget_ReceiveByte();
 176
 177         return true;
 178 }
 179
 180 /** Writes byte addressed memory to the target's memory spaces.
 181  *
 182  *  \param[in]  WriteCommand  Command to send to the device to write each memory byte
 183  *  \param[in]  WriteAddress  Start address to write to within the target's address space
 184  *  \param[in]  WriteBuffer   Buffer to source data from
 185  *  \param[in]  WriteSize     Number of bytes to write
 186  *
 187  *  \return Boolean true if the command sequence complete successfully
 188  */
 189 bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer)
 190 {
 191         /* Wait until the NVM controller is no longer busy */
 192         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 193           return false;
 194
 195         /* Send the memory write command to the target */
 196         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 197         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 198         PDITarget_SendByte(WriteCommand);
 199
 200         /* Send new memory byte to the memory to the target */
 201         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 202         NVMTarget_SendAddress(WriteAddress++);
 203         PDITarget_SendByte(*(WriteBuffer++));
 204
 205         return true;
 206 }
 207
 208 /** Writes page addressed memory to the target's memory spaces.
 209  *
 210  *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer
 211  *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer
 212  *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory
 213  *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page
 214  *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space
 215  *  \param[in]  WriteBuffer       Buffer to source data from
 216  *  \param[in]  WriteSize         Number of bytes to write
 217  *
 218  *  \return Boolean true if the command sequence complete successfully
 219  */
 220 bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,
 221                                uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
 222 {
 223         if (PageMode & XPRG_PAGEMODE_ERASE)
 224         {
 225                 /* Wait until the NVM controller is no longer busy */
 226                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 227                   return false;
 228
 229                 /* Send the memory buffer erase command to the target */
 230                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 231                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 232                 PDITarget_SendByte(EraseBuffCommand);
 233
 234                 /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
 235                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 236                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 237                 PDITarget_SendByte(1 << 0);
 238         }
 239
 240         if (WriteSize)
 241         {
 242                 /* Wait until the NVM controller is no longer busy */
 243                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 244                   return false;
 245
 246                 /* Send the memory buffer write command to the target */
 247                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 248                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 249                 PDITarget_SendByte(WriteBuffCommand);
 250
 251                 /* Load the PDI pointer register with the start address we want to write to */
 252                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 253                 NVMTarget_SendAddress(WriteAddress);
 254
 255                 /* Send the REPEAT command with the specified number of bytes to write */
 256                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 257                 PDITarget_SendByte(WriteSize - 1);
 258
 259                 /* Send a ST command with indirect access and postincrement to write the bytes */
 260                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 261                 for (uint16_t i = 0; i < WriteSize; i++)
 262                   PDITarget_SendByte(*(WriteBuffer++));
 263         }
 264
 265         if (PageMode & XPRG_PAGEMODE_WRITE)
 266         {
 267                 /* Wait until the NVM controller is no longer busy */
 268                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 269                   return false;
 270
 271                 /* Send the memory write command to the target */
 272                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 273                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 274                 PDITarget_SendByte(WritePageCommand);
 275
 276                 /* Send the address of the first page location to write the memory page */
 277                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 278                 NVMTarget_SendAddress(WriteAddress);
 279                 PDITarget_SendByte(0x00);
 280         }
 281
 282         return true;
 283 }
 284
 285 /** Erases a specific memory space of the target.
 286  *
 287  *  \param[in] EraseCommand  NVM erase command to send to the device
 288  *  \param[in] Address  Address inside the memory space to erase
 289  *
 290  *  \return Boolean true if the command sequence complete successfully
 291  */
 292 bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
 293 {
 294         /* Wait until the NVM controller is no longer busy */
 295         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 296           return false;
 297
 298         /* Send the memory erase command to the target */
 299         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 300         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 301         PDITarget_SendByte(EraseCommand);
 302
 303         /* Chip erase is handled separately, since it's procedure is different to other erase types */
 304         if (EraseCommand == NVM_CMD_CHIPERASE)
 305         {
 306                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 307                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 308                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 309                 PDITarget_SendByte(1 << 0);
 310         }
 311         else
 312         {
 313                 /* Other erase modes just need us to address a byte within the target memory space */
 314                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 315                 NVMTarget_SendAddress(Address);
 316                 PDITarget_SendByte(0x00);
 317         }
 318
 319         /* Wait until the NVM bus is ready again */
 320         if (!(PDITarget_WaitWhileNVMBusBusy()))
 321           return false;
 322
 323         return true;
 324 }
 325
 326 #endif