When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL...

diff --git a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
index 571ab6c..9f688db 100644 (file)
--- a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
+++ b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
@@ -68,7 +68,7 @@ void USB_Init(
        if (!(USB_Options & USB_OPT_MANUAL_PLL))
        {
                #if defined(USB_SERIES_4_AVR)
        if (!(USB_Options & USB_OPT_MANUAL_PLL))
        {
                #if defined(USB_SERIES_4_AVR)

-               PLLFRQ = ((1 << PLLUSB) | (1 << PDIV3) | (1 << PDIV1));
+               PLLFRQ = (1 << PDIV2);

                #endif
        }
 
                #endif
        }
 

diff --git a/LUFA/ManPages/ChangeLog.txt b/LUFA/ManPages/ChangeLog.txt
index 55e1241..b3bda78 100644 (file)
--- a/LUFA/ManPages/ChangeLog.txt
+++ b/LUFA/ManPages/ChangeLog.txt
@@ -15,7 +15,8 @@
   *
   *  <b>Changed:</b>
   *  - Core:
   *
   *  <b>Changed:</b>
   *  - Core:

-  *   - None
+  *   - When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not
+  *     a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale)

   *  - Library Applications:
   *   - None
   *
   *  - Library Applications:
   *   - None
   *