* Note that this design currently has the following limitations:\r
* - Minimum ISP target clock speed of 500KHz due to hardware SPI module prescaler limitations\r
* - No reversed/shorted target connector detection and notification\r
- * - Very slow TPI and PDI programming when in software emulated USART mode\r
+ * - A seperate header is required for each of the ISP, PDI and TPI programming protocols that the user wishes to use\r
*\r
* On AVR models with an ADC converter, AVCC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be\r
* set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models\r
* without an ADC converter, VTARGET will report a fixed 5V level at all times.\r
*\r
- * When compiled for the XPLAIN board target, this will automatically configure itself for the correct connections to the\r
- * XPLAIN's XMEGA AVR, and will enable hardware PDI/TPI only programming support (since ISP mode is not needed). Note that\r
- * the first revision XPLAIN board lacks a bootloader on the AT90USB1287, and thus for this firmware to be loaded, an external\r
- * programmer will be required.\r
- *\r
* While this application can be compiled for USB AVRs with as little as 8KB of FLASH, for full functionality 16KB or more\r
* of FLASH is required. On 8KB devices, ISP or PDI/TPI programming support can be disabled to reduce program size.\r
*\r
* <td><b>PDI 6 Pin Layout:</b></td>\r
* </tr>\r
* <tr>\r
- * <td>MISO <b><sup>2</sup></b></td>\r
+ * <td>Tx/Rx <b><sup>2</sup></b></td>\r
* <td>DATA</td>\r
* <td>1</td>\r
* </tr>\r
* <td>4</td>\r
* </tr>\r
* <tr>\r
- * <td>PORTx.y <b><sup>2, 3</sup></b></td>\r
+ * <td>XCLK</td>\r
* <td>CLOCK</td>\r
* <td>5</td>\r
* </tr>\r
* </table>\r
*\r
* <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n\r
- * <b><sup>2</sup></b> <i>When XPROG_VIA_HARDWARE_USART is set, the AVR's Tx and Rx become the DATA line when connected together\r
- * via a pair of 220 ohm resistors, and the AVR's XCK pin becomes CLOCK.</i> \n\r
- * <b><sup>3</sup></b> <i>See AUX line related tokens in the \ref SSec_Options section</i>\r
+ * <b><sup>2</sup></b> <i>The AVR's Tx and Rx become the DATA line when connected together via a pair of 220 ohm resistors</i> \n\r
*\r
* \section Sec_TPI TPI Connections\r
* Connections to the device for TPI programming<b><sup>1</sup></b> (when enabled):\r
* <td><b>TPI 6 Pin Layout:</b></td>\r
* </tr>\r
* <tr>\r
- * <td>MISO <b><sup>2</sup></b></td>\r
+ * <td>Tx/Rx <b><sup>2</sup></b></td>\r
* <td>DATA</td>\r
* <td>1</td>\r
* </tr>\r
* <td>2</td>\r
* </tr>\r
* <tr>\r
- * <td>SCLK <b><sup>2</sup></b></td>\r
+ * <td>XCLK <b><sup>2</sup></b></td>\r
* <td>CLOCK</td>\r
* <td>3</td>\r
* </tr>\r
* </table>\r
*\r
* <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n\r
- * <b><sup>2</sup></b> <i>When XPROG_VIA_HARDWARE_USART is set, the AVR's Tx and Rx become the DATA line when connected together\r
- * via a pair of 220 ohm resistors, and the AVR's XCK pin becomes CLOCK.</i> \n\r
+ * <b><sup>2</sup></b> <i>The AVR's Tx and Rx become the DATA line when connected together via a pair of 220 ohm resistors</i> \n\r
* <b><sup>3</sup></b> <i>See AUX line related tokens in the \ref SSec_Options section</i>\r
*\r
* \section SSec_Options Project Options\r
* <td>Define to enable PDI and TPI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td> \r
* </tr>\r
* <tr>\r
- * <td>XPROG_VIA_HARDWARE_USART</td>\r
- * <td>Makefile CDEFS</td>\r
- * <td>Define to force the PDI and TPI protocols (when enabled) to use the much faster hardware USART instead of bit-banging\r
- * to match the official AVRISP pinout. This breaks pinout compatibility with the official AVRISP MKII (and requires \r
- * seperate ISP, PDI, and TPI programming headers) but increases programming speed dramatically.\r
- * <i>Ignored when compiled for the XPLAIN board.</i></td> \r
- * </tr>\r
- * <tr>\r
* <td>NO_VTARGET_DETECT</td>\r
* <td>Makefile CDEFS</td>\r
* <td>Define to disable VTARGET sampling and reporting on AVR models with an ADC converter. This will cause the programmer\r
#if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)\r
\r
/** Flag to indicate if the USART is currently in Tx or Rx mode. */\r
-volatile bool IsSending;\r
-\r
-#if !defined(XPROG_VIA_HARDWARE_USART)\r
-/** Software USART raw frame bits for transmission/reception. */\r
-volatile uint16_t SoftUSART_Data;\r
-\r
-/** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */\r
-#define SoftUSART_BitCount GPIOR2\r
-\r
-\r
-/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */\r
-ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
-{\r
- /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
- BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;\r
-\r
- /* If not sending or receiving, just exit */\r
- if (!(SoftUSART_BitCount))\r
- return;\r
-\r
- /* Check to see if we are at a rising or falling edge of the clock */\r
- if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
- {\r
- /* If at rising clock edge and we are in send mode, abort */\r
- if (IsSending)\r
- return;\r
- \r
- /* Wait for the start bit when receiving */\r
- if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
- return;\r
-\r
- /* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
- * be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */\r
- if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
- ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
-\r
- SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--;\r
- }\r
- else\r
- {\r
- /* If at falling clock edge and we are in receive mode, abort */\r
- if (!IsSending)\r
- return;\r
-\r
- /* Set the data line to the next bit value */\r
- if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)\r
- BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- else\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; \r
-\r
- SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--; \r
- }\r
-}\r
-\r
-/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r
-ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
-{\r
- /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
- BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;\r
-\r
- /* If not sending or receiving, just exit */\r
- if (!(SoftUSART_BitCount))\r
- return;\r
-\r
- /* Check to see if we are at a rising or falling edge of the clock */\r
- if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)\r
- {\r
- /* If at rising clock edge and we are in send mode, abort */\r
- if (IsSending)\r
- return;\r
- \r
- /* Wait for the start bit when receiving */\r
- if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))\r
- return;\r
- \r
- /* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
- * be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */\r
- if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)\r
- ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
-\r
- SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--;\r
- }\r
- else\r
- {\r
- /* If at falling clock edge and we are in receive mode, abort */\r
- if (!IsSending)\r
- return;\r
-\r
- /* Set the data line to the next bit value */\r
- if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)\r
- BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
- else\r
- BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK; \r
-\r
- SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--;\r
- }\r
-}\r
-#endif\r
+volatile bool IsSending;\r
\r
/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */\r
void XPROGTarget_EnableTargetPDI(void)\r
{\r
IsSending = false;\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
-#else\r
- /* Set DATA and CLOCK lines to outputs */\r
- BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;\r
- \r
- /* Set DATA line low for at least 1ms to ensure that the device is ready for PDI mode to be entered */\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
- _delay_ms(1);\r
-\r
- /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
- BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- _delay_us(1);\r
-\r
- /* Fire timer compare channel A ISR to manage the software USART */\r
- OCR1A = BITS_BETWEEN_USART_CLOCKS;\r
- TCCR1B = (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << OCIE1A);\r
-#endif\r
\r
/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
XPROGTarget_SendBreak();\r
AUX_LINE_PORT &= ~AUX_LINE_MASK;\r
_delay_us(1);\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
-#else\r
- /* Set DATA and CLOCK lines to outputs */\r
- BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;\r
- BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;\r
- \r
- /* Set DATA line high for idle state */\r
- BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
-\r
- /* Fire timer capture channel ISR to manage the software USART */\r
- ICR1 = BITS_BETWEEN_USART_CLOCKS;\r
- TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << ICIE1);\r
-#endif\r
\r
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
XPROGTarget_SendBreak();\r
/* Switch to Rx mode to ensure that all pending transmissions are complete */\r
XPROGTarget_SetRxMode();\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
UCSR1A = ((1 << TXC1) | (1 << RXC1));\r
UCSR1B = 0;\r
/* Tristate all pins */\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
-#else\r
- /* Turn off software USART management timer */\r
- TCCR1B = 0;\r
-\r
- /* Set DATA and CLOCK lines to inputs */\r
- BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;\r
- \r
- /* Tristate DATA and CLOCK lines */\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK; \r
-#endif\r
}\r
\r
/** Disables the target's TPI interface, exits programming mode and starts the target's application. */\r
/* Switch to Rx mode to ensure that all pending transmissions are complete */\r
XPROGTarget_SetRxMode();\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
UCSR1B = 0;\r
/* Set all USART lines as input, tristate */\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
-#else\r
- /* Turn off software USART management timer */\r
- TCCR1B = 0;\r
-\r
- /* Set DATA and CLOCK lines to inputs */\r
- BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
- BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
- \r
- /* Tristate DATA and CLOCK lines */\r
- BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
- BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;\r
-#endif\r
\r
/* Tristate target /RESET line */\r
AUX_LINE_DDR &= ~AUX_LINE_MASK;\r
if (!(IsSending))\r
XPROGTarget_SetTxMode();\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait until there is space in the hardware Tx buffer before writing */\r
while (!(UCSR1A & (1 << UDRE1)));\r
UCSR1A |= (1 << TXC1);\r
UDR1 = Byte;\r
-#else\r
- /* Calculate the new USART frame data here while while we wait for a previous byte (if any) to finish sending */\r
- uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));\r
-\r
- /* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */\r
- uint8_t ParityData = Byte;\r
- while (ParityData)\r
- {\r
- NewUSARTData ^= (1 << 9);\r
- ParityData &= (ParityData - 1);\r
- }\r
-\r
- /* Wait until transmitter is idle before writing new data */\r
- while (SoftUSART_BitCount);\r
-\r
- /* Data shifted out LSB first, START DATA PARITY STOP STOP */\r
- SoftUSART_Data = NewUSARTData;\r
- SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
-#endif\r
\r
if (TimeoutMSRemaining)\r
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
if (IsSending)\r
XPROGTarget_SetRxMode();\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait until a byte has been received before reading */\r
while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining);\r
\r
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
\r
return UDR1;\r
-#else\r
- /* Wait until a byte has been received before reading */\r
- SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
- while (SoftUSART_BitCount && TimeoutMSRemaining);\r
-\r
- if (TimeoutMSRemaining)\r
- TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
-\r
- /* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */\r
- return (uint8_t)SoftUSART_Data;\r
-#endif\r
}\r
\r
/** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */\r
if (!(IsSending))\r
XPROGTarget_SetTxMode();\r
\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Need to do nothing for a full frame to send a BREAK */\r
for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)\r
{\r
while (PIND & (1 << 5));\r
while (!(PIND & (1 << 5)));\r
}\r
-#else\r
- while (SoftUSART_BitCount);\r
-\r
- /* Need to do nothing for a full frame to send a BREAK */\r
- SoftUSART_Data = 0x0FFF;\r
- SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
-#endif\r
\r
if (TimeoutMSRemaining)\r
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
\r
static void XPROGTarget_SetTxMode(void)\r
{\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait for a full cycle of the clock */\r
while (PIND & (1 << 5));\r
while (!(PIND & (1 << 5)));\r
UCSR1B |= (1 << TXEN1);\r
\r
IsSending = true;\r
-#else\r
- while (SoftUSART_BitCount && TimeoutMSRemaining);\r
- \r
- /* Wait for a full cycle of the clock */\r
- SoftUSART_Data = 0x0001;\r
- SoftUSART_BitCount = 1;\r
- while (SoftUSART_BitCount);\r
-\r
- if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
- {\r
- BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;\r
- }\r
- else\r
- {\r
- BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
- BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK; \r
- }\r
-#endif\r
\r
if (TimeoutMSRemaining)\r
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
\r
static void XPROGTarget_SetRxMode(void)\r
{\r
-#if defined(XPROG_VIA_HARDWARE_USART)\r
while (!(UCSR1A & (1 << TXC1)));\r
UCSR1A |= (1 << TXC1);\r
\r
\r
DDRD &= ~(1 << 3);\r
PORTD &= ~(1 << 3);\r
-#else\r
- while (SoftUSART_BitCount && TimeoutMSRemaining);\r
-\r
- if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
- {\r
- BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
-\r
- /* Wait until DATA line has been pulled up to idle by the target */\r
- while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining);\r
- }\r
- else\r
- {\r
- BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
- BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
-\r
- /* Wait until DATA line has been pulled up to idle by the target */\r
- while (!(BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK) && TimeoutMSRemaining);\r
- } \r
-#endif\r
\r
if (TimeoutMSRemaining)\r
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
projects / pub / lufa.git / commitdiff