Update file contributor copyrights for 2012.
[pub/lufa.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c
1 /*
2 LUFA Library
3 Copyright (C) Dean Camera, 2012.
4
5 dean [at] fourwalledcubicle [dot] com
6 www.lufa-lib.org
7 */
8
9 /*
10 Copyright 2012 Dean Camera (dean [at] fourwalledcubicle [dot] com)
11
12 Permission to use, copy, modify, distribute, and sell this
13 software and its documentation for any purpose is hereby granted
14 without fee, provided that the above copyright notice appear in
15 all copies and that both that the copyright notice and this
16 permission notice and warranty disclaimer appear in supporting
17 documentation, and that the name of the author not be used in
18 advertising or publicity pertaining to distribution of the
19 software without specific, written prior permission.
20
21 The author disclaim all warranties with regard to this
22 software, including all implied warranties of merchantability
23 and fitness. In no event shall the author be liable for any
24 special, indirect or consequential damages or any damages
25 whatsoever resulting from loss of use, data or profits, whether
26 in an action of contract, negligence or other tortious action,
27 arising out of or in connection with the use or performance of
28 this software.
29 */
30
31 /** \file
32 *
33 * Target-related functions for the PDI Protocol decoder.
34 */
35
36 #define INCLUDE_FROM_XPROGTARGET_C
37 #include "XPROGTarget.h"
38
39 #if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)
40
41 /** Flag to indicate if the USART is currently in Tx or Rx mode. */
42 bool IsSending;
43
44 /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
45 void XPROGTarget_EnableTargetPDI(void)
46 {
47 IsSending = false;
48
49 /* Set Tx and XCK as outputs, Rx as input */
50 DDRD |= (1 << 5) | (1 << 3);
51 DDRD &= ~(1 << 2);
52
53 /* Set DATA line high for at least 90ns to disable /RESET functionality */
54 PORTD |= (1 << 3);
55 _delay_us(1);
56
57 /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
58 UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
59 UCSR1B = (1 << TXEN1);
60 UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
61
62 /* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
63 XPROGTarget_SendIdle();
64 XPROGTarget_SendIdle();
65 }
66
67 /** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
68 void XPROGTarget_EnableTargetTPI(void)
69 {
70 IsSending = false;
71
72 /* Set /RESET line low for at least 400ns to enable TPI functionality */
73 AUX_LINE_DDR |= AUX_LINE_MASK;
74 AUX_LINE_PORT &= ~AUX_LINE_MASK;
75 _delay_us(1);
76
77 /* Set Tx and XCK as outputs, Rx as input */
78 DDRD |= (1 << 5) | (1 << 3);
79 DDRD &= ~(1 << 2);
80
81 /* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
82 UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
83 UCSR1B = (1 << TXEN1);
84 UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
85
86 /* Send two IDLEs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
87 XPROGTarget_SendIdle();
88 XPROGTarget_SendIdle();
89 }
90
91 /** Disables the target's PDI interface, exits programming mode and starts the target's application. */
92 void XPROGTarget_DisableTargetPDI(void)
93 {
94 /* Switch to Rx mode to ensure that all pending transmissions are complete */
95 if (IsSending)
96 XPROGTarget_SetRxMode();
97
98 /* Turn off receiver and transmitter of the USART, clear settings */
99 UCSR1A = ((1 << TXC1) | (1 << RXC1));
100 UCSR1B = 0;
101 UCSR1C = 0;
102
103 /* Tristate all pins */
104 DDRD &= ~((1 << 5) | (1 << 3));
105 PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
106 }
107
108 /** Disables the target's TPI interface, exits programming mode and starts the target's application. */
109 void XPROGTarget_DisableTargetTPI(void)
110 {
111 /* Switch to Rx mode to ensure that all pending transmissions are complete */
112 if (IsSending)
113 XPROGTarget_SetRxMode();
114
115 /* Turn off receiver and transmitter of the USART, clear settings */
116 UCSR1A |= (1 << TXC1) | (1 << RXC1);
117 UCSR1B = 0;
118 UCSR1C = 0;
119
120 /* Set all USART lines as inputs, tristate */
121 DDRD &= ~((1 << 5) | (1 << 3));
122 PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
123
124 /* Tristate target /RESET line */
125 AUX_LINE_DDR &= ~AUX_LINE_MASK;
126 AUX_LINE_PORT &= ~AUX_LINE_MASK;
127 }
128
129 /** Sends a byte via the USART.
130 *
131 * \param[in] Byte Byte to send through the USART
132 */
133 void XPROGTarget_SendByte(const uint8_t Byte)
134 {
135 /* Switch to Tx mode if currently in Rx mode */
136 if (!(IsSending))
137 XPROGTarget_SetTxMode();
138
139 /* Wait until there is space in the hardware Tx buffer before writing */
140 while (!(UCSR1A & (1 << UDRE1)));
141 UCSR1A |= (1 << TXC1);
142 UDR1 = Byte;
143 }
144
145 /** Receives a byte via the hardware USART, blocking until data is received or timeout expired.
146 *
147 * \return Received byte from the USART
148 */
149 uint8_t XPROGTarget_ReceiveByte(void)
150 {
151 /* Switch to Rx mode if currently in Tx mode */
152 if (IsSending)
153 XPROGTarget_SetRxMode();
154
155 /* Wait until a byte has been received before reading */
156 while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired));
157
158 /* Byte of data received - reset the timeout */
159 wdt_reset();
160
161 return UDR1;
162 }
163
164 /** Sends an IDLE via the USART to the attached target, consisting of a full frame of idle bits. */
165 void XPROGTarget_SendIdle(void)
166 {
167 /* Switch to Tx mode if currently in Rx mode */
168 if (!(IsSending))
169 XPROGTarget_SetTxMode();
170
171 /* Need to do nothing for a full frame to send an IDLE */
172 for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
173 {
174 /* Wait for a full cycle of the clock */
175 while (PIND & (1 << 5));
176 while (!(PIND & (1 << 5)));
177 while (PIND & (1 << 5));
178 }
179 }
180
181 static void XPROGTarget_SetTxMode(void)
182 {
183 /* Wait for a full cycle of the clock */
184 while (PIND & (1 << 5));
185 while (!(PIND & (1 << 5)));
186 while (PIND & (1 << 5));
187
188 PORTD |= (1 << 3);
189 DDRD |= (1 << 3);
190
191 UCSR1B &= ~(1 << RXEN1);
192 UCSR1B |= (1 << TXEN1);
193
194 IsSending = true;
195 }
196
197 static void XPROGTarget_SetRxMode(void)
198 {
199 while (!(UCSR1A & (1 << TXC1)));
200 UCSR1A |= (1 << TXC1);
201
202 UCSR1B &= ~(1 << TXEN1);
203 UCSR1B |= (1 << RXEN1);
204
205 DDRD &= ~(1 << 3);
206 PORTD &= ~(1 << 3);
207
208 IsSending = false;
209 }
210
211 #endif
212