Update copyrights for 2018.
[pub/lufa.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c
1 /*
2 LUFA Library
3 Copyright (C) Dean Camera, 2018.
4
5 dean [at] fourwalledcubicle [dot] com
6 www.lufa-lib.org
7 */
8
9 /*
10 Copyright 2018 Dean Camera (dean [at] fourwalledcubicle [dot] com)
11
12 Permission to use, copy, modify, distribute, and sell this
13 software and its documentation for any purpose is hereby granted
14 without fee, provided that the above copyright notice appear in
15 all copies and that both that the copyright notice and this
16 permission notice and warranty disclaimer appear in supporting
17 documentation, and that the name of the author not be used in
18 advertising or publicity pertaining to distribution of the
19 software without specific, written prior permission.
20
21 The author disclaims all warranties with regard to this
22 software, including all implied warranties of merchantability
23 and fitness. In no event shall the author be liable for any
24 special, indirect or consequential damages or any damages
25 whatsoever resulting from loss of use, data or profits, whether
26 in an action of contract, negligence or other tortious action,
27 arising out of or in connection with the use or performance of
28 this software.
29 */
30
31 /** \file
32 *
33 * Target-related functions for the PDI Protocol decoder.
34 */
35
36 #define INCLUDE_FROM_XPROGTARGET_C
37 #include "XPROGTarget.h"
38
39 #if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)
40
41 /** Flag to indicate if the USART is currently in Tx or Rx mode. */
42 static bool IsSending;
43
44 /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
45 void XPROGTarget_EnableTargetPDI(void)
46 {
47 IsSending = false;
48
49 /* Set Tx and XCK as outputs, Rx as input */
50 DDRD |= (1 << 5) | (1 << 3);
51 DDRD &= ~(1 << 2);
52
53 /* Set Tx (PDI CLOCK) high, DATA line low for at least 90ns to disable /RESET functionality */
54 PORTD |= (1 << 5);
55 PORTD &= ~(1 << 3);
56 _delay_us(100);
57
58 /* Set DATA line high (enables PDI interface after 16 PDI CLK cycles) */
59 PORTD |= (1 << 3);
60 _delay_us(20);
61
62 /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
63 UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
64 UCSR1B = (1 << TXEN1);
65 UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
66
67 /* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
68 XPROGTarget_SendIdle();
69 XPROGTarget_SendIdle();
70 }
71
72 /** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
73 void XPROGTarget_EnableTargetTPI(void)
74 {
75 IsSending = false;
76
77 /* Set /RESET line low for at least 400ns to enable TPI functionality */
78 AUX_LINE_DDR |= AUX_LINE_MASK;
79 AUX_LINE_PORT &= ~AUX_LINE_MASK;
80 _delay_us(100);
81
82 /* Set Tx and XCK as outputs, Rx as input */
83 DDRD |= (1 << 5) | (1 << 3);
84 DDRD &= ~(1 << 2);
85
86 /* Set up the synchronous USART for TPI communications - 8 data bits, even parity, 2 stop bits */
87 UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
88 UCSR1B = (1 << TXEN1);
89 UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
90
91 /* Send two IDLEs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
92 XPROGTarget_SendIdle();
93 XPROGTarget_SendIdle();
94 }
95
96 /** Disables the target's PDI interface, exits programming mode and starts the target's application. */
97 void XPROGTarget_DisableTargetPDI(void)
98 {
99 /* Switch to Rx mode to ensure that all pending transmissions are complete */
100 if (IsSending)
101 XPROGTarget_SetRxMode();
102
103 /* Turn off receiver and transmitter of the USART, clear settings */
104 UCSR1A = ((1 << TXC1) | (1 << RXC1));
105 UCSR1B = 0;
106 UCSR1C = 0;
107
108 /* Tristate all pins */
109 DDRD &= ~((1 << 5) | (1 << 3));
110 PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
111 }
112
113 /** Disables the target's TPI interface, exits programming mode and starts the target's application. */
114 void XPROGTarget_DisableTargetTPI(void)
115 {
116 /* Switch to Rx mode to ensure that all pending transmissions are complete */
117 if (IsSending)
118 XPROGTarget_SetRxMode();
119
120 /* Turn off receiver and transmitter of the USART, clear settings */
121 UCSR1A |= (1 << TXC1) | (1 << RXC1);
122 UCSR1B = 0;
123 UCSR1C = 0;
124
125 /* Set all USART lines as inputs, tristate */
126 DDRD &= ~((1 << 5) | (1 << 3));
127 PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
128
129 /* Tristate target /RESET line */
130 AUX_LINE_DDR &= ~AUX_LINE_MASK;
131 AUX_LINE_PORT &= ~AUX_LINE_MASK;
132 }
133
134 /** Sends a byte via the USART.
135 *
136 * \param[in] Byte Byte to send through the USART
137 */
138 void XPROGTarget_SendByte(const uint8_t Byte)
139 {
140 /* Switch to Tx mode if currently in Rx mode */
141 if (!(IsSending))
142 XPROGTarget_SetTxMode();
143
144 /* Wait until there is space in the hardware Tx buffer before writing */
145 while (!(UCSR1A & (1 << UDRE1)));
146 UCSR1A |= (1 << TXC1);
147 UDR1 = Byte;
148 }
149
150 /** Receives a byte via the hardware USART, blocking until data is received or timeout expired.
151 *
152 * \return Received byte from the USART
153 */
154 uint8_t XPROGTarget_ReceiveByte(void)
155 {
156 /* Switch to Rx mode if currently in Tx mode */
157 if (IsSending)
158 XPROGTarget_SetRxMode();
159
160 /* Wait until a byte has been received before reading */
161 while (!(UCSR1A & (1 << RXC1)) && TimeoutTicksRemaining);
162
163 return UDR1;
164 }
165
166 /** Sends an IDLE via the USART to the attached target, consisting of a full frame of idle bits. */
167 void XPROGTarget_SendIdle(void)
168 {
169 /* Switch to Tx mode if currently in Rx mode */
170 if (!(IsSending))
171 XPROGTarget_SetTxMode();
172
173 /* Need to do nothing for a full frame to send an IDLE */
174 for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
175 {
176 /* Wait for a full cycle of the clock */
177 while (PIND & (1 << 5));
178 while (!(PIND & (1 << 5)));
179 while (PIND & (1 << 5));
180 }
181 }
182
183 static void XPROGTarget_SetTxMode(void)
184 {
185 /* Wait for a full cycle of the clock */
186 while (PIND & (1 << 5));
187 while (!(PIND & (1 << 5)));
188 while (PIND & (1 << 5));
189
190 PORTD |= (1 << 3);
191 DDRD |= (1 << 3);
192
193 UCSR1B &= ~(1 << RXEN1);
194 UCSR1B |= (1 << TXEN1);
195
196 IsSending = true;
197 }
198
199 static void XPROGTarget_SetRxMode(void)
200 {
201 while (!(UCSR1A & (1 << TXC1)));
202 UCSR1A |= (1 << TXC1);
203
204 UCSR1B &= ~(1 << TXEN1);
205 UCSR1B |= (1 << RXEN1);
206
207 DDRD &= ~(1 << 3);
208 PORTD &= ~(1 << 3);
209
210 IsSending = false;
211 }
212
213 #endif
214