bool TINYNVM_WaitWhileNVMBusBusy(void)\r
{\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
+ uint8_t TimeoutMSRemaining = 100;\r
while (TimeoutMSRemaining)\r
{\r
/* Send the SLDCS command to read the TPI STATUS register to see the NVM bus is active */\r
XPROGTarget_SendByte(TPI_CMD_SLDCS | TPI_STATUS_REG);\r
if (XPROGTarget_ReceiveByte() & TPI_STATUS_NVM)\r
+ return true;\r
+\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
{\r
- TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
- return true;\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
}\r
}\r
\r
bool TINYNVM_WaitWhileNVMControllerBusy(void)\r
{\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
+ uint8_t TimeoutMSRemaining = 100;\r
while (TimeoutMSRemaining)\r
{\r
/* Send the SIN command to read the TPI STATUS register to see the NVM bus is busy */\r
\r
/* Check to see if the BUSY flag is still set */\r
if (!(XPROGTarget_ReceiveByte() & (1 << 7)))\r
+ return true;\r
+\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
{\r
- TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
- return true;\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
}\r
}\r
\r
bool XMEGANVM_WaitWhileNVMBusBusy(void)\r
{\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
+ uint8_t TimeoutMSRemaining = 100;\r
while (TimeoutMSRemaining)\r
{\r
/* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */\r
XPROGTarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
if (XPROGTarget_ReceiveByte() & PDI_STATUS_NVM)\r
+ return true;\r
+\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
{\r
- TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
- return true;\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
}\r
}\r
\r
bool XMEGANVM_WaitWhileNVMControllerBusy(void)\r
{\r
/* Poll the NVM STATUS register while the NVM controller is busy */\r
+ uint8_t TimeoutMSRemaining = 100;\r
while (TimeoutMSRemaining)\r
{\r
/* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
\r
/* Check to see if the BUSY flag is still set */\r
if (!(XPROGTarget_ReceiveByte() & (1 << 7)))\r
+ return true;\r
+\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
{\r
- TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
- return true;\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
}\r
}\r
\r
#define SoftUSART_BitCount GPIOR2\r
\r
\r
-/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */\r
+/** ISR to manage the rising edge of the PDI/TPI software USART when bit-banged USART mode is selected. */\r
ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+ TIFR1 |= (1 << OCF1B);\r
+ TIMSK1 = (1 << OCIE1B);\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
return;\r
\r
- /* Check to see if we are at a rising or falling edge of the clock */\r
- if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
- {\r
- /* If at rising clock edge and we are in send mode, abort */\r
- if (IsSending)\r
- return;\r
- \r
- /* Wait for the start bit when receiving */\r
- if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
- return;\r
- \r
- /* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
- * be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */\r
- if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
- ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
+ /* If at rising clock edge and we are in send mode, abort */\r
+ if (IsSending)\r
+ return;\r
+ \r
+ /* Wait for the start bit when receiving */\r
+ if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
+ return;\r
\r
- SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--;\r
- }\r
- else\r
- {\r
- /* If at falling clock edge and we are in receive mode, abort */\r
- if (!IsSending)\r
- return;\r
+ /* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
+ * be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */\r
+ if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
+ ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
- /* Set the data line to the next bit value */\r
- if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)\r
- BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- else\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; \r
+ SoftUSART_Data >>= 1;\r
+ SoftUSART_BitCount--;\r
+}\r
\r
- SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--;\r
- }\r
+/** ISR to manage the falling edge of the PDI/TPI software USART when bit-banged USART mode is selected. */\r
+ISR(TIMER1_COMPB_vect, ISR_BLOCK)\r
+{\r
+ /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
+ BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+ TIFR1 |= (1 << OCF1A);\r
+ TIMSK1 = (1 << OCIE1A);\r
+\r
+ /* If not sending or receiving, just exit */\r
+ if (!(SoftUSART_BitCount))\r
+ return;\r
+\r
+ /* If at falling clock edge and we are in receive mode, abort */\r
+ if (!IsSending)\r
+ return;\r
+\r
+ /* Set the data line to the next bit value */\r
+ if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)\r
+ BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
+ else\r
+ BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; \r
+\r
+ SoftUSART_Data >>= 1;\r
+ SoftUSART_BitCount--;\r
}\r
\r
/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r
\r
/* Fire timer compare channel A ISR to manage the software USART */\r
OCR1A = BITS_BETWEEN_USART_CLOCKS;\r
+ OCR1B = BITS_BETWEEN_USART_CLOCKS;\r
TCCR1B = (1 << WGM12) | (1 << CS10);\r
+ TCCR1C = (1 << FOC1B);\r
TIMSK1 = (1 << OCIE1A);\r
#endif\r
\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
+ /* Turn off software USART management timer */\r
+ TCCR1B = 0;\r
+ TCCR1C = 0;\r
+\r
/* Set /RESET high for a one millisecond to ensure target device is restarted */\r
BITBANG_PDICLOCK_PORT |= BITBANG_PDICLOCK_MASK;\r
_delay_ms(1);\r
\r
/* Tristate DATA and CLOCK lines */\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;\r
+ BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK; \r
#endif\r
}\r
\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
+ /* Turn off software USART management timer */\r
+ TCCR1B = 0;\r
+\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait until a byte has been received before reading */\r
- while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining);\r
+ uint8_t TimeoutMSRemaining = 100;\r
+ while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining)\r
+ {\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
+ {\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
+ } \r
+ }\r
+ \r
return UDR1;\r
#else\r
/* Wait until a byte has been received before reading */\r
SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
- while (SoftUSART_BitCount && TimeoutMSRemaining);\r
+ uint8_t TimeoutMSRemaining = 100;\r
+ while (SoftUSART_BitCount && TimeoutMSRemaining)\r
+ {\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
+ {\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
+ }\r
+ }\r
\r
/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */\r
return (uint8_t)SoftUSART_Data;\r
}\r
\r
/* Wait until DATA line has been pulled up to idle by the target */\r
- while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining);\r
+ uint8_t TimeoutMSRemaining = 100;\r
+ while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)\r
+ {\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
+ {\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
+ }\r
+ } \r
#endif\r
\r
IsSending = false;\r