+usbasp.2007-07-23
+-----------------
+- changed licence to GNU GPL v2
+- included new AVRUSB driver version (Release 2007-07-07); AVRUSB licence was changed to GNU GPL v2
+- fixed long addressing for Mega128 (by BoskiDialer)
+
usbasp.2006-12-29
-----------------
- fixed returnvalue in usbWriteFunction (by Jeroen Koeter)
LICENSE
-The project is built with AVR USB driver by Objective Development, which is
-published under a proprietary Open Source license. To conform with this
-license, USBasp is distributed under the same license conditions. See the
-file "firmware/usbdrv/License.txt" for details.
+USBasp is distributed under the terms and conditions of the GNU GPL version
+2 (see "firmware/usbdrv/License.txt" for details).
+
+USBasp is built with AVR USB driver by OBJECTIVE DEVELOPMENT GmbH. See
+"firmware/usbdrv/" for further information.
LIMITATIONS
Hardware:
-This package includes a circuit diagram. That circuit can only be used for
+This package includes a circuit diagram. This circuit can only be used for
programming 5V target systems. For other systems a level converter is needed.
Firmware:
libusb-win32 .................... http://libusb-win32.sourceforge.net/
-2006-12-29 Thomas Fischl <tfischl@gmx.de>
+2007-07-23 Thomas Fischl <tfischl@gmx.de>
http://www.fischl.de
+++ /dev/null
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Autor..........: Thomas Fischl <tfischl@gmx.de>
Description....: Provides functions for timing/waiting
- Licence........: Free under certain conditions. See Documentation.
+ Licence........: GNU GPL v2 (see Readme.txt)
Creation Date..: 2005-02-23
Last change....: 2005-04-20
*/
Autor..........: Thomas Fischl <tfischl@gmx.de>
Description....: Provides functions for timing/waiting
- Licence........: Free under certain conditions. See Documentation.
+ Licence........: GNU GPL v2 (see Readme.txt)
Creation Date..: 2005-02-23
Last change....: 2006-11-16
*/
Autor..........: Thomas Fischl <tfischl@gmx.de>
Description....: Provides functions for communication/programming
over ISP interface
- Licence........: Free under certain conditions. See Documentation.
+ Licence........: GNU GPL v2 (see Readme.txt)
Creation Date..: 2005-02-23
- Last change....: 2005-04-20
+ Last change....: 2007-07-23
*/
#include <avr/io.h>
return 1; /* error: device dosn't answer */
}
-uchar ispReadFlash(unsigned int address) {
+uchar ispReadFlash(unsigned long address) {
ispTransmit(0x20 | ((address & 1) << 3));
ispTransmit(address >> 9);
ispTransmit(address >> 1);
}
-uchar ispWriteFlash(unsigned int address, uchar data, uchar pollmode) {
+uchar ispWriteFlash(unsigned long address, uchar data, uchar pollmode) {
/* 0xFF is value after chip erase, so skip programming
if (data == 0xFF) {
}
-uchar ispFlushPage(unsigned int address, uchar pollvalue) {
+uchar ispFlushPage(unsigned long address, uchar pollvalue) {
ispTransmit(0x4C);
ispTransmit(address >> 9);
ispTransmit(address >> 1);
Autor..........: Thomas Fischl <tfischl@gmx.de>
Description....: Provides functions for communication/programming
over ISP interface
- Licence........: Free under certain conditions. See Documentation.
+ Licence........: GNU GPL v2 (see Readme.txt)
Creation Date..: 2005-02-23
- Last change....: 2005-04-20
+ Last change....: 2007-07-23
*/
#ifndef __isp_h_included__
uchar ispReadEEPROM(unsigned int address);
/* write byte to flash at given address */
-uchar ispWriteFlash(unsigned int address, uchar data, uchar pollmode);
+uchar ispWriteFlash(unsigned long address, uchar data, uchar pollmode);
-uchar ispFlushPage(unsigned int address, uchar pollvalue);
+uchar ispFlushPage(unsigned long address, uchar pollvalue);
/* read byte from flash at given address */
-uchar ispReadFlash(unsigned int address);
+uchar ispReadFlash(unsigned long address);
/* write byte to eeprom at given address */
uchar ispWriteEEPROM(unsigned int address, uchar data);
Thomas Fischl <tfischl@gmx.de>
- License:
- The project is built with AVR USB driver by Objective Development, which is
- published under an own licence based on the GNU General Public License (GPL).
- USBasp is also distributed under this enhanced licence. See Documentation.
-
+ License........: GNU GPL v2 (see Readme.txt)
Target.........: ATMega8 at 12 MHz
Creation Date..: 2005-02-20
- Last change....: 2006-12-29
+ Last change....: 2007-07-23
PC2 SCK speed option. GND -> slow (8khz SCK),
open -> fast (375kHz SCK)
#define USBASP_FUNC_WRITEFLASH 6
#define USBASP_FUNC_READEEPROM 7
#define USBASP_FUNC_WRITEEEPROM 8
+#define USBASP_FUNC_SETLONGADDRESS 9
#define PROG_STATE_IDLE 0
#define PROG_STATE_WRITEFLASH 1
static uchar prog_state = PROG_STATE_IDLE;
-static unsigned int prog_address;
+static uchar prog_address_newmode = 0;
+static unsigned long prog_address;
static unsigned int prog_nbytes = 0;
-static unsigned int prog_pagesize; //TP: Mega128 fix
+static unsigned int prog_pagesize;
static uchar prog_blockflags;
static uchar prog_pagecounter;
ispSetSCKOption(ISP_SCK_FAST);
}
+ /* set compatibility mode of address delivering */
+ prog_address_newmode = 0;
+
ispConnect();
ledRedOn();
len = 4;
} else if (data[1] == USBASP_FUNC_READFLASH) {
- prog_address = (data[3] << 8) | data[2];
+
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
+
prog_nbytes = (data[7] << 8) | data[6];
prog_state = PROG_STATE_READFLASH;
len = 0xff; /* multiple in */
} else if (data[1] == USBASP_FUNC_READEEPROM) {
- prog_address = (data[3] << 8) | data[2];
+
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
+
prog_nbytes = (data[7] << 8) | data[6];
prog_state = PROG_STATE_READEEPROM;
len = 0xff; /* multiple in */
len = 1;
} else if (data[1] == USBASP_FUNC_WRITEFLASH) {
- prog_address = (data[3] << 8) | data[2];
+
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
+
prog_pagesize = data[4];
prog_blockflags = data[5] & 0x0F;
- prog_pagesize += (((unsigned int)data[5] & 0xF0)<<4); //TP: Mega128 fix
+ prog_pagesize += (((unsigned int)data[5] & 0xF0)<<4);
if (prog_blockflags & PROG_BLOCKFLAG_FIRST) {
prog_pagecounter = prog_pagesize;
}
len = 0xff; /* multiple out */
} else if (data[1] == USBASP_FUNC_WRITEEEPROM) {
- prog_address = (data[3] << 8) | data[2];
+
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
+
prog_pagesize = 0;
prog_blockflags = 0;
prog_nbytes = (data[7] << 8) | data[6];
prog_state = PROG_STATE_WRITEEEPROM;
len = 0xff; /* multiple out */
+
+ } else if(data[1] == USBASP_FUNC_SETLONGADDRESS) {
+
+ /* set new mode of address delivering (ignore address delivered in commands) */
+ prog_address_newmode = 1;
+ /* set new address */
+ prog_address = *((unsigned long*)&data[2]);
}
usbMsgPtr = replyBuffer;
--- /dev/null
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/* Name: usbconfig.h
* Project: AVR USB driver
- * Author: Christian Starkjohann
+ * Author: Christian Starkjohann, Thomas Fischl
* Creation Date: 2005-04-01
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: usbconfig.h 43 2005-04-10 21:04:36Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
*/
#ifndef __usbconfig_h_included__
#define USB_CFG_IOPORTNAME B
/* This is the port where the USB bus is connected. When you configure it to
- * "PORTB", the registers PORTB, PINB (=PORTB-2) and DDRB (=PORTB-1) will be
- * used.
+ * "B", the registers PORTB, PINB and DDRB will be used.
*/
#define USB_CFG_DMINUS_BIT 0
/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected.
- * This MUST be bit 0 or 7. All other values will result in a compile error!
+ * This may be any bit in the port.
*/
#define USB_CFG_DPLUS_BIT 1
/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected.
* This may be any bit in the port. Please note that D+ must also be connected
* to interrupt pin INT0!
*/
+/* #define USB_CFG_CLOCK_KHZ (F_CPU/1000) */
+/* Clock rate of the AVR in MHz. Legal values are 12000, 16000 or 16500.
+ * The 16.5 MHz version of the code requires no crystal, it tolerates +/- 1%
+ * deviation from the nominal frequency. All other rates require a precision
+ * of 2000 ppm and thus a crystal!
+ * Default if not specified: 12 MHz
+ */
+
+/* ----------------------- Optional Hardware Config ------------------------ */
-/* #define USB_CFG_PULLUP_IOPORTNAME B */
-/* This is the port where the USB D- pullup resistor is connected. When you
- * configure it to "PORTB", the registers PORTB and DDRB (=PORTB-1) will be
- * used. If this constant is defined, the macros usbDeviceConnect() and
- * usbDeviceDisconnect will be available.
+/* #define USB_CFG_PULLUP_IOPORTNAME D */
+/* If you connect the 1.5k pullup resistor from D- to a port pin instead of
+ * V+, you can connect and disconnect the device from firmware by calling
+ * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h).
+ * This constant defines the port on which the pullup resistor is connected.
*/
-/* #define USB_CFG_PULLUP_BIT 2 */
-/* This is the bit number in USB_CFG_PULLUP_IOPORT where the USB D- 1.5 kOhm
- * pullup resistor is connected instead of VBUS. This may be any bit in
- * the port.
+/* #define USB_CFG_PULLUP_BIT 4 */
+/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined
+ * above) where the 1.5k pullup resistor is connected. See description
+ * above for details.
*/
/* --------------------------- Functional Range ---------------------------- */
/* Define this to 1 if you want to compile a version with two endpoints: The
* default control endpoint 0 and an interrupt-in endpoint 1.
*/
+#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0
+/* Define this to 1 if you want to compile a version with three endpoints: The
+ * default control endpoint 0, an interrupt-in endpoint 1 and an interrupt-in
+ * endpoint 3. You must also enable endpoint 1 above.
+ */
#define USB_CFG_IMPLEMENT_HALT 0
/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature
* for endpoint 1 (interrupt endpoint). Although you may not need this feature,
* The value is in milliamperes. [It will be divided by two since USB
* communicates power requirements in units of 2 mA.]
*/
-#define USB_CFG_SAMPLE_EXACT 1
-/* This variable affects Sampling Jitter for USB receiving. When it is 0, the
- * driver guarantees a sampling window of 1/2 bit. The USB spec requires
- * that the receiver has at most 1/4 bit sampling window. The 1/2 bit window
- * should still work reliably enough because we work at low speed. If you want
- * to meet the spec, set this value to 1. This will unroll a loop which
- * results in bigger code size.
- * If you have problems with long cables, try setting this value to 1.
- */
#define USB_CFG_IMPLEMENT_FN_WRITE 1
/* Set this to 1 if you want usbFunctionWrite() to be called for control-out
* transfers. Set it to 0 if you don't need it and want to save a couple of
* data from a static buffer, set it to 0 and return the data from
* usbFunctionSetup(). This saves a couple of bytes.
*/
+#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0
+/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoint 1.
+ * You must implement the function usbFunctionWriteOut() which receives all
+ * interrupt/bulk data sent to endpoint 1.
+ */
+#define USB_CFG_HAVE_FLOWCONTROL 0
+/* Define this to 1 if you want flowcontrol over USB data. See the definition
+ * of the macros usbDisableAllRequests() and usbEnableAllRequests() in
+ * usbdrv.h.
+ */
/* -------------------------- Device Description --------------------------- */
* you use obdev's free shared VID/PID pair. Be sure to read the rules in
* USBID-License.txt!
*/
-#define USB_CFG_DEVICE_VERSION 0x01, 0x01
+#define USB_CFG_DEVICE_VERSION 0x02, 0x01
/* Version number of the device: Minor number first, then major number.
*/
#define USB_CFG_VENDOR_NAME 'w', 'w', 'w', '.', 'f', 'i', 's', 'c', 'h', 'l', '.', 'd', 'e'
/* Same as above for the device name. If you don't want a device name, undefine
* the macros. See the file USBID-License.txt before you assign a name.
*/
-#define USB_CFG_SERIAL_NUMBER_LENGTH 0
-/* Set this define to the number of charcters in the serial number if your
- * device should have a serial number to uniquely identify each hardware
- * instance. You must supply the serial number in a string descriptor with the
- * name "usbCfgSerialNumberStringDescriptor", e.g.:
- * #define USB_CFG_SERIAL_NUMBER_LENGTH 5
- * int usbCfgSerialNumberStringDescriptor[] PROGMEM = {
- * USB_STRING_DESCRIPTOR_HEADER(USB_CFG_SERIAL_NUMBER_LENGTH),
- * '1', '2', '3', '4', '5'
- * };
- * See usbdrv.h for more information about the USB_STRING_DESCRIPTOR_HEADER()
- * macro or usbdrv.c for example string descriptors.
- * You may want to put "usbCfgSerialNumberStringDescriptor" at a constant
- * flash memory address (with magic linker commands) so that you don't need
- * to recompile if you change it.
+/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */
+/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */
+/* Same as above for the serial number. If you don't want a serial number,
+ * undefine the macros.
+ * It may be useful to provide the serial number through other means than at
+ * compile time. See the section about descriptor properties below for how
+ * to fine tune control over USB descriptors such as the string descriptor
+ * for the serial number.
*/
#define USB_CFG_DEVICE_CLASS 0xff
#define USB_CFG_DEVICE_SUBCLASS 0
* an HID device. Otherwise don't define it or define it to 0.
*/
+/* ------------------- Fine Control over USB Descriptors ------------------- */
+/* If you don't want to use the driver's default USB descriptors, you can
+ * provide our own. These can be provided as (1) fixed length static data in
+ * flash memory, (2) fixed length static data in RAM or (3) dynamically at
+ * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more
+ * information about this function.
+ * Descriptor handling is configured through the descriptor's properties. If
+ * no properties are defined or if they are 0, the default descriptor is used.
+ * Possible properties are:
+ * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched
+ * at runtime via usbFunctionDescriptor().
+ * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found
+ * in static memory is in RAM, not in flash memory.
+ * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash),
+ * the driver must know the descriptor's length. The descriptor itself is
+ * found at the address of a well known identifier (see below).
+ * List of static descriptor names (must be declared PROGMEM if in flash):
+ * char usbDescriptorDevice[];
+ * char usbDescriptorConfiguration[];
+ * char usbDescriptorHidReport[];
+ * char usbDescriptorString0[];
+ * int usbDescriptorStringVendor[];
+ * int usbDescriptorStringDevice[];
+ * int usbDescriptorStringSerialNumber[];
+ * Other descriptors can't be provided statically, they must be provided
+ * dynamically at runtime.
+ *
+ * Descriptor properties are or-ed or added together, e.g.:
+ * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18))
+ *
+ * The following descriptors are defined:
+ * USB_CFG_DESCR_PROPS_DEVICE
+ * USB_CFG_DESCR_PROPS_CONFIGURATION
+ * USB_CFG_DESCR_PROPS_STRINGS
+ * USB_CFG_DESCR_PROPS_STRING_0
+ * USB_CFG_DESCR_PROPS_STRING_VENDOR
+ * USB_CFG_DESCR_PROPS_STRING_PRODUCT
+ * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER
+ * USB_CFG_DESCR_PROPS_HID
+ * USB_CFG_DESCR_PROPS_HID_REPORT
+ * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver)
+ *
+ */
+
+#define USB_CFG_DESCR_PROPS_DEVICE 0
+#define USB_CFG_DESCR_PROPS_CONFIGURATION 0
+#define USB_CFG_DESCR_PROPS_STRINGS 0
+#define USB_CFG_DESCR_PROPS_STRING_0 0
+#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0
+#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0
+#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0
+#define USB_CFG_DESCR_PROPS_HID 0
+#define USB_CFG_DESCR_PROPS_HID_REPORT 0
+#define USB_CFG_DESCR_PROPS_UNKNOWN 0
+
+/* ----------------------- Optional MCU Description ------------------------ */
+
+/* The following configurations have working defaults in usbdrv.h. You
+ * usually don't need to set them explicitly. Only if you want to run
+ * the driver on a device which is not yet supported or with a compiler
+ * which is not fully supported (such as IAR C) or if you use a differnt
+ * interrupt than INT0, you may have to define some of these.
+ */
+/* #define USB_INTR_CFG MCUCR */
+/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */
+/* #define USB_INTR_CFG_CLR 0 */
+/* #define USB_INTR_ENABLE GIMSK */
+/* #define USB_INTR_ENABLE_BIT INT0 */
+/* #define USB_INTR_PENDING GIFR */
+/* #define USB_INTR_PENDING_BIT INTF0 */
+
#endif /* __usbconfig_h_included__ */
application code to reset data toggling on interrupt pipes.
* Release 2006-07-18
+
+ - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes
+ an assembler error.
+ - usbDeviceDisconnect() takes pull-up resistor to high impedance now.
+
+* Release 2007-02-01
+
+ - Merged in some code size improvements from usbtiny (thanks to Dick
+ Streefland for these optimizations!)
+ - Special alignment requirement for usbRxBuf not required any more. Thanks
+ again to Dick Streefland for this hint!
+ - Reverted to "#warning" instead of unused static variables -- new versions
+ of IAR CC should handle this directive.
+ - Changed Open Source license to GNU GPL v2 in order to make linking against
+ other free libraries easier. We no longer require publication of the
+ circuit diagrams, but we STRONGLY encourage it. If you improve the driver
+ itself, PLEASE grant us a royalty free license to your changes for our
+ commercial license.
+
+* Release 2007-03-29
+
+ - New configuration option "USB_PUBLIC" in usbconfig.h.
+ - Set USB version number to 1.10 instead of 1.01.
+ - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and
+ USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences
+ to USB_CFG_DESCR_PROPS_STRING_PRODUCT.
+ - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver
+ code.
+ - New assembler module for 16 MHz crystal.
+ - usbdrvasm.S contains common code only, clock-specific parts have been moved
+ to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively.
+
+* Release 2007-06-25
+
+ - 16 MHz module: Do SE0 check in stuffed bits as well.
+
+* Release 2007-07-07
--- /dev/null
+AVR-USB Driver Software License Agreement
+Version 2006-07-24
+
+THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN
+ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING
+THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT.
+
+
+1 DEFINITIONS
+
+1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH,
+Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA.
+
+1.2 "You" shall mean the Licensee.
+
+1.3 "AVR-USB" shall mean the firmware-only USB device implementation for
+Atmel AVR microcontrollers distributed by OBJECTIVE DEVELOPMENT and
+consisting of the files usbdrv.c, usbdrv.h, usbdrvasm.S, oddebug.c,
+oddebug.h, usbdrvasm.asm, iarcompat.h and usbconfig-prototype.h.
+
+
+2 LICENSE GRANTS
+
+2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source
+code of AVR-USB.
+
+2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the
+non-exclusive right to use and distribute AVR-USB with your hardware
+product(s), restricted by the limitations in section 3 below.
+
+2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify
+your copy of AVR-USB according to your needs.
+
+2.4 USB IDs. OBJECTIVE DEVELOPMENT grants you the exclusive rights to use
+USB Product ID(s) sent to you in e-mail after receiving your payment in
+conjunction with USB Vendor ID 5824. OBJECTIVE DEVELOPMENT has acquired an
+exclusive license for this pair of USB identifiers from Wouter van Ooijen
+(www.voti.nl), who has licensed the VID from the USB Implementers Forum,
+Inc. (www.usb.org).
+
+
+3 LICENSE RESTRICTIONS
+
+3.1 Number of Units. Only one of the following three definitions is
+applicable. Which one is determined by the amount you pay to OBJECTIVE
+DEVELOPMENT, see section 4 ("Payment") below.
+
+Hobby License: You may use AVR-USB according to section 2 above in no more
+than 5 hardware units. These units must not be sold for profit.
+
+Entry Level License: You may use AVR-USB according to section 2 above in no
+more than 150 hardware units.
+
+Professional License: You may use AVR-USB according to section 2 above in
+any number of hardware units, except for large scale production ("unlimited
+fair use"). Quantities below 10,000 units are not considered large scale
+production. If your reach quantities which are obviously large scale
+production, you must pay a license fee of 0.10 EUR per unit for all units
+above 10,000.
+
+3.2 Rental. You may not rent, lease, or lend AVR-USB or otherwise encumber
+any copy of AVR-USB, or any of the rights granted herein.
+
+3.3 Transfer. You may not transfer your rights under this Agreement to
+another party without OBJECTIVE DEVELOPMENT's prior written consent. If
+such consent is obtained, you may permanently transfer this License to
+another party. The recipient of such transfer must agree to all terms and
+conditions of this Agreement.
+
+3.4 Reservation of Rights. OBJECTIVE DEVELOPMENT retains all rights not
+expressly granted.
+
+3.5 Non-Exclusive Rights. Your license rights under this Agreement are
+non-exclusive.
+
+3.6 Third Party Rights. This Agreement cannot grant you rights controlled
+by third parties. In particular, you are not allowed to use the USB logo or
+other trademarks owned by the USB Implementers Forum, Inc. without their
+consent. Since such consent depends on USB certification, it should be
+noted that AVR-USB will not pass certification because it does not
+implement checksum verification and the microcontroller ports do not meet
+the electrical specifications.
+
+
+4 PAYMENT
+
+The payment amount depends on the variation of this agreement (according to
+section 3.1) into which you want to enter. Concrete prices are listed on
+OBJECTIVE DEVELOPMENT's web site, usually at
+http://www.obdev.at/avrusb/license.html. You agree to pay the amount listed
+there to OBJECTIVE DEVELOPMENT or OBJECTIVE DEVELOPMENT's payment processor
+or reseller.
+
+
+5 COPYRIGHT AND OWNERSHIP
+
+AVR-USB is protected by copyright laws and international copyright
+treaties, as well as other intellectual property laws and treaties. AVR-USB
+is licensed, not sold.
+
+
+6 TERM AND TERMINATION
+
+6.1 Term. This Agreement shall continue indefinitely. However, OBJECTIVE
+DEVELOPMENT may terminate this Agreement and revoke the granted license and
+USB-IDs if you fail to comply with any of its terms and conditions.
+
+6.2 Survival of Terms. All provisions regarding secrecy, confidentiality
+and limitation of liability shall survive termination of this agreement.
+
+
+7 DISCLAIMER OF WARRANTY AND LIABILITY
+
+LIMITED WARRANTY. AVR-USB IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
+KIND. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, OBJECTIVE
+DEVELOPMENT AND ITS SUPPLIERS HEREBY DISCLAIM ALL WARRANTIES, EITHER
+EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+NON-INFRINGEMENT, WITH REGARD TO AVR-USB, AND THE PROVISION OF OR FAILURE
+TO PROVIDE SUPPORT SERVICES. THIS LIMITED WARRANTY GIVES YOU SPECIFIC LEGAL
+RIGHTS. YOU MAY HAVE OTHERS, WHICH VARY FROM STATE/JURISDICTION TO
+STATE/JURISDICTION.
+
+LIMITATION OF LIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW,
+IN NO EVENT SHALL OBJECTIVE DEVELOPMENT OR ITS SUPPLIERS BE LIABLE FOR ANY
+SPECIAL, INCIDENTAL, INDIRECT, OR CONSEQUENTIAL DAMAGES WHATSOEVER
+(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR ANY OTHER PECUNIARY
+LOSS) ARISING OUT OF THE USE OF OR INABILITY TO USE AVR-USB OR THE
+PROVISION OF OR FAILURE TO PROVIDE SUPPORT SERVICES, EVEN IF OBJECTIVE
+DEVELOPMENT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN ANY
+CASE, OBJECTIVE DEVELOPMENT'S ENTIRE LIABILITY UNDER ANY PROVISION OF THIS
+AGREEMENT SHALL BE LIMITED TO THE AMOUNT ACTUALLY PAID BY YOU FOR AVR-USB.
+
+
+8 MISCELLANEOUS TERMS
+
+8.1 Marketing. OBJECTIVE DEVELOPMENT has the right to mention for marketing
+purposes that you entered into this agreement.
+
+8.2 Entire Agreement. This document represents the entire agreement between
+OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by
+an authorized representative of both, OBJECTIVE DEVELOPMENT and you.
+
+8.3 Severability. In case a provision of these terms and conditions should
+be or become partly or entirely invalid, ineffective, or not executable,
+the validity of all other provisions shall not be affected.
+
+8.4 Applicable Law. This agreement is governed by the laws of the Republic
+of Austria.
+
+8.5 Responsible Courts. The responsible courts in Vienna/Austria will have
+exclusive jurisdiction regarding all disputes in connection with this
+agreement.
-PREFACE
-
-Conceiving and understanding a new license is not an easy task. To make things
-easier for both, the author and the licensee, we have decided to base our
-license for the USB driver on an existing license with well-understood
-properties.
+OBJECTIVE DEVELOPMENT GmbH's AVR-USB driver software is distributed under the
+terms and conditions of the GNU GPL version 2, see the text below. In addition
+to the requirements in the GPL, we STRONGLY ENCOURAGE you to do the following:
-Our favorite choice for the base license was the GNU General Public License
-(GPL). However, we cannot use the GNU GPL directly for the following reasons:
-
-(1) It was not intended for projects involving hardware -- we must extend the
- term "source code" to at least the circuit diagram.
-(2) The GNU GPL does not require publication. Only if a binary is published,
- it requires that the source is published as well. This is reasonable for
- software because unpublished software is of little relevance. For projects
- involving hardware, we want to REQUIRE publication. More than that, we
- even want to define HOW the publication must be done (files contained,
- file formats etc).
-(3) As the author of the software, we can distribute it under more than one
- license. For people who don't want to meet the obligations of the GNU GPL,
- we want to offer commercial licenses. To avoid a split in revisions of
- the driver, we need special privileges to distribute contributed
- modifications under proprietary licenses.
-
-We can not simply modify the GNU GPL and incorporate our changes because the
-Free Software Foundation (FSF) who holds the copyright for the text of the
-GNU GPL does not allow modifications. We therefore set up our own small
-license which incorporates the GNU GPL by reference:
-
-
-
-LICENSE FOR PROJECTS BUILT WITH "OBJECTIVE DEVELOPMENT'S
-FIRMWARE-ONLY USB-DRIVER FOR ATMEL'S AVR MICROCONTROLLERS"
-Version 2006-01
-
-
-I. Definitions
-
-"OBDEV" shall mean OBJECTIVE DEVELOPMENT Software GmbH or any legal successor
-thereof.
-
-"Software Source Code" shall mean the preferred form of the software for
-making modifications to it.
-
-"USB Driver" shall mean the Software Source Code for OBDEV's firmware-only
-USB-driver for Atmel's AVR microcontrollers.
-
-"Function" shall mean the Software Source Code for all software executed on
-the microcontroller except the USB Driver.
-
-"Host Software" shall mean the Software Source Code for all software required
-to control the USB device from the USB host running any operating system.
-
-"Project" shall mean the USB Driver, the Function, the Host Software, circuit
-diagrams of the controller based hardware and accompanying documentation.
-
-"source code" shall have the same meaning as the term "Project" above.
-
-"Web Site" shall mean a collection of text and multimedia documents accessible
-worldwide over internet through the HyperText Transfer Protocol (HTTP) on
-TCP port 80 (standard HTTP port).
-
-
-II. General License Terms
-The general terms of this license consist of the GNU General Public License
-Version 2 (GNU GPL2) which is hereby incorporated into this section as though
-it were fully set forth here. A copy of the GNU GPL2 is included for your
-convenience in appendix A of this license.
-
-The term "source code" in the GNU GPL2 is to be understood as defined in
-section I above. If any term or definition in section I, III, IV or V
-conflicts with the GNU GPL2, the term or definition in section I, III, IV or
-V has precedence of the GNU GPL2.
-
-
-III. Distribution of the Project
-The distributed form of a Project must contain at least the following files:
-(a) Software Source Code files for the USB Driver, the Function and the Host
- Software.
-(b) Circuit diagrams for the hardware in PDF, PNG or GIF image file format.
-(c) A file with name "Readme.txt" in ASCII format with at least the following
- content (in English language):
- - An explanation what the Project does.
- - What to do with the distributed files (installation procedure etc.).
- - A reference to Objective Development's USB driver.
- - Your (author's) name and contact information. E-mail and/or URL is
- sufficient.
-(d) Optionally a text file with a description of the circuit diagram, an
- explanation of special (software) techniques used etc.
-(e) A copy of this license in a file with the name "License.txt". This copy
- can be in the "usbdrv" subdirectory which contains the driver.
-
-
-IV. Requirement for Publication
-All modifications and derived work (Projects using the USB Driver) MUST be
-distributed (published) as described in section III above on a Web Site. The
-main page must reproduce at least a description of the Project (e.g. as
-contained in the "Readme.txt" file distributed) and a download link for the
-entire Project. The URL of the main page must be submitted to OBDEV. OBDEV
-will provide a mechanism for submitting Project URLs and for publishing
-Projects on their Web Site. The Project must remain available for at least
-twelve (12) months after the initial publication or at least six (6) months
-after a subsequent version of that particular Project has been published.
-
-
-V. Author Privileges
-OBDEV reserves the right to distribute the USB Driver and all modified
-versions under other (proprietary) licenses. If you modify the USB Driver
-under the grants of this license, you therefore grant OBDEV (in addition to
-the grants of the GNU GPL2) a worldwide, perpetual, irrevocable royalty free
-license for your modifications. OBDEV shall not automatically gain rights
-other than those of the GNU GPL2 in the other parts of the Project. This
-section V overrides possibly contradicting terms in the GNU GPL2 referenced
-in section II.
+(1) Publish your entire project on a web site and drop us a note with the URL.
+Use the form at http://www.obdev.at/avrusb/feedback.html for your submission.
+
+(2) Adhere to minimum publication standards. Please include AT LEAST:
+ - a circuit diagram in PDF, PNG or GIF format
+ - full source code for the host software
+ - a Readme.txt file in ASCII format which describes the purpose of the
+ project and what can be found in which directories and which files
+ - a reference to http://www.obdev.at/avrusb/
+
+(3) If you improve the driver firmware itself, please give us a free license
+to your modifications for our commercial license offerings.
-APPENDIX A
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
TECHNICAL DOCUMENTATION
=======================
-The technical documentation for the firmware driver is contained in the file
-"usbdrv.h". Please read all of it carefully!
+The technical documentation (API) for the firmware driver is contained in the
+file "usbdrv.h". Please read all of it carefully! Configuration options are
+documented in "usbconfig-prototype.h".
+
+The driver consists of the following files:
+ Readme.txt ............. The file you are currently reading.
+ Changelog.txt .......... Release notes for all versions of the driver.
+ usbdrv.h ............... Driver interface definitions and technical docs.
+* usbdrv.c ............... High level language part of the driver. Link this
+ module to your code!
+* usbdrvasm.S ............ Assembler part of the driver. This module is mostly
+ a stub and includes one of the usbdrvasm*.S files
+ depending on processor clock. Link this module to
+ your code!
+ usbdrvasm12.S .......... 12 MHz version of the assembler routines. Included
+ by usbdrvasm.S, don't link it directly!
+ usbdrvasm16.S .......... 16 MHz version of the assembler routines. Included
+ by usbdrvasm.S, don't link it directly!
+ usbdrvasm165.S ......... 16.5 MHz version of the assembler routines including
+ a PLL so that an 1% accurate RC oscillator can be
+ used. Included by usbdrvasm.S, don't link directly!
+ usbconfig-prototype.h .. Prototype for your own usbdrv.h file.
+* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is
+ defined to a value greater than 0. Link this module
+ to your code!
+ oddebug.h .............. Interface definitions of the debug module.
+ iarcompat.h ............ Compatibility definitions for IAR C-compiler.
+ usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this
+ module instead of usbdrvasm.S when you assembler
+ with IAR's tools.
+ License.txt ............ Open Source license for this driver.
+ CommercialLicense.txt .. Optional commercial license for this driver.
+ USBID-License.txt ...... Terms and conditions for using particular USB ID
+ values for particular purposes.
+
+(*) ... These files should be linked to your project.
+
+
+CPU CORE CLOCK FREQUENCY
+========================
+We supply assembler modules for clock frequencies of 12 MHz, 16 MHz and
+16.5 MHz. Other clock rates are not supported. The actual clock rate must be
+configured in usbdrv.h unless you use the default 12 MHz.
+
+12 MHz Clock
+This is the traditional clock rate of AVR-USB because it's the lowest clock
+rate where the timing constraints of the USB spec can be met.
+
+16 MHz Clock
+This clock rate has been added for users of the Arduino board and other
+ready-made boards which come with a fixed 16 MHz crystal. It's also an option
+if you need the slightly higher clock rate for performance reasons. Since
+16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code
+is somewhat tricky and has to insert a leap cycle every third byte.
+
+16.5 MHz Clock
+The assembler module for this clock rate differs from the other modules because
+it has been built for an RC oscillator with only 1% precision. The receiver
+code inserts leap cycles to compensate for clock deviations. 1% is also the
+precision which can be achieved by calibrating the internal RC oscillator of
+the AVR. Please note that only AVRs with internal 64 MHz PLL oscillator can be
+used since the 8 MHz RC oscillator cannot be trimmed up to 16.5 MHz. This
+includes the very popular ATTiny25, ATTiny45, ATTiny85 series as well as the
+ATTiny26.
+
+We recommend that you obtain appropriate calibration values for 16.5 MHz core
+clock at programming time and store it in flash or EEPROM or compute the value
+from a reference clock at run time. However, since Atmel's 8 MHz calibration
+is much more precise than the guaranteed 10%, it's usually possible to add a
+fixed offset to this value.
USB IDENTIFIERS
To use our predefined VID/PID pair, you MUST conform to a couple of
requirements. See the file "USBID-License.txt" for details.
+Objective Development also has some offerings which include product IDs. See
+http://www.obdev.at/avrusb/ for details.
+
HOST DRIVER
===========
USING AVR-USB FOR FREE
======================
-The AVR firmware driver is published under an Open Source compliant license.
-See the file "License.txt" for details. Since it is not obvious for many
-people how this license applies to their own projects, here's a short guide:
+The AVR firmware driver is published under the GNU General Public License
+Version 2 (GPL2). See the file "License.txt" for details.
-(1) The USB driver and all your modifications to the driver itself are owned
-by Objective Development. You must give us a worldwide, perpetual,
-irrevocable royalty free license for your modifications.
+If you decide for the free GPL2, we STRONGLY ENCOURAGE you to do the following
+things IN ADDITION to the obligations from the GPL2:
-(2) Since you own the code you have written (except where you modify our
-driver), you can (at least in principle) determine the license for it freely.
-However, to "pay" for the USB driver code you link against, we demand that
-you choose an Open Source compliant license (compatible with our license) for
-your source code and the hardware circuit diagrams. Simply attach your
-license of choice to your parts of the project and leave our "License.txt" in
-the "usbdrv" subdirectory.
+(1) Publish your entire project on a web site and drop us a note with the URL.
+Use the form at http://www.obdev.at/avrusb/feedback.html for your submission.
-(3) We also demand that you publish your work on the Internet and drop us a
-note with the URL. The publication must meet certain formal criteria (files
-distributed, file formats etc.). See the file "License.txt" for details.
+(2) Adhere to minimum publication standards. Please include AT LEAST:
+ - a circuit diagram in PDF, PNG or GIF format
+ - full source code for the host software
+ - a Readme.txt file in ASCII format which describes the purpose of the
+ project and what can be found in which directories and which files
+ - a reference to http://www.obdev.at/avrusb/
-Other than that, you are allowed to manufacture any number of units and sell
-them for any price. If you like our driver, we also encourage you to make a
-donation on our web site.
+(3) If you improve the driver firmware itself, please give us a free license
+to your modifications for our commercial license offerings.
COMMERCIAL LICENSES FOR AVR-USB
===============================
-If you don't want to publish your source code and the circuit diagrams under
-an Open Source license, you can simply pay money for AVR-USB. As an
-additional benefit you get USB PIDs for free, licensed exclusively to you.
-See http://www.obdev.at/products/avrusb/license.html for details.
+If you don't want to publish your source code under the terms of the GPL2,
+you can simply pay money for AVR-USB. As an additional benefit you get
+USB PIDs for free, licensed exclusively to you. See the file
+"CommercialLicense.txt" for details.
* Creation Date: 2006-03-01
* Tabsize: 4
* Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: iarcompat.h 174 2006-03-23 10:09:01Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: iarcompat.h 275 2007-03-20 09:58:28Z cs $
*/
/*
* Creation Date: 2005-01-16
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: oddebug.c 215 2006-07-10 21:54:51Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: oddebug.c 275 2007-03-20 09:58:28Z cs $
*/
#include "oddebug.h"
#if DEBUG_LEVEL > 0
-static uchar Warning__Never_compile_production_devices_with_debugging;
-/* The "#warning" preprocessor directive is non-standard. The unused static
- * variable above should give a compiler warning on all compilers.
- */
+#warning "Never compile production devices with debugging enabled"
static void uartPutc(char c)
{
* Creation Date: 2005-01-16
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: oddebug.h 215 2006-07-10 21:54:51Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: oddebug.h 275 2007-03-20 09:58:28Z cs $
*/
#ifndef __oddebug_h_included__
* Creation Date: 2005-04-01
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: usbconfig-prototype.h 216 2006-07-14 21:51:00Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbconfig-prototype.h 358 2007-06-23 13:30:30Z cs $
*/
#ifndef __usbconfig_h_included__
This file is an example configuration (with inline documentation) for the USB
driver. It configures AVR-USB for an ATMega8 with USB D+ connected to Port D
bit 2 (which is also hardware interrupt 0) and USB D- to Port D bit 0. You may
-wire the lines to any other port, as long as D- is on bit 0 and D+ is also
-wired to INT0.
+wire the lines to any other port, as long as D+ is also wired to INT0.
To create your own usbconfig.h file, copy this file to the directory
containing "usbdrv" (that is your project firmware source directory) and
rename it to "usbconfig.h". Then edit it accordingly.
* This may be any bit in the port. Please note that D+ must also be connected
* to interrupt pin INT0!
*/
+/* #define USB_CFG_CLOCK_KHZ (F_CPU/1000) */
+/* Clock rate of the AVR in MHz. Legal values are 12000, 16000 or 16500.
+ * The 16.5 MHz version of the code requires no crystal, it tolerates +/- 1%
+ * deviation from the nominal frequency. All other rates require a precision
+ * of 2000 ppm and thus a crystal!
+ * Default if not specified: 12 MHz
+ */
/* ----------------------- Optional Hardware Config ------------------------ */
* above) where the 1.5k pullup resistor is connected. See description
* above for details.
*/
-/* #define USB_BUFFER_SECTION ".bss" */
-/* The USB receive buffer (variable "usbRxBuf") with a length of 22 bytes
- * MUST NOT cross a 256 byte boundary. We have introduced this configuration
- * option to allow you to change the data segment where this buffer is
- * allocated. If you have problems with the default segment (start of .bss),
- * you may change this setting. See the comment in usbdrv.h for details.
- * On IAR C, the default is the TINY_Z segment (first 256 bytes). You must
- * change this default for devices which don't have RAM below 0x100.
- */
/* --------------------------- Functional Range ---------------------------- */
* The value is in milliamperes. [It will be divided by two since USB
* communicates power requirements in units of 2 mA.]
*/
-#define USB_CFG_SAMPLE_EXACT 1
-/* This variable affects Sampling Jitter for USB receiving. When it is 0, the
- * driver guarantees a sampling window of 1/2 bit. The USB spec requires
- * that the receiver has at most 1/4 bit sampling window. The 1/2 bit window
- * should still work reliably enough because we work at low speed. If you want
- * to meet the spec, set this value to 1. This will unroll a loop which
- * results in bigger code size.
- * If you have problems with long cables, try setting this value to 1.
- */
#define USB_CFG_IMPLEMENT_FN_WRITE 0
/* Set this to 1 if you want usbFunctionWrite() to be called for control-out
* transfers. Set it to 0 if you don't need it and want to save a couple of
* Don't forget to keep the array and this define in sync!
*/
+/* #define USB_PUBLIC static */
+/* Use the define above if you #include usbdrv.c instead of linking against it.
+ * This technique saves a couple of bytes in flash memory.
+ */
+
/* ------------------- Fine Control over USB Descriptors ------------------- */
/* If you don't want to use the driver's default USB descriptors, you can
* provide our own. These can be provided as (1) fixed length static data in
* Creation Date: 2004-12-29
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: usbdrv.c 222 2006-07-17 15:07:34Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrv.c 350 2007-06-13 11:43:16Z cs $
*/
#include "iarcompat.h"
/* ------------------------------------------------------------------------- */
/* raw USB registers / interface to assembler code: */
-/* usbRxBuf MUST be in 1 byte addressable range (because usbInputBuf is only 1 byte) */
-__no_init uchar usbRxBuf[2][USB_BUFSIZE] __attribute__ ((section (USB_BUFFER_SECTION))) IAR_SECTION(USB_BUFFER_SECTION);/* raw RX buffer: PID, 8 bytes data, 2 bytes CRC */
+uchar usbRxBuf[2*USB_BUFSIZE]; /* raw RX buffer: PID, 8 bytes data, 2 bytes CRC */
+uchar usbInputBufOffset; /* offset in usbRxBuf used for low level receiving */
uchar usbDeviceAddr; /* assigned during enumeration, defaults to 0 */
uchar usbNewDeviceAddr; /* device ID which should be set after status phase */
uchar usbConfiguration; /* currently selected configuration. Administered by driver, but not used */
-uchar usbInputBuf; /* ptr to raw buffer used for receiving */
-uchar usbAppBuf; /* ptr to raw buffer passed to app for processing */
-volatile schar usbRxLen; /* = 0; number of bytes in usbAppBuf; 0 means free */
+volatile schar usbRxLen; /* = 0; number of bytes in usbRxBuf; 0 means free, -1 for flow control */
uchar usbCurrentTok; /* last token received, if more than 1 rx endpoint: MSb=endpoint */
uchar usbRxToken; /* token for data we received; if more than 1 rx endpoint: MSb=endpoint */
uchar usbMsgLen = 0xff; /* remaining number of bytes, no msg to send if -1 (see usbMsgPtr) */
/* USB status registers / not shared with asm code */
uchar *usbMsgPtr; /* data to transmit next -- ROM or RAM address */
static uchar usbMsgFlags; /* flag values see below */
-static uchar usbIsReset; /* = 0; USB bus is in reset phase */
#define USB_FLG_TX_PACKET (1<<0)
/* Leave free 6 bits after TX_PACKET. This way we can increment usbMsgFlags to toggle TX_PACKET */
};
#endif
-#if USB_CFG_DESCR_PROPS_STRING_DEVICE == 0 && USB_CFG_DEVICE_NAME_LEN
-#undef USB_CFG_DESCR_PROPS_STRING_DEVICE
-#define USB_CFG_DESCR_PROPS_STRING_DEVICE sizeof(usbDescriptorStringDevice)
+#if USB_CFG_DESCR_PROPS_STRING_PRODUCT == 0 && USB_CFG_DEVICE_NAME_LEN
+#undef USB_CFG_DESCR_PROPS_STRING_PRODUCT
+#define USB_CFG_DESCR_PROPS_STRING_PRODUCT sizeof(usbDescriptorStringDevice)
PROGMEM int usbDescriptorStringDevice[] = {
USB_STRING_DESCRIPTOR_HEADER(USB_CFG_DEVICE_NAME_LEN),
USB_CFG_DEVICE_NAME
PROGMEM char usbDescriptorDevice[] = { /* USB device descriptor */
18, /* sizeof(usbDescriptorDevice): length of descriptor in bytes */
USBDESCR_DEVICE, /* descriptor type */
- 0x01, 0x01, /* USB version supported */
+ 0x10, 0x01, /* USB version supported */
USB_CFG_DEVICE_CLASS,
USB_CFG_DEVICE_SUBCLASS,
0, /* protocol */
USB_CFG_DEVICE_ID, /* 2 bytes */
USB_CFG_DEVICE_VERSION, /* 2 bytes */
USB_CFG_DESCR_PROPS_STRING_VENDOR != 0 ? 1 : 0, /* manufacturer string index */
- USB_CFG_DESCR_PROPS_STRING_DEVICE != 0 ? 2 : 0, /* product string index */
+ USB_CFG_DESCR_PROPS_STRING_PRODUCT != 0 ? 2 : 0, /* product string index */
USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER != 0 ? 3 : 0, /* serial number string index */
1, /* number of configurations */
};
/* ------------------------------------------------------------------------- */
#if USB_CFG_HAVE_INTRIN_ENDPOINT
-uchar usbTxPacketCnt1;
-
-void usbSetInterrupt(uchar *data, uchar len)
+USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len)
{
uchar *p, i;
if(len > 8) /* interrupt transfers are limited to 8 bytes */
len = 8;
#endif
- i = USBPID_DATA1;
- if(usbTxPacketCnt1 & 1)
- i = USBPID_DATA0;
- if(usbTxLen1 & 0x10){ /* packet buffer was empty */
- usbTxPacketCnt1++;
+ if(usbTxLen1 & 0x10){ /* packet buffer was empty */
+ usbTxBuf1[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
}else{
- usbTxLen1 = USBPID_NAK; /* avoid sending incomplete interrupt data */
+ usbTxLen1 = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */
}
- p = usbTxBuf1;
- *p++ = i;
+ p = usbTxBuf1 + 1;
for(i=len;i--;)
*p++ = *data++;
usbCrc16Append(&usbTxBuf1[1], len);
#endif
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-uchar usbTxPacketCnt3;
-
-void usbSetInterrupt3(uchar *data, uchar len)
+USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len)
{
uchar *p, i;
- i = USBPID_DATA1;
- if(usbTxPacketCnt3 & 1)
- i = USBPID_DATA0;
- if(usbTxLen3 & 0x10){ /* packet buffer was empty */
- usbTxPacketCnt3++;
+ if(usbTxLen3 & 0x10){ /* packet buffer was empty */
+ usbTxBuf3[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
}else{
- usbTxLen3 = USBPID_NAK; /* avoid sending incomplete interrupt data */
+ usbTxLen3 = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */
}
- p = usbTxBuf3;
- *p++ = i;
+ p = usbTxBuf3 + 1;
for(i=len;i--;)
*p++ = *data++;
usbCrc16Append(&usbTxBuf3[1], len);
#endif
-static uchar usbRead(uchar *data, uchar len)
+static uchar usbRead(uchar *data, uchar len)
{
#if USB_CFG_IMPLEMENT_FN_READ
if(usbMsgFlags & USB_FLG_USE_DEFAULT_RW){
/* We use if() cascades because the compare is done byte-wise while switch()
* is int-based. The if() cascades are therefore more efficient.
*/
- DBG2(0x10 + ((usbRxToken >> 6) & 3), data, len);
+/* usbRxToken can be:
+ * 0x2d 00101101 (USBPID_SETUP for endpoint 0)
+ * 0xe1 11100001 (USBPID_OUT for endpoint 0)
+ * 0xff 11111111 (USBPID_OUT for endpoint 1)
+ */
+ DBG2(0x10 + ((usbRxToken >> 1) & 3), data, len); /* SETUP0=12; OUT0=10; OUT1=13 */
#if USB_CFG_IMPLEMENT_FN_WRITEOUT
- if(usbRxToken & 0x80){
+ if(usbRxToken == 0xff){
usbFunctionWriteOut(data, len);
return; /* no reply expected, hence no usbMsgPtr, usbMsgFlags, usbMsgLen set */
}
- if(usbRxToken == (uchar)(USBPID_SETUP & 0x7f)){ /* MSb contains endpoint (== 0) */
-#else
- if(usbRxToken == (uchar)USBPID_SETUP){
#endif
+ if(usbRxToken == (uchar)USBPID_SETUP){
+ usbTxLen = USBPID_NAK; /* abort pending transmit */
if(len == 8){ /* Setup size must be always 8 bytes. Ignore otherwise. */
uchar type = rq->bmRequestType & USBRQ_TYPE_MASK;
if(type == USBRQ_TYPE_STANDARD){
}else if(rq->wValue.bytes[0] == 1){
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor)
}else if(rq->wValue.bytes[0] == 2){
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_DEVICE, usbDescriptorStringDevice)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice)
}else if(rq->wValue.bytes[0] == 3){
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber)
}else if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
SET_REPLY_LEN(1);
#if USB_CFG_HAVE_INTRIN_ENDPOINT
}else if(rq->bRequest == USBRQ_SET_INTERFACE){ /* 11 */
- usbTxPacketCnt1 = 0; /* reset data toggling for interrupt endpoint */
+ USB_SET_DATATOKEN1(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
# if USB_CFG_HAVE_INTRIN_ENDPOINT3
- usbTxPacketCnt3 = 0; /* reset data toggling for interrupt endpoint */
+ USB_SET_DATATOKEN3(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
# endif
# if USB_CFG_IMPLEMENT_HALT
usbTxLen1 = USBPID_NAK;
}else if(rq->bRequest == USBRQ_CLEAR_FEATURE || rq->bRequest == USBRQ_SET_FEATURE){ /* 1|3 */
if(rq->wValue.bytes[0] == 0 && rq->wIndex.bytes[0] == 0x81){ /* feature 0 == HALT for endpoint == 1 */
usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL;
- usbTxPacketCnt1 = 0; /* reset data toggling for interrupt endpoint */
+ USB_SET_DATATOKEN1(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
# if USB_CFG_HAVE_INTRIN_ENDPOINT3
- usbTxPacketCnt3 = 0; /* reset data toggling for interrupt endpoint */
+ USB_SET_DATATOKEN3(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
# endif
}
# endif
static void usbBuildTxBlock(void)
{
-uchar wantLen, len, txLen, token;
+uchar wantLen, len, txLen, token;
wantLen = usbMsgLen;
if(wantLen > 8)
/* ------------------------------------------------------------------------- */
-void usbPoll(void)
+USB_PUBLIC void usbPoll(void)
{
-uchar len;
+schar len;
+uchar i;
if((len = usbRxLen) > 0){
/* We could check CRC16 here -- but ACK has already been sent anyway. If you
* need data integrity checks with this driver, check the CRC in your app
* code and report errors back to the host. Since the ACK was already sent,
* retries must be handled on application level.
- * unsigned crc = usbCrc16((uchar *)(unsigned)(usbAppBuf + 1), usbRxLen - 3);
+ * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3);
*/
- len -= 3; /* remove PID and CRC */
- if(len < 128){ /* no overflow */
- converter_t appBuf;
- appBuf.ptr = (uchar *)usbRxBuf;
- appBuf.bytes[0] = usbAppBuf;
- appBuf.bytes[0]++;
- usbProcessRx(appBuf.ptr, len);
- }
+ usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len - 3);
#if USB_CFG_HAVE_FLOWCONTROL
if(usbRxLen > 0) /* only mark as available if not inactivated */
usbRxLen = 0;
#else
- usbRxLen = 0; /* mark rx buffer as available */
+ usbRxLen = 0; /* mark rx buffer as available */
#endif
}
- if(usbMsgLen != 0xff){ /* transmit data pending? */
- if(usbTxLen & 0x10) /* transmit system idle */
+ if(usbTxLen & 0x10){ /* transmit system idle */
+ if(usbMsgLen != 0xff){ /* transmit data pending? */
usbBuildTxBlock();
+ }
}
- if(isNotSE0()){ /* SE0 state */
- usbIsReset = 0;
- }else{
- /* check whether SE0 lasts for more than 2.5us (3.75 bit times) */
- if(!usbIsReset){
- uchar i;
- for(i=100;i;i--){
- if(isNotSE0())
- goto notUsbReset;
- }
- usbIsReset = 1;
- usbNewDeviceAddr = 0;
- usbDeviceAddr = 0;
+ for(i = 10; i > 0; i--){
+ if(isNotSE0())
+ break;
+ }
+ if(i == 0){ /* RESET condition, called multiple times during reset */
+ usbNewDeviceAddr = 0;
+ usbDeviceAddr = 0;
#if USB_CFG_IMPLEMENT_HALT
- usbTxLen1 = USBPID_NAK;
+ usbTxLen1 = USBPID_NAK;
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
- usbTxLen3 = USBPID_NAK;
+ usbTxLen3 = USBPID_NAK;
#endif
#endif
- DBG1(0xff, 0, 0);
-notUsbReset:;
- }
+ DBG1(0xff, 0, 0);
}
}
/* ------------------------------------------------------------------------- */
-void usbInit(void)
+USB_PUBLIC void usbInit(void)
{
- usbInputBuf = (uchar)usbRxBuf[0];
- usbAppBuf = (uchar)usbRxBuf[1];
#if USB_INTR_CFG_SET != 0
USB_INTR_CFG |= USB_INTR_CFG_SET;
#endif
USB_INTR_CFG &= ~(USB_INTR_CFG_CLR);
#endif
USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT);
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+ USB_SET_DATATOKEN1(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
+# if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ USB_SET_DATATOKEN3(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
+# endif
+#endif
}
/* ------------------------------------------------------------------------- */
* Creation Date: 2004-12-29
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: usbdrv.h 230 2006-07-18 11:29:00Z cs $
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrv.h 375 2007-07-07 12:01:52Z cs $
*/
#ifndef __usbdrv_h_included__
Please adapt the values in usbconfig.h according to your hardware!
-The device MUST be clocked at 12 MHz. This is more than the 10 MHz allowed by
-an AT90S2313 powered at 4.5V. However, if the supply voltage to maximum clock
-relation is interpolated linearly, an ATtiny2313 meets the requirement by
-specification. In practice, the AT90S2313 can be overclocked and works well.
+The device MUST be clocked at exactly 12 MHz or 16 MHz or at 16.5 MHz +/- 1%.
+See usbconfig-prototype.h for details.
Limitations:
============
-Compiling:
-You should link the usbdrv.o module first because it has special alignment
-requirements for the receive buffer (the buffer must not cross a 256 byte
-page boundary, it must not even touch it at the end). If you can't link it
-first, you must use other measures to ensure alignment.
-Note: gcc does not always assign variable addresses in the order as the modules
-are linked or the variables are declared. You can choose a memory section for
-the receive buffer with the configuration option "USB_BUFFER_SECTION". This
-option defaults to ".bss". If you use your own section, you can place it at
-an arbitrary location with a linker option similar to
-"-Wl,--section-start=.mybuffer=0x800060". Use "avr-nm -ng" on the binary and
-search for "usbRxBuf" to find tbe base address of the 22 bytes rx buffer.
-
Robustness with respect to communication errors:
The driver assumes error-free communication. It DOES check for errors in
the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte,
performance does not permit that. The driver does not check Data0/Data1
toggling, but application software can implement the check.
-Sampling jitter:
-The driver guarantees a sampling window of 1/2 bit. The USB spec requires
-that the receiver has at most 1/4 bit sampling window. The 1/2 bit window
-should still work reliably enough because we work at low speed. If you want
-to meet the spec, define the macro "USB_CFG_SAMPLE_EXACT" to 1 in usbconfig.h.
-This will unroll a loop which results in bigger code size.
-
Input characteristics:
Since no differential receiver circuit is used, electrical interference
robustness may suffer. The driver samples only one of the data lines with
Maximum interrupt duration / CPU cycle consumption:
The driver handles all USB communication during the interrupt service
routine. The routine will not return before an entire USB message is received
-and the reply is sent. This may be up to ca. 1200 cycles = 100us if the host
-conforms to the standard. The driver will consume CPU cycles for all USB
-messages, even if they address another (low-speed) device on the same bus.
+and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if
+the host conforms to the standard. The driver will consume CPU cycles for all
+USB messages, even if they address another (low-speed) device on the same bus.
*/
/* --------------------------- Module Interface ---------------------------- */
/* ------------------------------------------------------------------------- */
-#define USBDRV_VERSION 20060718
+#define USBDRV_VERSION 20070707
/* This define uniquely identifies a driver version. It is a decimal number
* constructed from the driver's release date in the form YYYYMMDD. If the
* driver's behavior or interface changes, you can use this constant to
* older than 2006-01-25.
*/
-#ifndef __ASSEMBLER__
+#ifndef USB_PUBLIC
+#define USB_PUBLIC
+#endif
+/* USB_PUBLIC is used as declaration attribute for all functions exported by
+ * the USB driver. The default is no attribute (see above). You may define it
+ * to static either in usbconfig.h or from the command line if you include
+ * usbdrv.c instead of linking against it. Including the C module of the driver
+ * directly in your code saves a couple of bytes in flash memory.
+ */
+
+#ifndef __ASSEMBLER__
#ifndef uchar
#define uchar unsigned char
#endif
struct usbRequest; /* forward declaration */
-extern void usbInit(void);
+USB_PUBLIC void usbInit(void);
/* This function must be called before interrupts are enabled and the main
* loop is entered.
*/
-extern void usbPoll(void);
+USB_PUBLIC void usbPoll(void);
/* This function must be called at regular intervals from the main loop.
* Maximum delay between calls is somewhat less than 50ms (USB timeout for
* accepting a Setup message). Otherwise the device will not be recognized.
* Please note that debug outputs through the UART take ~ 0.5ms per byte
* at 19200 bps.
*/
-extern uchar *usbMsgPtr;
+extern uchar *usbMsgPtr;
/* This variable may be used to pass transmit data to the driver from the
* implementation of usbFunctionWrite(). It is also used internally by the
* driver for standard control requests.
*/
-extern uchar usbFunctionSetup(uchar data[8]);
+USB_PUBLIC uchar usbFunctionSetup(uchar data[8]);
/* This function is called when the driver receives a SETUP transaction from
* the host which is not answered by the driver itself (in practice: class and
* vendor requests). All control transfers start with a SETUP transaction where
* Note that calls to the functions usbFunctionRead() and usbFunctionWrite()
* are only done if enabled by the configuration in usbconfig.h.
*/
-extern uchar usbFunctionDescriptor(struct usbRequest *rq);
+USB_PUBLIC uchar usbFunctionDescriptor(struct usbRequest *rq);
/* You need to implement this function ONLY if you provide USB descriptors at
* runtime (which is an expert feature). It is very similar to
* usbFunctionSetup() above, but it is called only to request USB descriptor
* data. See the documentation of usbFunctionSetup() above for more info.
*/
#if USB_CFG_HAVE_INTRIN_ENDPOINT
-void usbSetInterrupt(uchar *data, uchar len);
+USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len);
/* This function sets the message which will be sent during the next interrupt
* IN transfer. The message is copied to an internal buffer and must not exceed
* a length of 8 bytes. The message may be 0 bytes long just to indicate the
* message already buffered will be lost.
*/
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-void usbSetInterrupt3(uchar *data, uchar len);
+USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len);
extern volatile uchar usbTxLen3;
#define usbInterruptIsReady3() (usbTxLen3 & 0x10)
/* Same as above for endpoint 3 */
*/
#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */
#if USB_CFG_IMPLEMENT_FN_WRITE
-extern uchar usbFunctionWrite(uchar *data, uchar len);
+USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len);
/* This function is called by the driver to provide a control transfer's
* payload data (control-out). It is called in chunks of up to 8 bytes. The
* total count provided in the current control transfer can be obtained from
*/
#endif /* USB_CFG_IMPLEMENT_FN_WRITE */
#if USB_CFG_IMPLEMENT_FN_READ
-extern uchar usbFunctionRead(uchar *data, uchar len);
+USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len);
/* This function is called by the driver to ask the application for a control
* transfer's payload data (control-in). It is called in chunks of up to 8
* bytes each. You should copy the data to the location given by 'data' and
*/
#endif /* USB_CFG_IMPLEMENT_FN_READ */
#if USB_CFG_IMPLEMENT_FN_WRITEOUT
-extern void usbFunctionWriteOut(uchar *data, uchar len);
+USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len);
/* This function is called by the driver when data on interrupt-out or bulk-
* out endpoint 1 is received. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT
* to 1 in usbconfig.h to get this function called.
* USB bus. It is only available if you have defined the constants
* USB_CFG_PULLUP_IOPORT and USB_CFG_PULLUP_BIT in usbconfig.h.
*/
-#define usbDeviceDisconnect() (USB_PULLUP_OUT &= ~(1<<USB_CFG_PULLUP_BIT))
+#define usbDeviceDisconnect() ((USB_PULLUP_DDR &= ~(1<<USB_CFG_PULLUP_BIT)), \
+ (USB_PULLUP_OUT &= ~(1<<USB_CFG_PULLUP_BIT)))
/* This macro (intended to look like a function) disconnects the device from
* the USB bus. It is only available if you have defined the constants
* USB_CFG_PULLUP_IOPORT and USB_CFG_PULLUP_BIT in usbconfig.h.
*/
#endif
-extern uchar usbTxPacketCnt1;
-extern uchar usbTxPacketCnt3;
-/* The two variables above are mostly for internal use by the driver. You may
- * have to reset usbTxPacketCnt1 to 0 if you start data toggling at DATA0 for
- * interrupt-IN endpoint 1 and usbTxPacketCnt3 for interrupt-IN endpoint 3
- * respectively.
+#define USB_SET_DATATOKEN1(token) usbTxBuf1[0] = token
+#define USB_SET_DATATOKEN3(token) usbTxBuf3[0] = token
+/* These two macros can be used by application software to reset data toggling
+ * for interrupt-in endpoints 1 and 3.
*/
#endif /* __ASSEMBLER__ */
#ifndef USB_CFG_DESCR_PROPS_STRING_VENDOR
#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0
#endif
-#ifndef USB_CFG_DESCR_PROPS_STRING_DEVICE
-#define USB_CFG_DESCR_PROPS_STRING_DEVICE 0
+#ifndef USB_CFG_DESCR_PROPS_STRING_PRODUCT
+#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0
#endif
#ifndef USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER
#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0
/* ------------------------- Constant definitions -------------------------- */
/* ------------------------------------------------------------------------- */
-#if !defined USB_CFG_VENDOR_ID || !defined USB_CFG_DEVICE_ID
-static uchar Warning_You_should_define_USB_CFG_VENDOR_ID_and_USB_CFG_DEVICE_ID_in_usbconfig_h;
-/* The unused variable above should generate a warning on all compilers. IAR cc
- * does not understand the "#warning" preprocessor direcetive.
- * If the user has not defined IDs, we default to obdev's free IDs.
+#if !defined __ASSEMBLER__ && (!defined USB_CFG_VENDOR_ID || !defined USB_CFG_DEVICE_ID)
+#warning "You should define USB_CFG_VENDOR_ID and USB_CFG_DEVICE_ID in usbconfig.h"
+/* If the user has not defined IDs, we default to obdev's free IDs.
* See USBID-License.txt for details.
*/
#endif
# endif
#endif
-#ifndef USB_BUFFER_SECTION
-# define USB_BUFFER_SECTION ".bss" /* if user has not selected a named section */
-#endif
-
/* Derive Output, Input and DataDirection ports from port names */
#ifndef USB_CFG_IOPORTNAME
#error "You must define USB_CFG_IOPORTNAME in usbconfig.h, see usbconfig-prototype.h"
#define USBPID_STALL 0x1e
#ifndef __ASSEMBLER__
+
+extern uchar usbTxBuf1[USB_BUFSIZE], usbTxBuf3[USB_BUFSIZE];
+
typedef union usbWord{
unsigned word;
uchar bytes[2];
/* Name: usbdrvasm.S
* Project: AVR USB driver
* Author: Christian Starkjohann
- * Creation Date: 2004-12-29
+ * Creation Date: 2007-06-13
* Tabsize: 4
- * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
- * This Revision: $Id: usbdrvasm.S 218 2006-07-15 17:08:14Z cs $
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * Revision: $Id$
*/
/*
General Description:
-This module implements the assembler part of the USB driver. See usbdrv.h
-for a description of the entire driver.
-Since almost all of this code is timing critical, don't change unless you
-really know what you are doing! Many parts require not only a maximum number
-of CPU cycles, but even an exact number of cycles!
-
-
-Timing constraints according to spec (in bit times):
-timing subject min max CPUcycles
----------------------------------------------------------------------------
-EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
-EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
-DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
+This module is the assembler part of the USB driver. This file contains
+general code (preprocessor acrobatics and CRC computation) and then includes
+the file appropriate for the given clock rate.
*/
#include "iarcompat.h"
#define cnt r19
#define x3 r20
#define x4 r21
+#define bitcnt r22
+#define phase x4
+#define leap x4
/* Some assembler dependent definitions and declarations: */
# define lo8(x) LOW(x)
# define hi8(x) ((x)>>8) /* not HIGH to allow XLINK to make a proper range check */
- extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBuf
- extern usbCurrentTok, usbRxLen, usbRxToken, usbAppBuf, usbTxLen
+ extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset
+ extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen
extern usbTxBuf, usbMsgLen, usbTxLen1, usbTxBuf1, usbTxLen3, usbTxBuf3
public usbCrc16
public usbCrc16Append
#endif /* __IAR_SYSTEMS_ASM__ */
-
-SIG_INTERRUPT0:
-;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
-;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
-;max allowable interrupt latency: 32 cycles -> max 25 cycles interrupt disable
-;max stack usage: [ret(2), x1, SREG, x2, cnt, shift, YH, YL, x3, x4] = 11 bytes
-usbInterrupt:
-;order of registers pushed:
-;x1, SREG, x2, cnt, shift, [YH, YL, x3]
- push x1 ;2 push only what is necessary to sync with edge ASAP
- in x1, SREG ;1
- push x1 ;2
-;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
-;sync up with J to K edge during sync pattern -- use fastest possible loops
-;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
-#if !USB_CFG_SAMPLE_EXACT
- ldi x1, 5 ;1 setup a timeout for waitForK
-#endif
-waitForJ:
- sbis USBIN, USBMINUS ;1 wait for D- == 1
- rjmp waitForJ ;2
-#if USB_CFG_SAMPLE_EXACT
-;The following code represents the unrolled loop in the else branch. It
-;results in a sampling window of 1/4 bit which meets the spec.
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- nop
- nop2
-foundK:
-#else
-waitForK:
- dec x1 ;1
- sbic USBIN, USBMINUS ;1 wait for D- == 0
- brne waitForK ;2
-#endif
-;{2, 6} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
-;we have 1 bit time for setup purposes, then sample again:
- push x2 ;2
- push cnt ;2
- push shift ;2
-shortcutEntry:
- ldi cnt, 1 ;1 pre-init bit counter (-1 because no dec follows, -1 because 1 bit already sampled)
- ldi x2, 1<<USB_CFG_DPLUS_BIT ;1 -> 8 edge sync ended with D- == 0
-;now wait until SYNC byte is over. Wait for either 2 bits low (success) or 2 bits high (failure)
-waitNoChange:
- in x1, USBIN ;1 <-- sample, timing: edge + {2, 6} cycles
- eor x2, x1 ;1
- sbrc x2, USBMINUS ;1 | 2
- ldi cnt, 2 ;1 | 0 cnt = numBits - 1 (because dec follows)
- mov x2, x1 ;1
- dec cnt ;1
- brne waitNoChange ;2 | 1
- sbrc x1, USBMINUS ;2
- rjmp sofError ;0 two consecutive "1" bits -> framing error
-;start reading data, but don't check for bitstuffing because these are the
-;first bits. Use the cycles for initialization instead. Note that we read and
-;store the binary complement of the data stream because eor results in 1 for
-;a change and 0 for no change.
- in x1, USBIN ;1 <-- sample bit 0, timing: edge + {3, 7} cycles
- eor x2, x1 ;1
- ldi shift, 0x00 ;1 prepare for bitstuff check later on in loop
- bst x2, USBMINUS ;1
- bld shift, 0 ;1
- push YH ;2 -> 7
- in x2, USBIN ;1 <-- sample bit 1, timing: edge + {2, 6} cycles
- eor x1, x2 ;1
- bst x1, USBMINUS ;1
- bld shift, 1 ;1
- push YL ;2
- lds YL, usbInputBuf ;2 -> 8
- in x1, USBIN ;1 <-- sample bit 2, timing: edge + {2, 6} cycles
- eor x2, x1 ;1
- bst x2, USBMINUS ;1
- bld shift, 2 ;1
- ldi cnt, USB_BUFSIZE;1
- ldi YH, hi8(usbRxBuf);1 assume that usbRxBuf does not cross a page
- push x3 ;2 -> 8
- in x2, USBIN ;1 <-- sample bit 3, timing: edge + {2, 6} cycles
- eor x1, x2 ;1
- bst x1, USBMINUS ;1
- bld shift, 3 ;1
- ser x3 ;1
- nop ;1
- rjmp rxbit4 ;2 -> 8
-
-shortcutToStart: ;{,43} into next frame: max 5.5 sync bits missed
-#if !USB_CFG_SAMPLE_EXACT
- ldi x1, 5 ;2 setup timeout
-#endif
-waitForJ1:
- sbis USBIN, USBMINUS ;1 wait for D- == 1
- rjmp waitForJ1 ;2
-#if USB_CFG_SAMPLE_EXACT
-;The following code represents the unrolled loop in the else branch. It
-;results in a sampling window of 1/4 bit which meets the spec.
- sbis USBIN, USBMINUS
- rjmp foundK1
- sbis USBIN, USBMINUS
- rjmp foundK1
- sbis USBIN, USBMINUS
- rjmp foundK1
- nop
- nop2
-foundK1:
-#else
-waitForK1:
- dec x1 ;1
- sbic USBIN, USBMINUS ;1 wait for D- == 0
- brne waitForK1 ;2
-#endif
- pop YH ;2 correct stack alignment
- nop2 ;2 delay for the same time as the pushes in the original code
- rjmp shortcutEntry ;2
-
-; ################# receiver loop #################
-; extra jobs done during bit interval:
-; bit 6: se0 check
-; bit 7: or, store, clear
-; bit 0: recover from delay [SE0 is unreliable here due to bit dribbling in hubs]
-; bit 1: se0 check
-; bit 2: se0 check
-; bit 3: overflow check
-; bit 4: se0 check
-; bit 5: rjmp
-
-; stuffed* helpers have the functionality of a subroutine, but we can't afford
-; the overhead of a call. We therefore need a separate routine for each caller
-; which jumps back appropriately.
-
-stuffed5: ;1 for branch taken
- in x2, USBIN ;1 <-- sample @ +1
- andi x2, USBMASK ;1
- breq se0a ;1
- andi x3, ~0x20 ;1
- ori shift, 0x20 ;1
- rjmp rxbit6 ;2
-
-stuffed6: ;1 for branch taken
- in x1, USBIN ;1 <-- sample @ +1
- andi x1, USBMASK ;1
- breq se0a ;1
- andi x3, ~0x40 ;1
- ori shift, 0x40 ;1
- rjmp rxbit7 ;2
-
-; This is somewhat special because it has to compensate for the delay in bit 7
-stuffed7: ;1 for branch taken
- andi x1, USBMASK ;1 already sampled by caller
- breq se0a ;1
- mov x2, x1 ;1 ensure correct NRZI sequence
- ori shift, 0x80 ;1 no need to set reconstruction in x3: shift has already been used
- in x1, USBIN ;1 <-- sample bit 0
- rjmp unstuffed7 ;2
-
-stuffed0: ;1 for branch taken
- in x1, USBIN ;1 <-- sample @ +1
- andi x1, USBMASK ;1
- breq se0a ;1
- andi x3, ~0x01 ;1
- ori shift, 0x01 ;1
- rjmp rxbit1 ;2
-
-;-----------------------------
-rxLoop:
- breq stuffed5 ;1
-rxbit6:
- in x1, USBIN ;1 <-- sample bit 6
- andi x1, USBMASK ;1
- breq se0a ;1
- eor x2, x1 ;1
- bst x2, USBMINUS;1
- bld shift, 6 ;1
- cpi shift, 0x02 ;1
- brlo stuffed6 ;1
-rxbit7:
- in x2, USBIN ;1 <-- sample bit 7
- eor x1, x2 ;1
- bst x1, USBMINUS;1
- bld shift, 7 ;1
- eor x3, shift ;1 x3 is 0 at bit locations we changed, 1 at others
- st y+, x3 ;2 the eor above reconstructed modified bits and inverted rx data
- ser x3 ;1
-rxbit0:
- in x1, USBIN ;1 <-- sample bit 0
- cpi shift, 0x04 ;1
- brlo stuffed7 ;1
-unstuffed7:
- eor x2, x1 ;1
- bst x2, USBMINUS;1
- bld shift, 0 ;1
- andi shift, 0xf9 ;1
- breq stuffed0 ;1
-rxbit1:
- in x2, USBIN ;1 <-- sample bit 1
- andi x2, USBMASK ;1
-se0a: ; enlarge jump range to SE0
- breq se0 ;1 check for SE0 more often close to start of byte
- eor x1, x2 ;1
- bst x1, USBMINUS;1
- bld shift, 1 ;1
- andi shift, 0xf3 ;1
- breq stuffed1 ;1
-rxbit2:
- in x1, USBIN ;1 <-- sample bit 2
- andi x1, USBMASK ;1
- breq se0 ;1
- eor x2, x1 ;1
- bst x2, USBMINUS;1
- bld shift, 2 ;1
- andi shift, 0xe7 ;1
- breq stuffed2 ;1
-rxbit3:
- in x2, USBIN ;1 <-- sample bit 3
- eor x1, x2 ;1
- bst x1, USBMINUS;1
- bld shift, 3 ;1
- dec cnt ;1 check for buffer overflow
- breq overflow ;1
- andi shift, 0xcf ;1
- breq stuffed3 ;1
-rxbit4:
- in x1, USBIN ;1 <-- sample bit 4
- andi x1, USBMASK ;1
- breq se0 ;1
- eor x2, x1 ;1
- bst x2, USBMINUS;1
- bld shift, 4 ;1
- andi shift, 0x9f ;1
- breq stuffed4 ;1
-rxbit5:
- in x2, USBIN ;1 <-- sample bit 5
- eor x1, x2 ;1
- bst x1, USBMINUS;1
- bld shift, 5 ;1
- andi shift, 0x3f ;1
- rjmp rxLoop ;2
-;-----------------------------
-
-stuffed1: ;1 for branch taken
- in x2, USBIN ;1 <-- sample @ +1
- andi x2, USBMASK ;1
- breq se0 ;1
- andi x3, ~0x02 ;1
- ori shift, 0x02 ;1
- rjmp rxbit2 ;2
-
-stuffed2: ;1 for branch taken
- in x1, USBIN ;1 <-- sample @ +1
- andi x1, USBMASK ;1
- breq se0 ;1
- andi x3, ~0x04 ;1
- ori shift, 0x04 ;1
- rjmp rxbit3 ;2
-
-stuffed3: ;1 for branch taken
- in x2, USBIN ;1 <-- sample @ +1
- andi x2, USBMASK ;1
- breq se0 ;1
- andi x3, ~0x08 ;1
- ori shift, 0x08 ;1
- rjmp rxbit4 ;2
-
-stuffed4: ;1 for branch taken
- in x1, USBIN ;1 <-- sample @ +1
- andi x1, USBMASK ;1
- breq se0 ;1
- andi x3, ~0x10 ;1
- ori shift, 0x10 ;1
- rjmp rxbit5 ;2
-
-;################ end receiver loop ###############
-
-overflow: ; ignore package if buffer overflow
- rjmp rxDoReturn ; enlarge jump range
-
-;This is the only non-error exit point for the software receiver loop
-;{4, 20} cycles after start of SE0, typically {10, 18} after SE0 start = {-6, 2} from end of SE0
-;next sync starts {16,} cycles after SE0 -> worst case start: +4 from next sync start
-;we don't check any CRCs here because there is no time left.
-se0: ;{-6, 2} from end of SE0 / {,4} into next frame
- mov cnt, YL ;1 assume buffer in lower 256 bytes of memory
- lds YL, usbInputBuf ;2 reposition to buffer start
- sub cnt, YL ;1 length of message
- ldi x1, 1<<USB_INTR_PENDING_BIT ;1
- cpi cnt, 3 ;1
- out USB_INTR_PENDING, x1;1 clear pending intr and check flag later. SE0 must be over. {,10} into next frame
- brlo rxDoReturn ;1 ensure valid packet size, ignore others
- ld x1, y ;2 PID
- ldd x2, y+1 ;2 ADDR + 1 bit endpoint number
- mov x3, x2 ;1 store for endpoint number
- andi x2, 0x7f ;1 mask endpoint number bit
- lds shift, usbDeviceAddr;2
- cpi x1, USBPID_SETUP ;1
- breq isSetupOrOut ;2 -> 19 = {13, 21} from SE0 end
- cpi x1, USBPID_OUT ;1
- breq isSetupOrOut ;2 -> 22 = {16, 24} from SE0 end / {,24} into next frame
- cpi x1, USBPID_IN ;1
- breq handleIn ;1
-#define USB_DATA_MASK ~(USBPID_DATA0 ^ USBPID_DATA1)
- andi x1, USB_DATA_MASK ;1
- cpi x1, USBPID_DATA0 & USB_DATA_MASK ;1
- brne rxDoReturn ;1 not a data PID -- ignore
-isData:
- lds x2, usbCurrentTok ;2
- tst x2 ;1
- breq rxDoReturn ;1 for other device or spontaneous data -- ignore
- lds x1, usbRxLen ;2
- cpi x1, 0 ;1
- brne sendNakAndReti ;1 no buffer space available / {30, 38} from SE0 end
-; 2006-03-11: The following two lines fix a problem where the device was not
-; recognized if usbPoll() was called less frequently than once every 4 ms.
- cpi cnt, 4 ;1 zero sized data packets are status phase only -- ignore and ack
- brmi sendAckAndReti ;1 keep rx buffer clean -- we must not NAK next SETUP
- sts usbRxLen, cnt ;2 store received data, swap buffers
- sts usbRxToken, x2 ;2
- lds x1, usbAppBuf ;2
- sts usbAppBuf, YL ;2
- sts usbInputBuf, x1 ;2 buffers now swapped
- rjmp sendAckAndReti ;2 -> {43, 51} from SE0 end
-
-handleIn: ; {18, 26} from SE0 end
- cp x2, shift ;1 shift contains our device addr
- brne rxDoReturn ;1 other device
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
- sbrc x3, 7 ;2 x3 contains addr + endpoint
- rjmp handleIn1 ;0
-#endif
- lds cnt, usbTxLen ;2
- sbrc cnt, 4 ;2
- rjmp sendCntAndReti ;0 -> {27, 35} from SE0 end
- ldi x1, USBPID_NAK ;1
- sts usbTxLen, x1 ;2 buffer is now free
- ldi YL, lo8(usbTxBuf) ;1
- ldi YH, hi8(usbTxBuf) ;1
- rjmp usbSendAndReti ;2 -> {34, 43} from SE0 end
-
-; Comment about when to set usbTxLen to USBPID_NAK:
-; We should set it back when we receive the ACK from the host. This would
-; be simple to implement: One static variable which stores whether the last
-; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
-; ACK. However, we set it back immediately when we send the package,
-; assuming that no error occurs and the host sends an ACK. We save one byte
-; RAM this way and avoid potential problems with endless retries. The rest of
-; the driver assumes error-free transfers anyway.
-
-otherOutOrSetup:
- clr x1
- sts usbCurrentTok, x1
-rxDoReturn:
- pop x3 ;2
- pop YL ;2
- pop YH ;2
- rjmp sofError ;2
-
-isSetupOrOut: ; we must be fast here -- a data package may follow / {,24} into next frame
- cp x2, shift ;1 shift contains our device addr
- brne otherOutOrSetup ;1 other device -- ignore
-#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we need second OUT endpoint, store endpoint address */
- andi x1, 0x7f ;1 mask out MSb in token
- andi x3, 0x80 ;1 mask out all but endpoint address
- or x1, x3 ;1 merge endpoint into currentToken
- sts usbCurrentTok, x1 ;2
- brmi dontResetEP0 ;1 endpoint 1 -> don't reset endpoint 0 input
-#else
- sts usbCurrentTok, x1 ;2
-#endif
-;A transmission can still have data in the output buffer while we receive a
-;SETUP package with an IN phase. To avoid that the old data is sent as a reply,
-;we abort transmission. We don't need to reset usbMsgLen because it is used
-;from the main loop only where the setup is processed anyway.
- ldi x1, USBPID_NAK ;1
- sts usbTxLen, x1 ;2 abort transmission
-dontResetEP0:
- pop x3 ;2
- pop YL ;2
- in x1, USB_INTR_PENDING;1
- sbrc x1, USB_INTR_PENDING_BIT;1 check whether data is already arriving {,41} into next frame
- rjmp shortcutToStart ;2 save the pops and pushes -- a new interrupt is aready pending
-;If the jump above was not taken, we can be at {,2} into the next frame here
- pop YH ;2
-txDoReturn:
-sofError: ; error in start of frame -- ignore frame
- ldi x1, 1<<USB_INTR_PENDING_BIT;1 many int0 events occurred during our processing -- clear pending flag
- out USB_INTR_PENDING, x1;1
- pop shift ;2
- pop cnt ;2
- pop x2 ;2
- pop x1 ;2
- out SREG, x1 ;1
- pop x1 ;2
- reti ;4 -> {,21} into next frame -> up to 3 sync bits missed
-
-sendCntAndReti: ; 19 cycles until SOP
- mov x3, cnt ;1
- rjmp usbSendX3 ;2
-sendNakAndReti: ; 19 cycles until SOP
- ldi x3, USBPID_NAK ;1
- rjmp usbSendX3 ;2
-sendAckAndReti: ; 17 cycles until SOP
- ldi x3, USBPID_ACK ;1
-usbSendX3:
- ldi YL, 20 ;1 'x3' is R20
- ldi YH, 0 ;1
- ldi cnt, 2 ;1
-;;;;rjmp usbSendAndReti fallthrough
-
-; USB spec says:
-; idle = J
-; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
-; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
-; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
-
-;usbSend:
-;pointer to data in 'Y'
-;number of bytes in 'cnt' -- including sync byte
-;uses: x1...x4, shift, cnt, Y
-usbSendAndReti: ; SOP starts 13 cycles after call
- push x4 ;2
- ldi x4, USBMASK ;1 exor mask
- sbi USBOUT, USBMINUS;1 prepare idle state; D+ and D- must have been 0 (no pullups)
- in x1, USBOUT ;1 port mirror for tx loop
- sbi USBDDR, USBMINUS;1
- sbi USBDDR, USBPLUS ;1 set D+ and D- to output: acquire bus
-; need not init x2 (bitstuff history) because sync starts with 0
- ldi shift, 0x80 ;1 sync byte is first byte sent
- rjmp txLoop ;2 -> 13 + 3 = 16 cycles until SOP
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
-handleIn1: ;{23, 31} from SE0
- ldi x1, USBPID_NAK ;1
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
- ldd x2, y+2 ;2
- sbrc x2, 0 ;2 1
- rjmp handleIn3 ;0 2
-#endif
- lds cnt, usbTxLen1 ;2
- sbrc cnt, 4 ;2
- rjmp sendCntAndReti ;0
- sts usbTxLen1, x1 ;2
- ldi YL, lo8(usbTxBuf1);1
- ldi YH, hi8(usbTxBuf1);1
- rjmp usbSendAndReti ;2 -> arrives at usbSendAndReti {34, 42} from SE0
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-handleIn3:
- lds cnt, usbTxLen3 ;2
- sbrc cnt, 4 ;2
- rjmp sendCntAndReti ;0
- sts usbTxLen3, x1 ;2
- ldi YL, lo8(usbTxBuf3);1
- ldi YH, hi8(usbTxBuf3);1
- rjmp usbSendAndReti ;2 -> arrives at usbSendAndReti {39, 47} from SE0
-#endif
-#endif
-
-bitstuff0: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- out USBOUT, x1 ;1 <-- out
- rjmp didStuff0 ;2 branch back 2 cycles earlier
-bitstuff1: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- sec ;1 set carry so that brsh will not jump
- out USBOUT, x1 ;1 <-- out
- rjmp didStuff1 ;2 jump back 1 cycle earler
-bitstuff2: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- rjmp didStuff2 ;2 jump back 3 cycles earlier and do out
-bitstuff3: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- rjmp didStuff3 ;2 jump back earlier
-
-txLoop:
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- out USBOUT, x1 ;1 <-- out
- ror shift ;1
- ror x2 ;1
-didStuff0:
- cpi x2, 0xfc ;1
- brsh bitstuff0 ;1
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- ror shift ;1
- out USBOUT, x1 ;1 <-- out
- ror x2 ;1
- cpi x2, 0xfc ;1
-didStuff1:
- brsh bitstuff1 ;1
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- ror shift ;1
- ror x2 ;1
-didStuff2:
- out USBOUT, x1 ;1 <-- out
- cpi x2, 0xfc ;1
- brsh bitstuff2 ;1
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- ror shift ;1
- ror x2 ;1
-didStuff3:
- cpi x2, 0xfc ;1
- out USBOUT, x1 ;1 <-- out
- brsh bitstuff3 ;1
- nop2 ;2
- ld x3, y+ ;2
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- out USBOUT, x1 ;1 <-- out
- ror shift ;1
- ror x2 ;1
-didStuff4:
- cpi x2, 0xfc ;1
- brsh bitstuff4 ;1
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- ror shift ;1
- out USBOUT, x1 ;1 <-- out
- ror x2 ;1
- cpi x2, 0xfc ;1
-didStuff5:
- brsh bitstuff5 ;1
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- ror shift ;1
- ror x2 ;1
-didStuff6:
- out USBOUT, x1 ;1 <-- out
- cpi x2, 0xfc ;1
- brsh bitstuff6 ;1
- sbrs shift, 0 ;1
- eor x1, x4 ;1
- ror shift ;1
- ror x2 ;1
-didStuff7:
- cpi x2, 0xfc ;1
- out USBOUT, x1 ;1 <-- out
- brsh bitstuff7 ;1
- mov shift, x3 ;1
- dec cnt ;1
- brne txLoop ;2 | 1
- cbr x1, USBMASK ;1 prepare SE0 [spec says EOP may be 15 to 18 cycles]
- pop x4 ;2
- out USBOUT, x1 ;1 <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
- ldi cnt, 2 ;| takes cnt * 3 cycles
-se0Delay: ;|
- dec cnt ;|
- brne se0Delay ;| -> 2 * 3 = 6 cycles
-;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
-;set address only after data packet was sent, not after handshake
- lds x2, usbNewDeviceAddr;2
- subi YL, 20 + 2 ;1
- sbci YH, 0 ;1
- breq skipAddrAssign ;2
- sts usbDeviceAddr, x2 ;0 if not skipped: SE0 is one cycle longer
-skipAddrAssign:
-;end of usbDeviceAddress transfer
- ori x1, USBIDLE ;1
- in x2, USBDDR ;1
- cbr x2, USBMASK ;1 set both pins to input
- out USBOUT, x1 ;1 <-- out J (idle) -- end of SE0 (EOP signal)
- cbr x1, USBMASK ;1 configure no pullup on both pins
- pop x3 ;2
- pop YL ;2
- out USBDDR, x2 ;1 <-- release bus now
- out USBOUT, x1 ;1 set pullup state
- pop YH ;2
- rjmp txDoReturn ;2 [we want to jump to rxDoReturn, but this saves cycles]
-
-
-bitstuff4: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- out USBOUT, x1 ;1 <-- out
- rjmp didStuff4 ;2 jump back 2 cycles earlier
-bitstuff5: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- sec ;1 set carry so that brsh is not taken
- out USBOUT, x1 ;1 <-- out
- rjmp didStuff5 ;2 jump back 1 cycle earlier
-bitstuff6: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- rjmp didStuff6 ;2 jump back 3 cycles earlier and do out there
-bitstuff7: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- rjmp didStuff7 ;2 jump back 4 cycles earlier
-
-; ######################## utility functions ########################
+;----------------------------------------------------------------------------
+; Utility functions
+;----------------------------------------------------------------------------
#ifdef __IAR_SYSTEMS_ASM__
/* Register assignments for usbCrc16 on IAR cc */
st ptr+, resCrcL
st ptr+, resCrcH
ret
+
+
+;----------------------------------------------------------------------------
+; Now include the clock rate specific code
+;----------------------------------------------------------------------------
+
+#ifndef USB_CFG_CLOCK_KHZ
+# define USB_CFG_CLOCK_KHZ 12000
+#endif
+
+#if USB_CFG_CLOCK_KHZ == 12000
+# include "usbdrvasm12.S"
+#elif USB_CFG_CLOCK_KHZ == 16000
+# include "usbdrvasm16.S"
+#elif USB_CFG_CLOCK_KHZ == 16500
+# include "usbdrvasm165.S"
+#else
+# error "USB_CFG_CLOCK_KHZ is not one of the supported rates!"
+#endif
* Creation Date: 2006-03-01
* Tabsize: 4
* Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: Proprietary, free under certain conditions. See Documentation.
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
* This Revision: $Id$
*/
--- /dev/null
+/* Name: usbdrvasm12.S
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2004-12-29
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrvasm12.S 353 2007-06-21 19:05:08Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 12 MHz version of the asssembler part of the USB driver. It
+requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+
+
+Timing constraints according to spec (in bit times):
+timing subject min max CPUcycles
+---------------------------------------------------------------------------
+EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
+EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
+DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
+*/
+
+;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
+;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
+;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
+;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
+;Numbers in brackets are maximum cycles since SOF.
+SIG_INTERRUPT0:
+;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
+ push YL ;2 [35] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1 [37]
+ push YL ;2 [39]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
+waitForJ:
+ sbis USBIN, USBMINUS ;1 [40] wait for D- == 1
+ rjmp waitForJ ;2
+waitForK:
+;The following code results in a sampling window of 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ rjmp sofError
+foundK:
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push YH ;2 [2]
+ lds YL, usbInputBufOffset;2 [4]
+ clr YH ;1 [5]
+ subi YL, lo8(-(usbRxBuf));1 [6]
+ sbci YH, hi8(-(usbRxBuf));1 [7]
+
+ sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
+ rjmp haveTwoBitsK ;2 [10]
+ pop YH ;2 [11] undo the push from before
+ rjmp waitForK ;2 [13] this was not the end of sync, retry
+haveTwoBitsK:
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+ push shift ;2 [16]
+ push x1 ;2 [12]
+ push x2 ;2 [14]
+
+ in x1, USBIN ;1 [17] <-- sample bit 0
+ ldi shift, 0xff ;1 [18]
+ bst x1, USBMINUS ;1 [19]
+ bld shift, 0 ;1 [20]
+ push x3 ;2 [22]
+ push cnt ;2 [24]
+
+ in x2, USBIN ;1 [25] <-- sample bit 1
+ ser x3 ;1 [26] [inserted init instruction]
+ eor x1, x2 ;1 [27]
+ bst x1, USBMINUS ;1 [28]
+ bld shift, 1 ;1 [29]
+ ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
+ rjmp rxbit2 ;2 [32]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+
+unstuff0: ;1 (branch taken)
+ andi x3, ~0x01 ;1 [15]
+ mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
+ in x2, USBIN ;1 [17] <-- sample bit 1 again
+ ori shift, 0x01 ;1 [18]
+ rjmp didUnstuff0 ;2 [20]
+
+unstuff1: ;1 (branch taken)
+ mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
+ andi x3, ~0x02 ;1 [22]
+ ori shift, 0x02 ;1 [23]
+ nop ;1 [24]
+ in x1, USBIN ;1 [25] <-- sample bit 2 again
+ rjmp didUnstuff1 ;2 [27]
+
+unstuff2: ;1 (branch taken)
+ andi x3, ~0x04 ;1 [29]
+ ori shift, 0x04 ;1 [30]
+ mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
+ nop ;1 [32]
+ in x2, USBIN ;1 [33] <-- sample bit 3
+ rjmp didUnstuff2 ;2 [35]
+
+unstuff3: ;1 (branch taken)
+ in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
+ andi x3, ~0x08 ;1 [35]
+ ori shift, 0x08 ;1 [36]
+ rjmp didUnstuff3 ;2 [38]
+
+unstuff4: ;1 (branch taken)
+ andi x3, ~0x10 ;1 [40]
+ in x1, USBIN ;1 [41] <-- sample stuffed bit 4
+ ori shift, 0x10 ;1 [42]
+ rjmp didUnstuff4 ;2 [44]
+
+unstuff5: ;1 (branch taken)
+ andi x3, ~0x20 ;1 [48]
+ in x2, USBIN ;1 [49] <-- sample stuffed bit 5
+ ori shift, 0x20 ;1 [50]
+ rjmp didUnstuff5 ;2 [52]
+
+unstuff6: ;1 (branch taken)
+ andi x3, ~0x40 ;1 [56]
+ in x1, USBIN ;1 [57] <-- sample stuffed bit 6
+ ori shift, 0x40 ;1 [58]
+ rjmp didUnstuff6 ;2 [60]
+
+; extra jobs done during bit interval:
+; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
+; bit 1: se0 check
+; bit 2: overflow check
+; bit 3: recovery from delay [bit 0 tasks took too long]
+; bit 4: none
+; bit 5: none
+; bit 6: none
+; bit 7: jump, eor
+rxLoop:
+ eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ in x1, USBIN ;1 [1] <-- sample bit 0
+ st y+, x3 ;2 [3] store data
+ ser x3 ;1 [4]
+ nop ;1 [5]
+ eor x2, x1 ;1 [6]
+ bst x2, USBMINUS;1 [7]
+ bld shift, 0 ;1 [8]
+ in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
+ andi x2, USBMASK ;1 [10]
+ breq se0 ;1 [11] SE0 check for bit 1
+ andi shift, 0xf9 ;1 [12]
+didUnstuff0:
+ breq unstuff0 ;1 [13]
+ eor x1, x2 ;1 [14]
+ bst x1, USBMINUS;1 [15]
+ bld shift, 1 ;1 [16]
+rxbit2:
+ in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
+ andi shift, 0xf3 ;1 [18]
+ breq unstuff1 ;1 [19] do remaining work for bit 1
+didUnstuff1:
+ subi cnt, 1 ;1 [20]
+ brcs overflow ;1 [21] loop control
+ eor x2, x1 ;1 [22]
+ bst x2, USBMINUS;1 [23]
+ bld shift, 2 ;1 [24]
+ in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
+ andi shift, 0xe7 ;1 [26]
+ breq unstuff2 ;1 [27]
+didUnstuff2:
+ eor x1, x2 ;1 [28]
+ bst x1, USBMINUS;1 [29]
+ bld shift, 3 ;1 [30]
+didUnstuff3:
+ andi shift, 0xcf ;1 [31]
+ breq unstuff3 ;1 [32]
+ in x1, USBIN ;1 [33] <-- sample bit 4
+ eor x2, x1 ;1 [34]
+ bst x2, USBMINUS;1 [35]
+ bld shift, 4 ;1 [36]
+didUnstuff4:
+ andi shift, 0x9f ;1 [37]
+ breq unstuff4 ;1 [38]
+ nop2 ;2 [40]
+ in x2, USBIN ;1 [41] <-- sample bit 5
+ eor x1, x2 ;1 [42]
+ bst x1, USBMINUS;1 [43]
+ bld shift, 5 ;1 [44]
+didUnstuff5:
+ andi shift, 0x3f ;1 [45]
+ breq unstuff5 ;1 [46]
+ nop2 ;2 [48]
+ in x1, USBIN ;1 [49] <-- sample bit 6
+ eor x2, x1 ;1 [50]
+ bst x2, USBMINUS;1 [51]
+ bld shift, 6 ;1 [52]
+didUnstuff6:
+ cpi shift, 0x02 ;1 [53]
+ brlo unstuff6 ;1 [54]
+ nop2 ;2 [56]
+ in x2, USBIN ;1 [57] <-- sample bit 7
+ eor x1, x2 ;1 [58]
+ bst x1, USBMINUS;1 [59]
+ bld shift, 7 ;1 [60]
+didUnstuff7:
+ cpi shift, 0x04 ;1 [61]
+ brsh rxLoop ;2 [63] loop control
+unstuff7:
+ andi x3, ~0x80 ;1 [63]
+ ori shift, 0x80 ;1 [64]
+ in x2, USBIN ;1 [65] <-- sample stuffed bit 7
+ nop ;1 [66]
+ rjmp didUnstuff7 ;2 [68]
+
+
+;----------------------------------------------------------------------------
+; Processing of received packet (numbers in brackets are cycles after end of SE0)
+;----------------------------------------------------------------------------
+;This is the only non-error exit point for the software receiver loop
+;we don't check any CRCs here because there is no time left.
+#define token x1
+se0: ; [0]
+ subi cnt, USB_BUFSIZE ;1 [1]
+ neg cnt ;1 [2]
+ cpi cnt, 3 ;1 [3]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [4]
+ out USB_INTR_PENDING, x2;1 [5] clear pending intr and check flag later. SE0 should be over.
+ brlo doReturn ;1 [6] this is probably an ACK, NAK or similar packet
+ sub YL, cnt ;1 [7]
+ sbci YH, 0 ;1 [8]
+ ld token, y ;2 [10]
+ cpi token, USBPID_DATA0 ;1 [11]
+ breq handleData ;1 [12]
+ cpi token, USBPID_DATA1 ;1 [13]
+ breq handleData ;1 [14]
+ ldd x2, y+1 ;2 [16] ADDR and 1 bit endpoint number
+ mov x3, x2 ;1 [17] store for endpoint number
+ andi x2, 0x7f ;1 [18] x2 is now ADDR
+ lds shift, usbDeviceAddr;2 [20]
+ cp x2, shift ;1 [21]
+overflow: ; This is a hack: brcs overflow will never have Z flag set
+ brne ignorePacket ;1 [22] packet for different address
+ cpi token, USBPID_IN ;1 [23]
+ breq handleIn ;1 [24]
+ cpi token, USBPID_SETUP ;1 [25]
+ breq handleSetupOrOut ;1 [26]
+ cpi token, USBPID_OUT ;1 [27]
+ breq handleSetupOrOut ;1 [28]
+; rjmp ignorePacket ;fallthrough, should not happen anyway.
+
+ignorePacket:
+ clr shift
+ sts usbCurrentTok, shift
+doReturn:
+ pop cnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+sofError:
+ pop YL
+ out SREG, YL
+ pop YL
+ reti
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
+handleIn3: ;1 [38] (branch taken)
+ lds cnt, usbTxLen3 ;2 [40]
+ sbrc cnt, 4 ;2 [42]
+ rjmp sendCntAndReti ;0 43 + 17 = 60 until SOP
+ sts usbTxLen3, x1 ;2 [44] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf3) ;1 [45]
+ ldi YH, hi8(usbTxBuf3) ;1 [46]
+ rjmp usbSendAndReti ;2 [48] + 13 = 61 until SOP (violates the spec by 1 cycle)
+#endif
+
+;Setup and Out are followed by a data packet two bit times (16 cycles) after
+;the end of SE0. The sync code allows up to 40 cycles delay from the start of
+;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
+handleSetupOrOut: ;1 [29] (branch taken)
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
+ sbrc x3, 7 ;1 [30] skip if endpoint 0
+ ldi token, -1 ;1 [31] indicate that this is endpoint 1 OUT
+#endif
+ sts usbCurrentTok, token;2 [33]
+ pop cnt ;2 [35]
+ pop x3 ;2 [37]
+ pop x2 ;2 [39]
+ pop x1 ;2 [41]
+ pop shift ;2 [43]
+ pop YH ;2 [45]
+ in YL, USB_INTR_PENDING;1 [46]
+ sbrc YL, USB_INTR_PENDING_BIT;1 [47] check whether data is already arriving
+ rjmp waitForJ ;2 [49] save the pops and pushes -- a new interrupt is aready pending
+ rjmp sofError ;2 not an error, but it does the pops and reti we want
+
+
+handleData: ;1 [15] (branch taken)
+ lds token, usbCurrentTok;2 [17]
+ tst token ;1 [18]
+ breq doReturn ;1 [19]
+ lds x2, usbRxLen ;2 [21]
+ tst x2 ;1 [22]
+ brne sendNakAndReti ;1 [23]
+; 2006-03-11: The following two lines fix a problem where the device was not
+; recognized if usbPoll() was called less frequently than once every 4 ms.
+ cpi cnt, 4 ;1 [24] zero sized data packets are status phase only -- ignore and ack
+ brmi sendAckAndReti ;1 [25] keep rx buffer clean -- we must not NAK next SETUP
+ sts usbRxLen, cnt ;2 [27] store received data, swap buffers
+ sts usbRxToken, token ;2 [29]
+ lds x2, usbInputBufOffset;2 [31] swap buffers
+ ldi cnt, USB_BUFSIZE ;1 [32]
+ sub cnt, x2 ;1 [33]
+ sts usbInputBufOffset, cnt;2 [35] buffers now swapped
+ rjmp sendAckAndReti ;2 [37] + 19 = 56 until SOP
+
+handleIn: ;1 [25] (branch taken)
+;We don't send any data as long as the C code has not processed the current
+;input data and potentially updated the output data. That's more efficient
+;in terms of code size than clearing the tx buffers when a packet is received.
+ lds x1, usbRxLen ;2 [27]
+ cpi x1, 1 ;1 [28] negative values are flow control, 0 means "buffer free"
+ brge sendNakAndReti ;1 [29] unprocessed input packet?
+ ldi x1, USBPID_NAK ;1 [30] prepare value for usbTxLen
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+ sbrc x3, 7 ;2 [33] x3 contains addr + endpoint
+ rjmp handleIn1 ;0
+#endif
+ lds cnt, usbTxLen ;2 [34]
+ sbrc cnt, 4 ;2 [36] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;0 37 + 17 = 54 until SOP
+ sts usbTxLen, x1 ;2 [38] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf) ;1 [39]
+ ldi YH, hi8(usbTxBuf) ;1 [40]
+ rjmp usbSendAndReti ;2 [42] + 14 = 56 until SOP
+
+; Comment about when to set usbTxLen to USBPID_NAK:
+; We should set it back when we receive the ACK from the host. This would
+; be simple to implement: One static variable which stores whether the last
+; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
+; ACK. However, we set it back immediately when we send the package,
+; assuming that no error occurs and the host sends an ACK. We save one byte
+; RAM this way and avoid potential problems with endless retries. The rest of
+; the driver assumes error-free transfers anyway.
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
+handleIn1: ;1 [33] (branch taken)
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
+ ldd x2, y+2 ;2 [35]
+ sbrc x2, 0 ;2 [37]
+ rjmp handleIn3 ;0
+#endif
+ lds cnt, usbTxLen1 ;2 [39]
+ sbrc cnt, 4 ;2 [41] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;0 42 + 17 = 59 until SOP
+ sts usbTxLen1, x1 ;2 [43] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf1) ;1 [44]
+ ldi YH, hi8(usbTxBuf1) ;1 [45]
+ rjmp usbSendAndReti ;2 [47] + 13 = 60 until SOP
+#endif
+
+
+;----------------------------------------------------------------------------
+; Transmitting data
+;----------------------------------------------------------------------------
+
+bitstuff0: ;1 (for branch taken)
+ eor x1, x4 ;1
+ ldi x2, 0 ;1
+ out USBOUT, x1 ;1 <-- out
+ rjmp didStuff0 ;2 branch back 2 cycles earlier
+bitstuff1: ;1 (for branch taken)
+ eor x1, x4 ;1
+ rjmp didStuff1 ;2 we know that C is clear, jump back to do OUT and ror 0 into x2
+bitstuff2: ;1 (for branch taken)
+ eor x1, x4 ;1
+ rjmp didStuff2 ;2 jump back 4 cycles earlier and do out and ror 0 into x2
+bitstuff3: ;1 (for branch taken)
+ eor x1, x4 ;1
+ rjmp didStuff3 ;2 jump back earlier and ror 0 into x2
+bitstuff4: ;1 (for branch taken)
+ eor x1, x4 ;1
+ ldi x2, 0 ;1
+ out USBOUT, x1 ;1 <-- out
+ rjmp didStuff4 ;2 jump back 2 cycles earlier
+
+sendNakAndReti: ;0 [-19] 19 cycles until SOP
+ ldi x3, USBPID_NAK ;1 [-18]
+ rjmp usbSendX3 ;2 [-16]
+sendAckAndReti: ;0 [-19] 19 cycles until SOP
+ ldi x3, USBPID_ACK ;1 [-18]
+ rjmp usbSendX3 ;2 [-16]
+sendCntAndReti: ;0 [-17] 17 cycles until SOP
+ mov x3, cnt ;1 [-16]
+usbSendX3: ;0 [-16]
+ ldi YL, 20 ;1 [-15] 'x3' is R20
+ ldi YH, 0 ;1 [-14]
+ ldi cnt, 2 ;1 [-13]
+; rjmp usbSendAndReti fallthrough
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
+; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
+; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte
+;uses: x1...x4, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+usbSendAndReti: ;0 [-13] timing: 13 cycles until SOP
+ in x2, USBDDR ;1 [-12]
+ ori x2, USBMASK ;1 [-11]
+ sbi USBOUT, USBMINUS;2 [-9] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;1 [-8] port mirror for tx loop
+ out USBDDR, x2 ;1 [-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ push x4 ;2 [-5]
+ ldi x4, USBMASK ;1 [-4] exor mask
+ ldi shift, 0x80 ;1 [-3] sync byte is first byte sent
+txLoop: ; [62]
+ sbrs shift, 0 ;1 [-2] [62]
+ eor x1, x4 ;1 [-1] [63]
+ out USBOUT, x1 ;1 [0] <-- out bit 0
+ ror shift ;1 [1]
+ ror x2 ;1 [2]
+didStuff0:
+ cpi x2, 0xfc ;1 [3]
+ brsh bitstuff0 ;1 [4]
+ sbrs shift, 0 ;1 [5]
+ eor x1, x4 ;1 [6]
+ ror shift ;1 [7]
+didStuff1:
+ out USBOUT, x1 ;1 [8] <-- out bit 1
+ ror x2 ;1 [9]
+ cpi x2, 0xfc ;1 [10]
+ brsh bitstuff1 ;1 [11]
+ sbrs shift, 0 ;1 [12]
+ eor x1, x4 ;1 [13]
+ ror shift ;1 [14]
+didStuff2:
+ ror x2 ;1 [15]
+ out USBOUT, x1 ;1 [16] <-- out bit 2
+ cpi x2, 0xfc ;1 [17]
+ brsh bitstuff2 ;1 [18]
+ sbrs shift, 0 ;1 [19]
+ eor x1, x4 ;1 [20]
+ ror shift ;1 [21]
+didStuff3:
+ ror x2 ;1 [22]
+ cpi x2, 0xfc ;1 [23]
+ out USBOUT, x1 ;1 [24] <-- out bit 3
+ brsh bitstuff3 ;1 [25]
+ nop2 ;2 [27]
+ ld x3, y+ ;2 [29]
+ sbrs shift, 0 ;1 [30]
+ eor x1, x4 ;1 [31]
+ out USBOUT, x1 ;1 [32] <-- out bit 4
+ ror shift ;1 [33]
+ ror x2 ;1 [34]
+didStuff4:
+ cpi x2, 0xfc ;1 [35]
+ brsh bitstuff4 ;1 [36]
+ sbrs shift, 0 ;1 [37]
+ eor x1, x4 ;1 [38]
+ ror shift ;1 [39]
+didStuff5:
+ out USBOUT, x1 ;1 [40] <-- out bit 5
+ ror x2 ;1 [41]
+ cpi x2, 0xfc ;1 [42]
+ brsh bitstuff5 ;1 [43]
+ sbrs shift, 0 ;1 [44]
+ eor x1, x4 ;1 [45]
+ ror shift ;1 [46]
+didStuff6:
+ ror x2 ;1 [47]
+ out USBOUT, x1 ;1 [48] <-- out bit 6
+ cpi x2, 0xfc ;1 [49]
+ brsh bitstuff6 ;1 [50]
+ sbrs shift, 0 ;1 [51]
+ eor x1, x4 ;1 [52]
+ ror shift ;1 [53]
+didStuff7:
+ ror x2 ;1 [54]
+ cpi x2, 0xfc ;1 [55]
+ out USBOUT, x1 ;1 [56] <-- out bit 7
+ brsh bitstuff7 ;1 [57]
+ mov shift, x3 ;1 [58]
+ dec cnt ;1 [59]
+ brne txLoop ;1/2 [60/61]
+;make SE0:
+ cbr x1, USBMASK ;1 [61] prepare SE0 [spec says EOP may be 15 to 18 cycles]
+ pop x4 ;2 [63]
+;brackets are cycles from start of SE0 now
+ out USBOUT, x1 ;1 [0] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
+ nop2 ;2 [2]
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ lds x2, usbNewDeviceAddr;2 [4]
+ subi YL, 20 + 2 ;1 [5]
+ sbci YH, 0 ;1 [6]
+ breq skipAddrAssign ;2 [8]
+ sts usbDeviceAddr, x2;0 if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;1 [9] int0 occurred during TX -- clear pending flag
+ out USB_INTR_PENDING, x2;1 [10]
+ ori x1, USBIDLE ;1 [11]
+ in x2, USBDDR ;1 [12]
+ cbr x2, USBMASK ;1 [13] set both pins to input
+ mov x3, x1 ;1 [14]
+ cbr x3, USBMASK ;1 [15] configure no pullup on both pins
+ out USBOUT, x1 ;1 [16] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;1 [17] <-- release bus now
+ out USBOUT, x3 ;1 [18] <-- ensure no pull-up resistors are active
+ rjmp doReturn
+
+bitstuff5: ;1 (for branch taken)
+ eor x1, x4 ;1
+ rjmp didStuff5 ;2 same trick as above...
+bitstuff6: ;1 (for branch taken)
+ eor x1, x4 ;1
+ rjmp didStuff6 ;2 same trick as above...
+bitstuff7: ;1 (for branch taken)
+ eor x1, x4 ;1
+ rjmp didStuff7 ;2 same trick as above...
--- /dev/null
+/* Name: usbdrvasm16.S
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-06-15
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * Revision: $Id$
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 16 MHz version of the asssembler part of the USB driver. It
+requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+SIG_INTERRUPT0:
+;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
+ push YL ;[-25] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-23]
+ push YL ;[-22]
+ push YH ;[-20]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
+waitForJ:
+ sbis USBIN, USBMINUS ;[-18] wait for D- == 1
+ rjmp waitForJ
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-15]
+ rjmp foundK ;[-14]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ rjmp sofError
+foundK: ;[-12]
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push bitcnt ;[-12]
+; [---] ;[-11]
+ lds YL, usbInputBufOffset;[-10]
+; [---] ;[-9]
+ clr YH ;[-8]
+ subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
+ push shift ;[-5]
+; [---] ;[-4]
+ ldi bitcnt, 0x55 ;[-3] [rx loop init]
+ sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
+ rjmp haveTwoBitsK ;[-1]
+ pop shift ;[0] undo the push from before
+ pop bitcnt ;[2] undo the push from before
+ rjmp waitForK ;[4] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 21 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK:
+ push x1 ;[1]
+ push x2 ;[3]
+ push x3 ;[5]
+ ldi shift, 0 ;[7]
+ ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
+ push x4 ;[9] == leap
+
+ in x1, USBIN ;[11] <-- sample bit 0
+ andi x1, USBMASK ;[12]
+ bst x1, USBMINUS ;[13]
+ bld shift, 7 ;[14]
+ push cnt ;[15]
+ ldi leap, 0 ;[17] [rx loop init]
+ ldi cnt, USB_BUFSIZE;[18] [rx loop init]
+ rjmp rxbit1 ;[19] arrives at [21]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+
+unstuff6:
+ andi x2, USBMASK ;[03]
+ ori x3, 1<<6 ;[04] will not be shifted any more
+ andi shift, ~0x80;[05]
+ mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
+ subi leap, 3 ;[07] since this is a short (10 cycle) bit, enforce leap bit
+ rjmp didUnstuff6 ;[08]
+
+unstuff7:
+ ori x3, 1<<7 ;[09] will not be shifted any more
+ in x2, USBIN ;[00] [10] re-sample bit 7
+ andi x2, USBMASK ;[01]
+ andi shift, ~0x80;[02]
+ subi leap, 3 ;[03] since this is a short (10 cycle) bit, enforce leap bit
+ rjmp didUnstuff7 ;[04]
+
+unstuffEven:
+ ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
+ in x1, USBIN ;[00] [10]
+ andi shift, ~0x80;[01]
+ andi x1, USBMASK ;[02]
+ breq se0 ;[03]
+ subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
+ nop ;[05]
+ rjmp didUnstuffE ;[06]
+
+unstuffOdd:
+ ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
+ in x2, USBIN ;[00] [10]
+ andi shift, ~0x80;[01]
+ andi x2, USBMASK ;[02]
+ breq se0 ;[03]
+ subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
+ nop ;[05]
+ rjmp didUnstuffO ;[06]
+
+rxByteLoop:
+ andi x1, USBMASK ;[03]
+ eor x2, x1 ;[04]
+ subi leap, 1 ;[05]
+ brpl skipLeap ;[06]
+ subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
+ nop ;1
+skipLeap:
+ subi x2, 1 ;[08]
+ ror shift ;[09]
+didUnstuff6:
+ cpi shift, 0xfc ;[10]
+ in x2, USBIN ;[00] [11] <-- sample bit 7
+ brcc unstuff6 ;[01]
+ andi x2, USBMASK ;[02]
+ eor x1, x2 ;[03]
+ subi x1, 1 ;[04]
+ ror shift ;[05]
+didUnstuff7:
+ cpi shift, 0xfc ;[06]
+ brcc unstuff7 ;[07]
+ eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
+ st y+, x3 ;[09] store data
+rxBitLoop:
+ in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
+ andi x1, USBMASK ;[01]
+ eor x2, x1 ;[02]
+ andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
+ subi x2, 1 ;[04]
+ ror shift ;[05]
+ cpi shift, 0xfc ;[06]
+ brcc unstuffEven ;[07]
+didUnstuffE:
+ lsr x3 ;[08]
+ lsr x3 ;[09]
+rxbit1:
+ in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
+ andi x2, USBMASK ;[01]
+ breq se0 ;[02]
+ eor x1, x2 ;[03]
+ subi x1, 1 ;[04]
+ ror shift ;[05]
+ cpi shift, 0xfc ;[06]
+ brcc unstuffOdd ;[07]
+didUnstuffO:
+ subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
+ brcs rxBitLoop ;[09]
+
+ subi cnt, 1 ;[10]
+ in x1, USBIN ;[00] [11] <-- sample bit 6
+ brcc rxByteLoop ;[01]
+ rjmp ignorePacket; overflow
+
+;----------------------------------------------------------------------------
+; Processing of received packet (numbers in brackets are cycles after center of SE0)
+;----------------------------------------------------------------------------
+;This is the only non-error exit point for the software receiver loop
+;we don't check any CRCs here because there is no time left.
+#define token x1
+se0:
+ subi cnt, USB_BUFSIZE ;[5]
+ neg cnt ;[6]
+ cpi cnt, 3 ;[7]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
+ out USB_INTR_PENDING, x2;[9] clear pending intr and check flag later. SE0 should be over.
+ brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
+ sub YL, cnt ;[11]
+ sbci YH, 0 ;[12]
+ ld token, y ;[13]
+ cpi token, USBPID_DATA0 ;[15]
+ breq handleData ;[16]
+ cpi token, USBPID_DATA1 ;[17]
+ breq handleData ;[18]
+ ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
+ mov x3, x2 ;[21] store for endpoint number
+ andi x2, 0x7f ;[22] x2 is now ADDR
+ lds shift, usbDeviceAddr;[23]
+ cp x2, shift ;[25]
+overflow: ; This is a hack: brcs overflow will never have Z flag set
+ brne ignorePacket ;[26] packet for different address
+ cpi token, USBPID_IN ;[27]
+ breq handleIn ;[28]
+ cpi token, USBPID_SETUP ;[29]
+ breq handleSetupOrOut ;[30]
+ cpi token, USBPID_OUT ;[31]
+ breq handleSetupOrOut ;[32]
+; rjmp ignorePacket ;fallthrough, should not happen anyway.
+
+ignorePacket:
+ clr shift
+ sts usbCurrentTok, shift
+doReturn:
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop bitcnt
+sofError:
+ pop YH
+ pop YL
+ out SREG, YL
+ pop YL
+ reti
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
+handleIn3:
+ lds cnt, usbTxLen3 ;[43]
+ sbrc cnt, 4 ;[45]
+ rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
+ sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf3) ;[49]
+ ldi YH, hi8(usbTxBuf3) ;[50]
+ rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
+#endif
+
+;Setup and Out are followed by a data packet two bit times (16 cycles) after
+;the end of SE0. The sync code allows up to 40 cycles delay from the start of
+;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
+handleSetupOrOut: ;[34]
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
+ sbrc x3, 7 ;[34] skip if endpoint 0
+ ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
+#endif
+ sts usbCurrentTok, token;[36]
+ pop cnt ;[38]
+ pop x4 ;[40]
+ pop x3 ;[42]
+ pop x2 ;[44]
+ pop x1 ;[46]
+ pop shift ;[48]
+ pop bitcnt ;[50]
+ in YL, USB_INTR_PENDING;[52]
+ sbrc YL, USB_INTR_PENDING_BIT;[53] check whether data is already arriving
+ rjmp waitForJ ;[54] save the pops and pushes -- a new interrupt is aready pending
+ rjmp sofError ;[55] not an error, but it does the pops and reti we want
+
+
+handleData:
+ lds token, usbCurrentTok;[20]
+ tst token ;[22]
+ breq doReturn ;[23]
+ lds x2, usbRxLen ;[24]
+ tst x2 ;[26]
+ brne sendNakAndReti ;[27]
+; 2006-03-11: The following two lines fix a problem where the device was not
+; recognized if usbPoll() was called less frequently than once every 4 ms.
+ cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
+ brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
+ sts usbRxLen, cnt ;[30] store received data, swap buffers
+ sts usbRxToken, token ;[32]
+ lds x2, usbInputBufOffset;[34] swap buffers
+ ldi cnt, USB_BUFSIZE ;[36]
+ sub cnt, x2 ;[37]
+ sts usbInputBufOffset, cnt;[38] buffers now swapped
+ rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
+
+handleIn:
+;We don't send any data as long as the C code has not processed the current
+;input data and potentially updated the output data. That's more efficient
+;in terms of code size than clearing the tx buffers when a packet is received.
+ lds x1, usbRxLen ;[30]
+ cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
+ brge sendNakAndReti ;[33] unprocessed input packet?
+ ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+ sbrc x3, 7 ;[35] x3 contains addr + endpoint
+ rjmp handleIn1 ;[36]
+#endif
+ lds cnt, usbTxLen ;[37]
+ sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
+ sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf) ;[43]
+ ldi YH, hi8(usbTxBuf) ;[44]
+ rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
+
+; Comment about when to set usbTxLen to USBPID_NAK:
+; We should set it back when we receive the ACK from the host. This would
+; be simple to implement: One static variable which stores whether the last
+; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
+; ACK. However, we set it back immediately when we send the package,
+; assuming that no error occurs and the host sends an ACK. We save one byte
+; RAM this way and avoid potential problems with endless retries. The rest of
+; the driver assumes error-free transfers anyway.
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
+handleIn1: ;[38]
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
+ ldd x2, y+2 ;[38]
+ sbrc x2, 0 ;[40]
+ rjmp handleIn3 ;[41]
+#endif
+ lds cnt, usbTxLen1 ;[42]
+ sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
+ sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf1) ;[48]
+ ldi YH, hi8(usbTxBuf1) ;[49]
+ rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
+#endif
+
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+
+bitstuffN:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6]
+ nop2 ;[7]
+ nop ;[9]
+ out USBOUT, x1 ;[10] <-- out
+ rjmp didStuffN ;[0]
+
+bitstuff6:
+ eor x1, x4 ;[4]
+ ldi x2, 0 ;[5]
+ nop2 ;[6] C is zero (brcc)
+ rjmp didStuff6 ;[8]
+
+bitstuff7:
+ eor x1, x4 ;[3]
+ ldi x2, 0 ;[4]
+ rjmp didStuff7 ;[5]
+
+
+sendNakAndReti:
+ ldi x3, USBPID_NAK ;[-18]
+ rjmp sendX3AndReti ;[-17]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov x3, cnt ;[-16]
+sendX3AndReti:
+ ldi YL, 20 ;[-15] x3==r20 address is 20
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We don't match the transfer rate exactly (don't insert leap cycles every third
+;byte) because the spec demands only 1.5% precision anyway.
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+txByteLoop:
+ ldi bitcnt, 0x2a ;[-4] [6] binary 00101010
+txBitLoop:
+ sbrs shift, 0 ;[-3] [7]
+ eor x1, x4 ;[-2] [8]
+ out USBOUT, x1 ;[-1] [9] <-- out N
+ ror shift ;[0] [10]
+ ror x2 ;[1]
+didStuffN:
+ cpi x2, 0xfc ;[2]
+ brcc bitstuffN ;[3]
+ lsr bitcnt ;[4]
+ brcc txBitLoop ;[5]
+ brne txBitLoop ;[6]
+
+ sbrs shift, 0 ;[7]
+ eor x1, x4 ;[8]
+ ror shift ;[9]
+didStuff6:
+ out USBOUT, x1 ;[-1] [10] <-- out 6
+ ror x2 ;[0] [11]
+ cpi x2, 0xfc ;[1]
+ brcc bitstuff6 ;[2]
+ sbrs shift, 0 ;[3]
+ eor x1, x4 ;[4]
+ ror shift ;[5]
+ ror x2 ;[6]
+didStuff7:
+ nop ;[7]
+ nop2 ;[8]
+ out USBOUT, x1 ;[-1][10] <-- out 7
+ cpi x2, 0xfc ;[0] [11]
+ brcc bitstuff7 ;[1]
+ ld shift, y+ ;[2]
+ dec cnt ;[4]
+ brne txByteLoop ;[4]
+;make SE0:
+ cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
+ lds x2, usbNewDeviceAddr;[8]
+ out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ subi YL, 2 ;[0]
+ sbci YH, 0 ;[1]
+ breq skipAddrAssign ;[2]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
+ out USB_INTR_PENDING, x2;[5]
+ ori x1, USBIDLE ;[6]
+ in x2, USBDDR ;[7]
+ cbr x2, USBMASK ;[8] set both pins to input
+ mov x3, x1 ;[9]
+ cbr x3, USBMASK ;[10] configure no pullup on both pins
+ ldi x4, 4 ;[11]
+se0Delay:
+ dec x4 ;[12] [15] [18] [21]
+ brne se0Delay ;[13] [16] [19] [22]
+ out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[24] <-- release bus now
+ out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm165.S
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-04-22
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * Revision: $Id$
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 16.5 MHz version of the USB driver. It is intended for the
+ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
+This version contains a phase locked loop in the receiver routine to cope with
+slight clock rate deviations of up to +/- 1%.
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
+;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
+;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
+;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 16.5 MHz -> 11 cycles per bit
+; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+
+SIG_INTERRUPT0:
+;order of registers pushed: r0, SREG [sofError], YL, YH, shift, x1, x2, x3, x4, cnt
+ push r0 ;[-23] push only what is necessary to sync with edge ASAP
+ in r0, SREG ;[-21]
+ push r0 ;[-20]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
+waitForJ:
+ sbis USBIN, USBMINUS ;[-18] wait for D- == 1
+ rjmp waitForJ
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-15]
+ rjmp foundK ;[-14]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ rjmp sofError
+foundK: ;[-12]
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push YL ;[-12]
+; [---] ;[-11]
+ push YH ;[-10]
+; [---] ;[-9]
+ lds YL, usbInputBufOffset;[-8]
+; [---] ;[-7]
+ clr YH ;[-6]
+ subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
+ mov r0, x2 ;[-3] [rx loop init]
+ sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
+ rjmp haveTwoBitsK ;[-1]
+ pop YH ;[0] undo the pushes from before
+ pop YL ;[2]
+ rjmp waitForK ;[4] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 22 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK: ;[1]
+ push shift ;[1]
+ push x1 ;[3]
+ push x2 ;[5]
+ push x3 ;[7]
+ ldi shift, 0xff ;[9] [rx loop init]
+ ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
+
+ in x1, USBIN ;[11] <-- sample bit 0
+ bst x1, USBMINUS ;[12]
+ bld shift, 0 ;[13]
+ push x4 ;[14] == phase
+; [---] ;[15]
+ push cnt ;[16]
+; [---] ;[17]
+ ldi phase, 0 ;[18] [rx loop init]
+ ldi cnt, USB_BUFSIZE;[19] [rx loop init]
+ rjmp rxbit1 ;[20]
+; [---] ;[21]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+/*
+byte oriented operations done during loop:
+bit 0: store data
+bit 1: SE0 check
+bit 2: overflow check
+bit 3: catch up
+bit 4: rjmp to achieve conditional jump range
+bit 5: PLL
+bit 6: catch up
+bit 7: jump, fixup bitstuff
+; 87 [+ 2] cycles
+------------------------------------------------------------------
+*/
+continueWithBit5:
+ in x2, USBIN ;[055] <-- bit 5
+ eor r0, x2 ;[056]
+ or phase, r0 ;[057]
+ sbrc phase, USBMINUS ;[058]
+ lpm ;[059] optional nop3; modifies r0
+ in phase, USBIN ;[060] <-- phase
+ eor x1, x2 ;[061]
+ bst x1, USBMINUS ;[062]
+ bld shift, 5 ;[063]
+ andi shift, 0x3f ;[064]
+ in x1, USBIN ;[065] <-- bit 6
+ breq unstuff5 ;[066] *** unstuff escape
+ eor phase, x1 ;[067]
+ eor x2, x1 ;[068]
+ bst x2, USBMINUS ;[069]
+ bld shift, 6 ;[070]
+didUnstuff6: ;[ ]
+ in r0, USBIN ;[071] <-- phase
+ cpi shift, 0x02 ;[072]
+ brlo unstuff6 ;[073] *** unstuff escape
+didUnstuff5: ;[ ]
+ nop2 ;[074]
+; [---] ;[075]
+ in x2, USBIN ;[076] <-- bit 7
+ eor x1, x2 ;[077]
+ bst x1, USBMINUS ;[078]
+ bld shift, 7 ;[079]
+didUnstuff7: ;[ ]
+ eor r0, x2 ;[080]
+ or phase, r0 ;[081]
+ in r0, USBIN ;[082] <-- phase
+ cpi shift, 0x04 ;[083]
+ brsh rxLoop ;[084]
+; [---] ;[085]
+unstuff7: ;[ ]
+ andi x3, ~0x80 ;[085]
+ ori shift, 0x80 ;[086]
+ in x2, USBIN ;[087] <-- sample stuffed bit 7
+ nop ;[088]
+ rjmp didUnstuff7 ;[089]
+; [---] ;[090]
+ ;[080]
+
+unstuff5: ;[067]
+ eor phase, x1 ;[068]
+ andi x3, ~0x20 ;[069]
+ ori shift, 0x20 ;[070]
+ in r0, USBIN ;[071] <-- phase
+ mov x2, x1 ;[072]
+ nop ;[073]
+ nop2 ;[074]
+; [---] ;[075]
+ in x1, USBIN ;[076] <-- bit 6
+ eor r0, x1 ;[077]
+ or phase, r0 ;[078]
+ eor x2, x1 ;[079]
+ bst x2, USBMINUS ;[080]
+ bld shift, 6 ;[081] no need to check bitstuffing, we just had one
+ in r0, USBIN ;[082] <-- phase
+ rjmp didUnstuff5 ;[083]
+; [---] ;[084]
+ ;[074]
+
+unstuff6: ;[074]
+ andi x3, ~0x40 ;[075]
+ in x1, USBIN ;[076] <-- bit 6 again
+ ori shift, 0x40 ;[077]
+ nop2 ;[078]
+; [---] ;[079]
+ rjmp didUnstuff6 ;[080]
+; [---] ;[081]
+ ;[071]
+
+unstuff0: ;[013]
+ eor r0, x2 ;[014]
+ or phase, r0 ;[015]
+ andi x2, USBMASK ;[016] check for SE0
+ in r0, USBIN ;[017] <-- phase
+ breq didUnstuff0 ;[018] direct jump to se0 would be too long
+ andi x3, ~0x01 ;[019]
+ ori shift, 0x01 ;[020]
+ mov x1, x2 ;[021] mov existing sample
+ in x2, USBIN ;[022] <-- bit 1 again
+ rjmp didUnstuff0 ;[023]
+; [---] ;[024]
+ ;[014]
+
+unstuff1: ;[024]
+ eor r0, x1 ;[025]
+ or phase, r0 ;[026]
+ andi x3, ~0x02 ;[027]
+ in r0, USBIN ;[028] <-- phase
+ ori shift, 0x02 ;[029]
+ mov x2, x1 ;[030]
+ rjmp didUnstuff1 ;[031]
+; [---] ;[032]
+ ;[022]
+
+unstuff2: ;[035]
+ eor r0, x2 ;[036]
+ or phase, r0 ;[037]
+ andi x3, ~0x04 ;[038]
+ in r0, USBIN ;[039] <-- phase
+ ori shift, 0x04 ;[040]
+ mov x1, x2 ;[041]
+ rjmp didUnstuff2 ;[042]
+; [---] ;[043]
+ ;[033]
+
+unstuff3: ;[043]
+ in x2, USBIN ;[044] <-- bit 3 again
+ eor r0, x2 ;[045]
+ or phase, r0 ;[046]
+ andi x3, ~0x08 ;[047]
+ ori shift, 0x08 ;[048]
+ nop ;[049]
+ in r0, USBIN ;[050] <-- phase
+ rjmp didUnstuff3 ;[051]
+; [---] ;[052]
+ ;[042]
+
+unstuff4: ;[053]
+ andi x3, ~0x10 ;[054]
+ in x1, USBIN ;[055] <-- bit 4 again
+ ori shift, 0x10 ;[056]
+ rjmp didUnstuff4 ;[057]
+; [---] ;[058]
+ ;[048]
+
+rxLoop: ;[085]
+ eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ in x1, USBIN ;[000] <-- bit 0
+ st y+, x3 ;[001]
+; [---] ;[002]
+ eor r0, x1 ;[003]
+ or phase, r0 ;[004]
+ eor x2, x1 ;[005]
+ in r0, USBIN ;[006] <-- phase
+ ser x3 ;[007]
+ bst x2, USBMINUS ;[008]
+ bld shift, 0 ;[009]
+ andi shift, 0xf9 ;[010]
+rxbit1: ;[ ]
+ in x2, USBIN ;[011] <-- bit 1
+ breq unstuff0 ;[012] *** unstuff escape
+ andi x2, USBMASK ;[013] SE0 check for bit 1
+didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
+ breq se0 ;[014]
+ eor r0, x2 ;[015]
+ or phase, r0 ;[016]
+ in r0, USBIN ;[017] <-- phase
+ eor x1, x2 ;[018]
+ bst x1, USBMINUS ;[019]
+ bld shift, 1 ;[020]
+ andi shift, 0xf3 ;[021]
+didUnstuff1: ;[ ]
+ in x1, USBIN ;[022] <-- bit 2
+ breq unstuff1 ;[023] *** unstuff escape
+ eor r0, x1 ;[024]
+ or phase, r0 ;[025]
+ subi cnt, 1 ;[026] overflow check
+ brcs overflow ;[027]
+ in r0, USBIN ;[028] <-- phase
+ eor x2, x1 ;[029]
+ bst x2, USBMINUS ;[030]
+ bld shift, 2 ;[031]
+ andi shift, 0xe7 ;[032]
+didUnstuff2: ;[ ]
+ in x2, USBIN ;[033] <-- bit 3
+ breq unstuff2 ;[034] *** unstuff escape
+ eor r0, x2 ;[035]
+ or phase, r0 ;[036]
+ eor x1, x2 ;[037]
+ bst x1, USBMINUS ;[038]
+ in r0, USBIN ;[039] <-- phase
+ bld shift, 3 ;[040]
+ andi shift, 0xcf ;[041]
+didUnstuff3: ;[ ]
+ breq unstuff3 ;[042] *** unstuff escape
+ nop ;[043]
+ in x1, USBIN ;[044] <-- bit 4
+ eor x2, x1 ;[045]
+ bst x2, USBMINUS ;[046]
+ bld shift, 4 ;[047]
+didUnstuff4: ;[ ]
+ eor r0, x1 ;[048]
+ or phase, r0 ;[049]
+ in r0, USBIN ;[050] <-- phase
+ andi shift, 0x9f ;[051]
+ breq unstuff4 ;[052] *** unstuff escape
+ rjmp continueWithBit5;[053]
+; [---] ;[054]
+
+;----------------------------------------------------------------------------
+; Processing of received packet (numbers in brackets are cycles after center of SE0)
+;----------------------------------------------------------------------------
+;This is the only non-error exit point for the software receiver loop
+;we don't check any CRCs here because there is no time left.
+#define token x1
+se0:
+ subi cnt, USB_BUFSIZE ;[5]
+ neg cnt ;[6]
+ cpi cnt, 3 ;[7]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
+ out USB_INTR_PENDING, x2;[9] clear pending intr and check flag later. SE0 should be over.
+ brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
+ sub YL, cnt ;[11]
+ sbci YH, 0 ;[12]
+ ld token, y ;[13]
+ cpi token, USBPID_DATA0 ;[15]
+ breq handleData ;[16]
+ cpi token, USBPID_DATA1 ;[17]
+ breq handleData ;[18]
+ ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
+ mov x3, x2 ;[21] store for endpoint number
+ andi x2, 0x7f ;[22] x2 is now ADDR
+ lds shift, usbDeviceAddr;[23]
+ cp x2, shift ;[25]
+overflow: ; This is a hack: brcs overflow will never have Z flag set
+ brne ignorePacket ;[26] packet for different address
+ cpi token, USBPID_IN ;[27]
+ breq handleIn ;[28]
+ cpi token, USBPID_SETUP ;[29]
+ breq handleSetupOrOut ;[30]
+ cpi token, USBPID_OUT ;[31]
+ breq handleSetupOrOut ;[32]
+; rjmp ignorePacket ;fallthrough, should not happen anyway.
+
+ignorePacket:
+ clr shift
+ sts usbCurrentTok, shift
+doReturn:
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ pop YL
+sofError:
+ pop r0
+ out SREG, r0
+ pop r0
+ reti
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
+handleIn3:
+ lds cnt, usbTxLen3 ;[43]
+ sbrc cnt, 4 ;[45]
+ rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
+ sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf3) ;[49]
+ ldi YH, hi8(usbTxBuf3) ;[50]
+ rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
+#endif
+
+;Setup and Out are followed by a data packet two bit times (16 cycles) after
+;the end of SE0. The sync code allows up to 40 cycles delay from the start of
+;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
+handleSetupOrOut: ;[34]
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
+ sbrc x3, 7 ;[34] skip if endpoint 0
+ ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
+#endif
+ sts usbCurrentTok, token;[36]
+ pop cnt ;[38]
+ pop x4 ;[40]
+ pop x3 ;[42]
+ pop x2 ;[44]
+ pop x1 ;[46]
+ pop shift ;[48]
+ pop YH ;[50]
+ pop YL ;[52]
+ in r0, USB_INTR_PENDING;[54]
+ sbrc r0, USB_INTR_PENDING_BIT;[55] check whether data is already arriving
+ rjmp waitForJ ;[56] save the pops and pushes -- a new interrupt is aready pending
+ rjmp sofError ;[57] not an error, but it does the pops and reti we want
+
+
+handleData:
+ lds token, usbCurrentTok;[20]
+ tst token ;[22]
+ breq doReturn ;[23]
+ lds x2, usbRxLen ;[24]
+ tst x2 ;[26]
+ brne sendNakAndReti ;[27]
+; 2006-03-11: The following two lines fix a problem where the device was not
+; recognized if usbPoll() was called less frequently than once every 4 ms.
+ cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
+ brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
+ sts usbRxLen, cnt ;[30] store received data, swap buffers
+ sts usbRxToken, token ;[32]
+ lds x2, usbInputBufOffset;[34] swap buffers
+ ldi cnt, USB_BUFSIZE ;[36]
+ sub cnt, x2 ;[37]
+ sts usbInputBufOffset, cnt;[38] buffers now swapped
+ rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
+
+handleIn:
+;We don't send any data as long as the C code has not processed the current
+;input data and potentially updated the output data. That's more efficient
+;in terms of code size than clearing the tx buffers when a packet is received.
+ lds x1, usbRxLen ;[30]
+ cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
+ brge sendNakAndReti ;[33] unprocessed input packet?
+ ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+ sbrc x3, 7 ;[35] x3 contains addr + endpoint
+ rjmp handleIn1 ;[36]
+#endif
+ lds cnt, usbTxLen ;[37]
+ sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
+ sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf) ;[43]
+ ldi YH, hi8(usbTxBuf) ;[44]
+ rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
+
+; Comment about when to set usbTxLen to USBPID_NAK:
+; We should set it back when we receive the ACK from the host. This would
+; be simple to implement: One static variable which stores whether the last
+; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
+; ACK. However, we set it back immediately when we send the package,
+; assuming that no error occurs and the host sends an ACK. We save one byte
+; RAM this way and avoid potential problems with endless retries. The rest of
+; the driver assumes error-free transfers anyway.
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
+handleIn1: ;[38]
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
+ ldd x2, y+2 ;[38]
+ sbrc x2, 0 ;[40]
+ rjmp handleIn3 ;[41]
+#endif
+ lds cnt, usbTxLen1 ;[42]
+ sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
+ sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf1) ;[48]
+ ldi YH, hi8(usbTxBuf1) ;[49]
+ rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
+#endif
+
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+
+bitstuff7:
+ eor x1, x4 ;[4]
+ ldi x2, 0 ;[5]
+ nop2 ;[6] C is zero (brcc)
+ rjmp didStuff7 ;[8]
+
+bitstuffN:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6]
+ lpm ;[7] 3 cycle NOP, modifies r0
+ out USBOUT, x1 ;[10] <-- out
+ rjmp didStuffN ;[0]
+
+#define bitStatus x3
+
+sendNakAndReti:
+ ldi cnt, USBPID_NAK ;[-19]
+ rjmp sendCntAndReti ;[-18]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov r0, cnt ;[-16]
+ ldi YL, 0 ;[-15] R0 address is 0
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+ ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
+byteloop:
+bitloop:
+ sbrs shift, 0 ;[8] [-3]
+ eor x1, x4 ;[9] [-2]
+ out USBOUT, x1 ;[10] [-1] <-- out
+ ror shift ;[0]
+ ror x2 ;[1]
+didStuffN:
+ cpi x2, 0xfc ;[2]
+ brcc bitstuffN ;[3]
+ nop ;[4]
+ subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
+ brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
+ sbrs shift, 0 ;[7]
+ eor x1, x4 ;[8]
+ ror shift ;[9]
+didStuff7:
+ out USBOUT, x1 ;[10] <-- out
+ ror x2 ;[0]
+ cpi x2, 0xfc ;[1]
+ brcc bitstuff7 ;[2]
+ ld shift, y+ ;[3]
+ dec cnt ;[5]
+ brne byteloop ;[6]
+;make SE0:
+ cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
+ lds x2, usbNewDeviceAddr;[8]
+ out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ subi YL, 2 ;[0]
+ sbci YH, 0 ;[1]
+ breq skipAddrAssign ;[2]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
+ out USB_INTR_PENDING, x2;[5]
+ ori x1, USBIDLE ;[6]
+ in x2, USBDDR ;[7]
+ cbr x2, USBMASK ;[8] set both pins to input
+ mov x3, x1 ;[9]
+ cbr x3, USBMASK ;[10] configure no pullup on both pins
+ ldi x4, 4 ;[11]
+se0Delay:
+ dec x4 ;[12] [15] [18] [21]
+ brne se0Delay ;[13] [16] [19] [22]
+ out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[24] <-- release bus now
+ out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
+ rjmp doReturn
projects / pub / USBasp.git / commitdiff