# Declare files that will always have CRLF line endings on checkout.
-*.inf text eol=crlf
+*.inf text eol=crlf
+*.cat text eol=crlf
# Declare pacth and diff files allow trailing whitespace
*.diff text=auto -whitespace
-usbasp.2007-10-23
------------------
+usbasp.2009-02-28 (v1.3)
+------------------------
+- added support for software control of ISP speed (based on patch by Jurgis Brigmanis)
+- included new AVRUSB driver version (Release 2008-11-26)
+- added libusb 0.1.12.1 windows drivers (needed for WinAVR version 20080512 or greater)
+
+usbasp.2007-10-23 (v1.2)
+------------------------
- red LED turns on before connecting to target device: this signal can be used to control external tri-state buffers (by Pawel Szramowski)
usbasp.2007-07-23
libusb-win32 .................... http://libusb-win32.sourceforge.net/
-2007-07-23 Thomas Fischl <tfischl@gmx.de>
+2009-02-28 Thomas Fischl <tfischl@gmx.de>
http://www.fischl.de
+++ /dev/null
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--- /dev/null
+With WinAVR version 20080512 or greater, please use libusb_0.1.12.1.
+Use libusb_0.1.10.1 with older WinAVR versions.
--- /dev/null
+[Version]
+Signature = "$Chicago$"
+provider = %manufacturer%
+DriverVer = 03/09/2005,0.1.10.1
+CatalogFile = usbasp.cat
+
+Class = LibUsbDevices
+ClassGUID = {EB781AAF-9C70-4523-A5DF-642A87ECA567}
+
+[ClassInstall]
+AddReg=ClassInstall.AddReg
+
+[ClassInstall32]
+AddReg=ClassInstall.AddReg
+
+[ClassInstall.AddReg]
+HKR,,,,"LibUSB-Win32 Devices"
+HKR,,Icon,,"-20"
+
+[Manufacturer]
+%manufacturer%=Devices
+
+;--------------------------------------------------------------------------
+; Files
+;--------------------------------------------------------------------------
+
+[SourceDisksNames]
+1 = "Libusb-Win32 Driver Installation Disk",,
+
+[SourceDisksFiles]
+libusb0.sys = 1,,
+libusb0.dll = 1,,
+
+[DestinationDirs]
+LIBUSB.Files.Sys = 10,System32\Drivers
+LIBUSB.Files.Dll = 10,System32
+
+[LIBUSB.Files.Sys]
+libusb0.sys
+
+[LIBUSB.Files.Dll]
+libusb0.dll
+
+;--------------------------------------------------------------------------
+; Device driver
+;--------------------------------------------------------------------------
+
+[LIBUSB_DEV]
+CopyFiles = LIBUSB.Files.Sys, LIBUSB.Files.Dll
+AddReg = LIBUSB_DEV.AddReg
+
+[LIBUSB_DEV.NT]
+CopyFiles = LIBUSB.Files.Sys, LIBUSB.Files.Dll
+
+[LIBUSB_DEV.HW]
+DelReg = LIBUSB_DEV.DelReg.HW
+
+[LIBUSB_DEV.NT.HW]
+DelReg = LIBUSB_DEV.DelReg.HW
+
+[LIBUSB_DEV.NT.Services]
+AddService = libusb0, 0x00000002, LIBUSB.AddService
+
+[LIBUSB_DEV.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,libusb0.sys
+
+[LIBUSB_DEV.DelReg.HW]
+HKR,,"LowerFilters"
+
+;--------------------------------------------------------------------------
+; Services
+;--------------------------------------------------------------------------
+
+[LIBUSB.AddService]
+DisplayName = "LibUsb-Win32 - Kernel Driver 03/09/2005, 0.1.10.1"
+ServiceType = 1
+StartType = 3
+ErrorControl = 0
+ServiceBinary = %12%\libusb0.sys
+
+;--------------------------------------------------------------------------
+; Devices
+;--------------------------------------------------------------------------
+
+[Devices]
+"USBasp"=LIBUSB_DEV, USB\VID_16c0&PID_05dc
+
+[Strings]
+manufacturer = "www.fischl.de"
--- /dev/null
+This file will contain the digital signature of the files to be installed
+on the system.
+This file will be provided by Microsoft upon certification of your drivers.
--- /dev/null
+[Version]
+Signature = "$Chicago$"
+provider = %manufacturer%
+DriverVer = 03/20/2007,0.1.12.1
+CatalogFile = usbasp.cat
+CatalogFile.NT = usbasp.cat
+CatalogFile.NTAMD64 = usbasp_x64.cat
+
+Class = LibUsbDevices
+ClassGUID = {EB781AAF-9C70-4523-A5DF-642A87ECA567}
+
+[ClassInstall]
+AddReg=libusb_class_install_add_reg
+
+[ClassInstall32]
+AddReg=libusb_class_install_add_reg
+
+[libusb_class_install_add_reg]
+HKR,,,,"LibUSB-Win32 Devices"
+HKR,,Icon,,"-20"
+
+[Manufacturer]
+%manufacturer%=Devices,NT,NTAMD64
+
+;--------------------------------------------------------------------------
+; Files
+;--------------------------------------------------------------------------
+
+[SourceDisksNames]
+1 = "Libusb-Win32 Driver Installation Disk",,
+
+[SourceDisksFiles]
+libusb0.sys = 1,,
+libusb0.dll = 1,,
+libusb0_x64.sys = 1,,
+libusb0_x64.dll = 1,,
+
+[DestinationDirs]
+libusb_files_sys = 10,system32\drivers
+libusb_files_sys_x64 = 10,system32\drivers
+libusb_files_dll = 10,system32
+libusb_files_dll_wow64 = 10,syswow64
+libusb_files_dll_x64 = 10,system32
+
+[libusb_files_sys]
+libusb0.sys
+
+[libusb_files_sys_x64]
+libusb0.sys,libusb0_x64.sys
+
+[libusb_files_dll]
+libusb0.dll
+
+[libusb_files_dll_wow64]
+libusb0.dll
+
+[libusb_files_dll_x64]
+libusb0.dll,libusb0_x64.dll
+
+;--------------------------------------------------------------------------
+; Device driver
+;--------------------------------------------------------------------------
+
+[LIBUSB_DEV]
+CopyFiles = libusb_files_sys, libusb_files_dll
+AddReg = libusb_add_reg
+
+[LIBUSB_DEV.NT]
+CopyFiles = libusb_files_sys, libusb_files_dll
+
+[LIBUSB_DEV.NTAMD64]
+CopyFiles = libusb_files_sys_x64, libusb_files_dll_wow64, libusb_files_dll_x64
+
+[LIBUSB_DEV.HW]
+DelReg = libusb_del_reg_hw
+AddReg = libusb_add_reg_hw
+
+[LIBUSB_DEV.NT.HW]
+DelReg = libusb_del_reg_hw
+AddReg = libusb_add_reg_hw
+
+[LIBUSB_DEV.NTAMD64.HW]
+DelReg = libusb_del_reg_hw
+AddReg = libusb_add_reg_hw
+
+[LIBUSB_DEV.NT.Services]
+AddService = libusb0, 0x00000002, libusb_add_service
+
+[LIBUSB_DEV.NTAMD64.Services]
+AddService = libusb0, 0x00000002, libusb_add_service
+
+[libusb_add_reg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,libusb0.sys
+
+; Older versions of this .inf file installed filter drivers. They are not
+; needed any more and must be removed
+[libusb_del_reg_hw]
+HKR,,LowerFilters
+HKR,,UpperFilters
+
+; Device properties
+[libusb_add_reg_hw]
+HKR,,SurpriseRemovalOK, 0x00010001, 1
+
+;--------------------------------------------------------------------------
+; Services
+;--------------------------------------------------------------------------
+
+[libusb_add_service]
+DisplayName = "LibUsb-Win32 - Kernel Driver 03/20/2007, 0.1.12.1"
+ServiceType = 1
+StartType = 3
+ErrorControl = 0
+ServiceBinary = %12%\libusb0.sys
+
+;--------------------------------------------------------------------------
+; Devices
+;--------------------------------------------------------------------------
+
+[Devices]
+"USBasp"=LIBUSB_DEV, USB\VID_16c0&PID_05dc
+
+[Devices.NT]
+"USBasp"=LIBUSB_DEV, USB\VID_16c0&PID_05dc
+
+[Devices.NTAMD64]
+"USBasp"=LIBUSB_DEV, USB\VID_16c0&PID_05dc
+
+
+;--------------------------------------------------------------------------
+; Strings
+;--------------------------------------------------------------------------
+
+[Strings]
+manufacturer = "www.fischl.de"
--- /dev/null
+This file will contain the digital signature of the files to be installed
+on the system.
+This file will be provided by Microsoft upon certification of your drivers.
+++ /dev/null
-[Version]
-Signature = "$Chicago$"
-provider = %manufacturer%
-DriverVer = 03/09/2005,0.1.10.1
-CatalogFile = usbasp.cat
-
-Class = LibUsbDevices
-ClassGUID = {EB781AAF-9C70-4523-A5DF-642A87ECA567}
-
-[ClassInstall]
-AddReg=ClassInstall.AddReg
-
-[ClassInstall32]
-AddReg=ClassInstall.AddReg
-
-[ClassInstall.AddReg]
-HKR,,,,"LibUSB-Win32 Devices"
-HKR,,Icon,,"-20"
-
-[Manufacturer]
-%manufacturer%=Devices
-
-;--------------------------------------------------------------------------
-; Files
-;--------------------------------------------------------------------------
-
-[SourceDisksNames]
-1 = "Libusb-Win32 Driver Installation Disk",,
-
-[SourceDisksFiles]
-libusb0.sys = 1,,
-libusb0.dll = 1,,
-
-[DestinationDirs]
-LIBUSB.Files.Sys = 10,System32\Drivers
-LIBUSB.Files.Dll = 10,System32
-
-[LIBUSB.Files.Sys]
-libusb0.sys
-
-[LIBUSB.Files.Dll]
-libusb0.dll
-
-;--------------------------------------------------------------------------
-; Device driver
-;--------------------------------------------------------------------------
-
-[LIBUSB_DEV]
-CopyFiles = LIBUSB.Files.Sys, LIBUSB.Files.Dll
-AddReg = LIBUSB_DEV.AddReg
-
-[LIBUSB_DEV.NT]
-CopyFiles = LIBUSB.Files.Sys, LIBUSB.Files.Dll
-
-[LIBUSB_DEV.HW]
-DelReg = LIBUSB_DEV.DelReg.HW
-
-[LIBUSB_DEV.NT.HW]
-DelReg = LIBUSB_DEV.DelReg.HW
-
-[LIBUSB_DEV.NT.Services]
-AddService = libusb0, 0x00000002, LIBUSB.AddService
-
-[LIBUSB_DEV.AddReg]
-HKR,,DevLoader,,*ntkern
-HKR,,NTMPDriver,,libusb0.sys
-
-[LIBUSB_DEV.DelReg.HW]
-HKR,,"LowerFilters"
-
-;--------------------------------------------------------------------------
-; Services
-;--------------------------------------------------------------------------
-
-[LIBUSB.AddService]
-DisplayName = "LibUsb-Win32 - Kernel Driver 03/09/2005, 0.1.10.1"
-ServiceType = 1
-StartType = 3
-ErrorControl = 0
-ServiceBinary = %12%\libusb0.sys
-
-;--------------------------------------------------------------------------
-; Devices
-;--------------------------------------------------------------------------
-
-[Devices]
-"USBasp"=LIBUSB_DEV, USB\VID_16c0&PID_05dc
-
-[Strings]
-manufacturer = "www.fischl.de"
/*
- clock.c - part of USBasp
-
- Autor..........: Thomas Fischl <tfischl@gmx.de>
- Description....: Provides functions for timing/waiting
- Licence........: GNU GPL v2 (see Readme.txt)
- Creation Date..: 2005-02-23
- Last change....: 2005-04-20
-*/
+ * clock.c - part of USBasp
+ *
+ * Autor..........: Thomas Fischl <tfischl@gmx.de>
+ * Description....: Provides functions for timing/waiting
+ * Licence........: GNU GPL v2 (see Readme.txt)
+ * Creation Date..: 2005-02-23
+ * Last change....: 2005-04-20
+ */
#include <inttypes.h>
#include <avr/io.h>
/* wait time * 320 us */
void clockWait(uint8_t time) {
- uint8_t i;
- for (i = 0; i < time; i++) {
- uint8_t starttime = TIMERVALUE;
- while ((uint8_t) (TIMERVALUE - starttime) < CLOCK_T_320us) {}
- }
+ uint8_t i;
+ for (i = 0; i < time; i++) {
+ uint8_t starttime = TIMERVALUE;
+ while ((uint8_t) (TIMERVALUE - starttime) < CLOCK_T_320us) {
+ }
+ }
}
/*
- clock.h - part of USBasp
-
- Autor..........: Thomas Fischl <tfischl@gmx.de>
- Description....: Provides functions for timing/waiting
- Licence........: GNU GPL v2 (see Readme.txt)
- Creation Date..: 2005-02-23
- Last change....: 2006-11-16
-*/
+ * clock.h - part of USBasp
+ *
+ * Autor..........: Thomas Fischl <tfischl@gmx.de>
+ * Description....: Provides functions for timing/waiting
+ * Licence........: GNU GPL v2 (see Readme.txt)
+ * Creation Date..: 2005-02-23
+ * Last change....: 2006-11-16
+ */
#ifndef __clock_h_included__
#define __clock_h_included__
/*
- isp.c - part of USBasp
-
- Autor..........: Thomas Fischl <tfischl@gmx.de>
- Description....: Provides functions for communication/programming
- over ISP interface
- Licence........: GNU GPL v2 (see Readme.txt)
- Creation Date..: 2005-02-23
- Last change....: 2007-07-23
-*/
+ * isp.c - part of USBasp
+ *
+ * Autor..........: Thomas Fischl <tfischl@gmx.de>
+ * Description....: Provides functions for communication/programming
+ * over ISP interface
+ * Licence........: GNU GPL v2 (see Readme.txt)
+ * Creation Date..: 2005-02-23
+ * Last change....: 2009-02-28
+ */
#include <avr/io.h>
#include "isp.h"
#include "clock.h"
+#include "usbasp.h"
#define spiHWdisable() SPCR = 0
-void spiHWenable() {
+uchar sck_sw_delay;
+uchar sck_spcr;
+uchar sck_spsr;
- /* enable SPI, master, 375kHz SCK */
- SPCR = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
- SPSR = (1 << SPI2X);
+void spiHWenable() {
+ SPCR = sck_spcr;
+ SPSR = sck_spsr;
}
void ispSetSCKOption(uchar option) {
- if (option == 0) {
-
- /* use software spi */
- ispTransmit = ispTransmit_sw;
- // spiHWdisable();
-
- } else {
-
- /* use hardware spi */
- ispTransmit = ispTransmit_hw;
-
- }
+ if (option == USBASP_ISP_SCK_AUTO)
+ option = USBASP_ISP_SCK_375;
+
+ if (option >= USBASP_ISP_SCK_93_75) {
+ ispTransmit = ispTransmit_hw;
+ sck_spsr = 0;
+
+ switch (option) {
+
+ case USBASP_ISP_SCK_1500:
+ /* enable SPI, master, 1.5MHz, XTAL/8 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR0);
+ sck_spsr = (1 << SPI2X);
+ case USBASP_ISP_SCK_750:
+ /* enable SPI, master, 750kHz, XTAL/16 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR0);
+ break;
+ case USBASP_ISP_SCK_375:
+ default:
+ /* enable SPI, master, 375kHz, XTAL/32 (default) */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
+ sck_spsr = (1 << SPI2X);
+ break;
+ case USBASP_ISP_SCK_187_5:
+ /* enable SPI, master, 187.5kHz XTAL/64 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
+ break;
+ case USBASP_ISP_SCK_93_75:
+ /* enable SPI, master, 93.75kHz XTAL/128 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1) | (1 << SPR0);
+ break;
+ }
+
+ } else {
+ ispTransmit = ispTransmit_sw;
+ switch (option) {
+
+ case USBASP_ISP_SCK_32:
+ sck_sw_delay = 3;
+
+ break;
+ case USBASP_ISP_SCK_16:
+ sck_sw_delay = 6;
+
+ break;
+ case USBASP_ISP_SCK_8:
+ sck_sw_delay = 12;
+
+ break;
+ case USBASP_ISP_SCK_4:
+ sck_sw_delay = 24;
+
+ break;
+ case USBASP_ISP_SCK_2:
+ sck_sw_delay = 48;
+
+ break;
+ case USBASP_ISP_SCK_1:
+ sck_sw_delay = 96;
+
+ break;
+ case USBASP_ISP_SCK_0_5:
+ sck_sw_delay = 192;
+
+ break;
+ }
+ }
}
void ispDelay() {
- uint8_t starttime = TIMERVALUE;
- while ((uint8_t) (TIMERVALUE - starttime) < 12) { }
+ uint8_t starttime = TIMERVALUE;
+ while ((uint8_t) (TIMERVALUE - starttime) < sck_sw_delay) {
+ }
}
void ispConnect() {
- /* all ISP pins are inputs before */
- /* now set output pins */
- ISP_DDR |= (1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI);
+ /* all ISP pins are inputs before */
+ /* now set output pins */
+ ISP_DDR |= (1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI);
- /* reset device */
- ISP_OUT &= ~(1 << ISP_RST); /* RST low */
- ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
+ /* reset device */
+ ISP_OUT &= ~(1 << ISP_RST); /* RST low */
+ ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
- /* positive reset pulse > 2 SCK (target) */
- ispDelay();
- ISP_OUT |= (1 << ISP_RST); /* RST high */
- ispDelay();
- ISP_OUT &= ~(1 << ISP_RST); /* RST low */
+ /* positive reset pulse > 2 SCK (target) */
+ ispDelay();
+ ISP_OUT |= (1 << ISP_RST); /* RST high */
+ ispDelay();
+ ISP_OUT &= ~(1 << ISP_RST); /* RST low */
- if (ispTransmit == ispTransmit_hw) {
- spiHWenable();
- }
+ if (ispTransmit == ispTransmit_hw) {
+ spiHWenable();
+ }
}
void ispDisconnect() {
- /* set all ISP pins inputs */
- ISP_DDR &= ~((1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI));
- /* switch pullups off */
- ISP_OUT &= ~((1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI));
+ /* set all ISP pins inputs */
+ ISP_DDR &= ~((1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI));
+ /* switch pullups off */
+ ISP_OUT &= ~((1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI));
- /* disable hardware SPI */
- spiHWdisable();
+ /* disable hardware SPI */
+ spiHWdisable();
}
uchar ispTransmit_sw(uchar send_byte) {
- uchar rec_byte = 0;
- uchar i;
- for (i = 0; i < 8; i++) {
-
- /* set MSB to MOSI-pin */
- if ((send_byte & 0x80) != 0) {
- ISP_OUT |= (1 << ISP_MOSI); /* MOSI high */
- } else {
- ISP_OUT &= ~(1 << ISP_MOSI); /* MOSI low */
- }
- /* shift to next bit */
- send_byte = send_byte << 1;
-
- /* receive data */
- rec_byte = rec_byte << 1;
- if ((ISP_IN & (1 << ISP_MISO)) != 0) {
- rec_byte++;
- }
-
- /* pulse SCK */
- ISP_OUT |= (1 << ISP_SCK); /* SCK high */
- ispDelay();
- ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
- ispDelay();
- }
-
- return rec_byte;
+ uchar rec_byte = 0;
+ uchar i;
+ for (i = 0; i < 8; i++) {
+
+ /* set MSB to MOSI-pin */
+ if ((send_byte & 0x80) != 0) {
+ ISP_OUT |= (1 << ISP_MOSI); /* MOSI high */
+ } else {
+ ISP_OUT &= ~(1 << ISP_MOSI); /* MOSI low */
+ }
+ /* shift to next bit */
+ send_byte = send_byte << 1;
+
+ /* receive data */
+ rec_byte = rec_byte << 1;
+ if ((ISP_IN & (1 << ISP_MISO)) != 0) {
+ rec_byte++;
+ }
+
+ /* pulse SCK */
+ ISP_OUT |= (1 << ISP_SCK); /* SCK high */
+ ispDelay();
+ ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
+ ispDelay();
+ }
+
+ return rec_byte;
}
uchar ispTransmit_hw(uchar send_byte) {
- SPDR = send_byte;
+ SPDR = send_byte;
- while (!(SPSR & (1 << SPIF)));
- return SPDR;
+ while (!(SPSR & (1 << SPIF)))
+ ;
+ return SPDR;
}
uchar ispEnterProgrammingMode() {
- uchar check;
- uchar count = 32;
+ uchar check;
+ uchar count = 32;
- while (count--) {
- ispTransmit(0xAC);
- ispTransmit(0x53);
- check = ispTransmit(0);
- ispTransmit(0);
+ while (count--) {
+ ispTransmit(0xAC);
+ ispTransmit(0x53);
+ check = ispTransmit(0);
+ ispTransmit(0);
- if (check == 0x53) {
- return 0;
- }
+ if (check == 0x53) {
+ return 0;
+ }
- spiHWdisable();
+ spiHWdisable();
- /* pulse SCK */
- ISP_OUT |= (1 << ISP_SCK); /* SCK high */
- ispDelay();
- ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
- ispDelay();
+ /* pulse SCK */
+ ISP_OUT |= (1 << ISP_SCK); /* SCK high */
+ ispDelay();
+ ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
+ ispDelay();
- if (ispTransmit == ispTransmit_hw) {
- spiHWenable();
- }
+ if (ispTransmit == ispTransmit_hw) {
+ spiHWenable();
+ }
- }
+ }
- return 1; /* error: device dosn't answer */
+ return 1; /* error: device dosn't answer */
}
uchar ispReadFlash(unsigned long address) {
- ispTransmit(0x20 | ((address & 1) << 3));
- ispTransmit(address >> 9);
- ispTransmit(address >> 1);
- return ispTransmit(0);
+ ispTransmit(0x20 | ((address & 1) << 3));
+ ispTransmit(address >> 9);
+ ispTransmit(address >> 1);
+ return ispTransmit(0);
}
-
uchar ispWriteFlash(unsigned long address, uchar data, uchar pollmode) {
- /* 0xFF is value after chip erase, so skip programming
- if (data == 0xFF) {
- return 0;
- }
- */
-
- ispTransmit(0x40 | ((address & 1) << 3));
- ispTransmit(address >> 9);
- ispTransmit(address >> 1);
- ispTransmit(data);
-
- if (pollmode == 0)
- return 0;
-
- if (data == 0x7F) {
- clockWait(15); /* wait 4,8 ms */
- return 0;
- } else {
-
- /* polling flash */
- uchar retries = 30;
- uint8_t starttime = TIMERVALUE;
- while (retries != 0) {
- if (ispReadFlash(address) != 0x7F) {
- return 0;
- };
-
- if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
- starttime = TIMERVALUE;
- retries --;
- }
-
- }
- return 1; /* error */
- }
+ /* 0xFF is value after chip erase, so skip programming
+ if (data == 0xFF) {
+ return 0;
+ }
+ */
+
+ ispTransmit(0x40 | ((address & 1) << 3));
+ ispTransmit(address >> 9);
+ ispTransmit(address >> 1);
+ ispTransmit(data);
+
+ if (pollmode == 0)
+ return 0;
+
+ if (data == 0x7F) {
+ clockWait(15); /* wait 4,8 ms */
+ return 0;
+ } else {
+
+ /* polling flash */
+ uchar retries = 30;
+ uint8_t starttime = TIMERVALUE;
+ while (retries != 0) {
+ if (ispReadFlash(address) != 0x7F) {
+ return 0;
+ };
+
+ if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
+ starttime = TIMERVALUE;
+ retries--;
+ }
+
+ }
+ return 1; /* error */
+ }
}
-
uchar ispFlushPage(unsigned long address, uchar pollvalue) {
- ispTransmit(0x4C);
- ispTransmit(address >> 9);
- ispTransmit(address >> 1);
- ispTransmit(0);
-
+ ispTransmit(0x4C);
+ ispTransmit(address >> 9);
+ ispTransmit(address >> 1);
+ ispTransmit(0);
- if (pollvalue == 0xFF) {
- clockWait(15);
- return 0;
- } else {
+ if (pollvalue == 0xFF) {
+ clockWait(15);
+ return 0;
+ } else {
- /* polling flash */
- uchar retries = 30;
- uint8_t starttime = TIMERVALUE;
+ /* polling flash */
+ uchar retries = 30;
+ uint8_t starttime = TIMERVALUE;
- while (retries != 0) {
- if (ispReadFlash(address) != 0xFF) {
- return 0;
- };
+ while (retries != 0) {
+ if (ispReadFlash(address) != 0xFF) {
+ return 0;
+ };
- if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
- starttime = TIMERVALUE;
- retries --;
- }
+ if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
+ starttime = TIMERVALUE;
+ retries--;
+ }
- }
+ }
- return 1; /* error */
- }
+ return 1; /* error */
+ }
}
-
uchar ispReadEEPROM(unsigned int address) {
- ispTransmit(0xA0);
- ispTransmit(address >> 8);
- ispTransmit(address);
- return ispTransmit(0);
+ ispTransmit(0xA0);
+ ispTransmit(address >> 8);
+ ispTransmit(address);
+ return ispTransmit(0);
}
-
uchar ispWriteEEPROM(unsigned int address, uchar data) {
- ispTransmit(0xC0);
- ispTransmit(address >> 8);
- ispTransmit(address);
- ispTransmit(data);
+ ispTransmit(0xC0);
+ ispTransmit(address >> 8);
+ ispTransmit(address);
+ ispTransmit(data);
- clockWait(30); // wait 9,6 ms
+ clockWait(30); // wait 9,6 ms
- return 0;
- /*
- if (data == 0xFF) {
- clockWait(30); // wait 9,6 ms
- return 0;
- } else {
-
- // polling eeprom
- uchar retries = 30; // about 9,6 ms
- uint8_t starttime = TIMERVALUE;
-
- while (retries != 0) {
- if (ispReadEEPROM(address) != 0xFF) {
return 0;
- };
-
- if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
- starttime = TIMERVALUE;
- retries --;
- }
-
- }
- return 1; // error
- }
- */
-
}
/*
- isp.h - part of USBasp
-
- Autor..........: Thomas Fischl <tfischl@gmx.de>
- Description....: Provides functions for communication/programming
- over ISP interface
- Licence........: GNU GPL v2 (see Readme.txt)
- Creation Date..: 2005-02-23
- Last change....: 2007-07-23
-*/
+ * isp.h - part of USBasp
+ *
+ * Autor..........: Thomas Fischl <tfischl@gmx.de>
+ * Description....: Provides functions for communication/programming
+ * over ISP interface
+ * Licence........: GNU GPL v2 (see Readme.txt)
+ * Creation Date..: 2005-02-23
+ * Last change....: 2009-02-28
+ */
#ifndef __isp_h_included__
#define __isp_h_included__
#define ISP_MISO PB4
#define ISP_SCK PB5
-#define ISP_DELAY 1
-#define ISP_SCK_SLOW 0
-#define ISP_SCK_FAST 1
-
/* Prepare connection to target device */
void ispConnect();
/*
- USBasp - USB in-circuit programmer for Atmel AVR controllers
-
- Thomas Fischl <tfischl@gmx.de>
-
- License........: GNU GPL v2 (see Readme.txt)
- Target.........: ATMega8 at 12 MHz
- Creation Date..: 2005-02-20
- Last change....: 2007-07-23
-
- PC2 SCK speed option. GND -> slow (8khz SCK),
- open -> fast (375kHz SCK)
-*/
+ * USBasp - USB in-circuit programmer for Atmel AVR controllers
+ *
+ * Thomas Fischl <tfischl@gmx.de>
+ *
+ * License........: GNU GPL v2 (see Readme.txt)
+ * Target.........: ATMega8 at 12 MHz
+ * Creation Date..: 2005-02-20
+ * Last change....: 2009-02-28
+ *
+ * PC2 SCK speed option.
+ * GND -> slow (8khz SCK),
+ * open -> software set speed (default is 375kHz SCK)
+ */
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
#include <avr/wdt.h>
+#include "usbasp.h"
#include "usbdrv.h"
#include "isp.h"
#include "clock.h"
-#define USBASP_FUNC_CONNECT 1
-#define USBASP_FUNC_DISCONNECT 2
-#define USBASP_FUNC_TRANSMIT 3
-#define USBASP_FUNC_READFLASH 4
-#define USBASP_FUNC_ENABLEPROG 5
-#define USBASP_FUNC_WRITEFLASH 6
-#define USBASP_FUNC_READEEPROM 7
-#define USBASP_FUNC_WRITEEEPROM 8
-#define USBASP_FUNC_SETLONGADDRESS 9
-
-#define PROG_STATE_IDLE 0
-#define PROG_STATE_WRITEFLASH 1
-#define PROG_STATE_READFLASH 2
-#define PROG_STATE_READEEPROM 3
-#define PROG_STATE_WRITEEEPROM 4
-
-#define PROG_BLOCKFLAG_FIRST 1
-#define PROG_BLOCKFLAG_LAST 2
-
-#define ledRedOn() PORTC &= ~(1 << PC1)
-#define ledRedOff() PORTC |= (1 << PC1)
-#define ledGreenOn() PORTC &= ~(1 << PC0)
-#define ledGreenOff() PORTC |= (1 << PC0)
-
static uchar replyBuffer[8];
static uchar prog_state = PROG_STATE_IDLE;
+static uchar prog_sck = USBASP_ISP_SCK_AUTO;
static uchar prog_address_newmode = 0;
static unsigned long prog_address;
static uchar prog_blockflags;
static uchar prog_pagecounter;
-
uchar usbFunctionSetup(uchar data[8]) {
- uchar len = 0;
-
- if(data[1] == USBASP_FUNC_CONNECT){
+ uchar len = 0;
- /* set SCK speed */
- if ((PINC & (1 << PC2)) == 0) {
- ispSetSCKOption(ISP_SCK_SLOW);
- } else {
- ispSetSCKOption(ISP_SCK_FAST);
- }
+ if (data[1] == USBASP_FUNC_CONNECT) {
- /* set compatibility mode of address delivering */
- prog_address_newmode = 0;
+ /* set SCK speed */
+ if ((PINC & (1 << PC2)) == 0) {
+ ispSetSCKOption(USBASP_ISP_SCK_8);
+ } else {
+ ispSetSCKOption(prog_sck);
+ }
- ledRedOn();
- ispConnect();
+ /* set compatibility mode of address delivering */
+ prog_address_newmode = 0;
- } else if (data[1] == USBASP_FUNC_DISCONNECT) {
- ispDisconnect();
- ledRedOff();
+ ledRedOn();
+ ispConnect();
- } else if (data[1] == USBASP_FUNC_TRANSMIT) {
- replyBuffer[0] = ispTransmit(data[2]);
- replyBuffer[1] = ispTransmit(data[3]);
- replyBuffer[2] = ispTransmit(data[4]);
- replyBuffer[3] = ispTransmit(data[5]);
- len = 4;
+ } else if (data[1] == USBASP_FUNC_DISCONNECT) {
+ ispDisconnect();
+ ledRedOff();
- } else if (data[1] == USBASP_FUNC_READFLASH) {
+ } else if (data[1] == USBASP_FUNC_TRANSMIT) {
+ replyBuffer[0] = ispTransmit(data[2]);
+ replyBuffer[1] = ispTransmit(data[3]);
+ replyBuffer[2] = ispTransmit(data[4]);
+ replyBuffer[3] = ispTransmit(data[5]);
+ len = 4;
- if (!prog_address_newmode)
- prog_address = (data[3] << 8) | data[2];
+ } else if (data[1] == USBASP_FUNC_READFLASH) {
- prog_nbytes = (data[7] << 8) | data[6];
- prog_state = PROG_STATE_READFLASH;
- len = 0xff; /* multiple in */
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
- } else if (data[1] == USBASP_FUNC_READEEPROM) {
+ prog_nbytes = (data[7] << 8) | data[6];
+ prog_state = PROG_STATE_READFLASH;
+ len = 0xff; /* multiple in */
- if (!prog_address_newmode)
- prog_address = (data[3] << 8) | data[2];
+ } else if (data[1] == USBASP_FUNC_READEEPROM) {
- prog_nbytes = (data[7] << 8) | data[6];
- prog_state = PROG_STATE_READEEPROM;
- len = 0xff; /* multiple in */
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
- } else if (data[1] == USBASP_FUNC_ENABLEPROG) {
- replyBuffer[0] = ispEnterProgrammingMode();;
- len = 1;
+ prog_nbytes = (data[7] << 8) | data[6];
+ prog_state = PROG_STATE_READEEPROM;
+ len = 0xff; /* multiple in */
- } else if (data[1] == USBASP_FUNC_WRITEFLASH) {
+ } else if (data[1] == USBASP_FUNC_ENABLEPROG) {
+ replyBuffer[0] = ispEnterProgrammingMode();
+ len = 1;
- if (!prog_address_newmode)
- prog_address = (data[3] << 8) | data[2];
+ } else if (data[1] == USBASP_FUNC_WRITEFLASH) {
- prog_pagesize = data[4];
- prog_blockflags = data[5] & 0x0F;
- prog_pagesize += (((unsigned int)data[5] & 0xF0)<<4);
- if (prog_blockflags & PROG_BLOCKFLAG_FIRST) {
- prog_pagecounter = prog_pagesize;
- }
- prog_nbytes = (data[7] << 8) | data[6];
- prog_state = PROG_STATE_WRITEFLASH;
- len = 0xff; /* multiple out */
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
- } else if (data[1] == USBASP_FUNC_WRITEEEPROM) {
+ prog_pagesize = data[4];
+ prog_blockflags = data[5] & 0x0F;
+ prog_pagesize += (((unsigned int) data[5] & 0xF0) << 4);
+ if (prog_blockflags & PROG_BLOCKFLAG_FIRST) {
+ prog_pagecounter = prog_pagesize;
+ }
+ prog_nbytes = (data[7] << 8) | data[6];
+ prog_state = PROG_STATE_WRITEFLASH;
+ len = 0xff; /* multiple out */
- if (!prog_address_newmode)
- prog_address = (data[3] << 8) | data[2];
+ } else if (data[1] == USBASP_FUNC_WRITEEEPROM) {
- prog_pagesize = 0;
- prog_blockflags = 0;
- prog_nbytes = (data[7] << 8) | data[6];
- prog_state = PROG_STATE_WRITEEEPROM;
- len = 0xff; /* multiple out */
+ if (!prog_address_newmode)
+ prog_address = (data[3] << 8) | data[2];
- } else if(data[1] == USBASP_FUNC_SETLONGADDRESS) {
+ prog_pagesize = 0;
+ prog_blockflags = 0;
+ prog_nbytes = (data[7] << 8) | data[6];
+ prog_state = PROG_STATE_WRITEEEPROM;
+ len = 0xff; /* multiple out */
- /* set new mode of address delivering (ignore address delivered in commands) */
- prog_address_newmode = 1;
- /* set new address */
- prog_address = *((unsigned long*)&data[2]);
- }
+ } else if (data[1] == USBASP_FUNC_SETLONGADDRESS) {
- usbMsgPtr = replyBuffer;
+ /* set new mode of address delivering (ignore address delivered in commands) */
+ prog_address_newmode = 1;
+ /* set new address */
+ prog_address = *((unsigned long*) &data[2]);
- return len;
-}
+ } else if (data[1] == USBASP_FUNC_SETISPSCK) {
+ /* set sck option */
+ prog_sck = data[2];
+ replyBuffer[0] = 0;
+ len = 1;
+ }
-uchar usbFunctionRead(uchar *data, uchar len) {
+ usbMsgPtr = replyBuffer;
- uchar i;
-
- /* check if programmer is in correct read state */
- if ((prog_state != PROG_STATE_READFLASH) &&
- (prog_state != PROG_STATE_READEEPROM)) {
- return 0xff;
- }
-
- /* fill packet */
- for (i = 0; i < len; i++) {
- if (prog_state == PROG_STATE_READFLASH) {
- data[i] = ispReadFlash(prog_address);
- } else {
- data[i] = ispReadEEPROM(prog_address);
- }
- prog_address++;
- }
-
- /* last packet? */
- if (len < 8) {
- prog_state = PROG_STATE_IDLE;
- }
-
- return len;
+ return len;
}
+uchar usbFunctionRead(uchar *data, uchar len) {
-uchar usbFunctionWrite(uchar *data, uchar len) {
+ uchar i;
- uchar retVal = 0;
- uchar i;
+ /* check if programmer is in correct read state */
+ if ((prog_state != PROG_STATE_READFLASH) && (prog_state
+ != PROG_STATE_READEEPROM)) {
+ return 0xff;
+ }
- /* check if programmer is in correct write state */
- if ((prog_state != PROG_STATE_WRITEFLASH) &&
- (prog_state != PROG_STATE_WRITEEEPROM)) {
- return 0xff;
- }
+ /* fill packet */
+ for (i = 0; i < len; i++) {
+ if (prog_state == PROG_STATE_READFLASH) {
+ data[i] = ispReadFlash(prog_address);
+ } else {
+ data[i] = ispReadEEPROM(prog_address);
+ }
+ prog_address++;
+ }
+
+ /* last packet? */
+ if (len < 8) {
+ prog_state = PROG_STATE_IDLE;
+ }
+ return len;
+}
- for (i = 0; i < len; i++) {
+uchar usbFunctionWrite(uchar *data, uchar len) {
- if (prog_state == PROG_STATE_WRITEFLASH) {
- /* Flash */
+ uchar retVal = 0;
+ uchar i;
- if (prog_pagesize == 0) {
- /* not paged */
- ispWriteFlash(prog_address, data[i], 1);
- } else {
- /* paged */
- ispWriteFlash(prog_address, data[i], 0);
- prog_pagecounter --;
- if (prog_pagecounter == 0) {
- ispFlushPage(prog_address, data[i]);
- prog_pagecounter = prog_pagesize;
+ /* check if programmer is in correct write state */
+ if ((prog_state != PROG_STATE_WRITEFLASH) && (prog_state
+ != PROG_STATE_WRITEEEPROM)) {
+ return 0xff;
}
- }
- } else {
- /* EEPROM */
- ispWriteEEPROM(prog_address, data[i]);
- }
+ for (i = 0; i < len; i++) {
- prog_nbytes --;
+ if (prog_state == PROG_STATE_WRITEFLASH) {
+ /* Flash */
- if (prog_nbytes == 0) {
- prog_state = PROG_STATE_IDLE;
- if ((prog_blockflags & PROG_BLOCKFLAG_LAST) &&
- (prog_pagecounter != prog_pagesize)) {
+ if (prog_pagesize == 0) {
+ /* not paged */
+ ispWriteFlash(prog_address, data[i], 1);
+ } else {
+ /* paged */
+ ispWriteFlash(prog_address, data[i], 0);
+ prog_pagecounter--;
+ if (prog_pagecounter == 0) {
+ ispFlushPage(prog_address, data[i]);
+ prog_pagecounter = prog_pagesize;
+ }
+ }
- /* last block and page flush pending, so flush it now */
- ispFlushPage(prog_address, data[i]);
- }
+ } else {
+ /* EEPROM */
+ ispWriteEEPROM(prog_address, data[i]);
+ }
- retVal = 1; // Need to return 1 when no more data is to be received
- }
+ prog_nbytes--;
- prog_address ++;
- }
+ if (prog_nbytes == 0) {
+ prog_state = PROG_STATE_IDLE;
+ if ((prog_blockflags & PROG_BLOCKFLAG_LAST) && (prog_pagecounter
+ != prog_pagesize)) {
- return retVal;
-}
+ /* last block and page flush pending, so flush it now */
+ ispFlushPage(prog_address, data[i]);
+ }
+ retVal = 1; // Need to return 1 when no more data is to be received
+ }
-int main(void)
-{
- uchar i, j;
-
- PORTD = 0;
- PORTB = 0; /* no pullups on USB and ISP pins */
- DDRD = ~(1 << 2); /* all outputs except PD2 = INT0 */
+ prog_address++;
+ }
- DDRB = ~0; /* output SE0 for USB reset */
- j = 0;
- while(--j){ /* USB Reset by device only required on Watchdog Reset */
- i = 0;
- while(--i); /* delay >10ms for USB reset */
- }
- DDRB = 0; /* all USB and ISP pins inputs */
+ return retVal;
+}
- DDRC = 0x03; /* all inputs except PC0, PC1 */
- PORTC = 0xfe;
+int main(void) {
+ uchar i, j;
+
+ /* no pullups on USB and ISP pins */
+ PORTD = 0;
+ PORTB = 0;
+ /* all outputs except PD2 = INT0 */
+ DDRD = ~(1 << 2);
+
+ /* output SE0 for USB reset */
+ DDRB = ~0;
+ j = 0;
+ /* USB Reset by device only required on Watchdog Reset */
+ while (--j) {
+ i = 0;
+ /* delay >10ms for USB reset */
+ while (--i)
+ ;
+ }
+ /* all USB and ISP pins inputs */
+ DDRB = 0;
- clockInit(); /* init timer */
+ /* all inputs except PC0, PC1 */
+ DDRC = 0x03;
+ PORTC = 0xfe;
- ispSetSCKOption(ISP_SCK_FAST);
+ /* init timer */
+ clockInit();
- usbInit();
- sei();
- for(;;){ /* main event loop */
- usbPoll();
- }
- return 0;
+ /* main event loop */
+ usbInit();
+ sei();
+ for (;;) {
+ usbPoll();
+ }
+ return 0;
}
--- /dev/null
+/*
+ * usbasp.c - part of USBasp
+ *
+ * Autor..........: Thomas Fischl <tfischl@gmx.de>
+ * Description....: Definitions and macros for usbasp
+ * Licence........: GNU GPL v2 (see Readme.txt)
+ * Creation Date..: 2009-02-28
+ * Last change....: 2009-02-28
+ */
+
+#ifndef USBASP_H_
+#define USBASP_H_
+
+/* USB function call identifiers */
+#define USBASP_FUNC_CONNECT 1
+#define USBASP_FUNC_DISCONNECT 2
+#define USBASP_FUNC_TRANSMIT 3
+#define USBASP_FUNC_READFLASH 4
+#define USBASP_FUNC_ENABLEPROG 5
+#define USBASP_FUNC_WRITEFLASH 6
+#define USBASP_FUNC_READEEPROM 7
+#define USBASP_FUNC_WRITEEEPROM 8
+#define USBASP_FUNC_SETLONGADDRESS 9
+#define USBASP_FUNC_SETISPSCK 10
+
+/* programming state */
+#define PROG_STATE_IDLE 0
+#define PROG_STATE_WRITEFLASH 1
+#define PROG_STATE_READFLASH 2
+#define PROG_STATE_READEEPROM 3
+#define PROG_STATE_WRITEEEPROM 4
+
+/* Block mode flags */
+#define PROG_BLOCKFLAG_FIRST 1
+#define PROG_BLOCKFLAG_LAST 2
+
+/* ISP SCK speed identifiers */
+#define USBASP_ISP_SCK_AUTO 0
+#define USBASP_ISP_SCK_0_5 1 /* 500 Hz */
+#define USBASP_ISP_SCK_1 2 /* 1 kHz */
+#define USBASP_ISP_SCK_2 3 /* 2 kHz */
+#define USBASP_ISP_SCK_4 4 /* 4 kHz */
+#define USBASP_ISP_SCK_8 5 /* 8 kHz */
+#define USBASP_ISP_SCK_16 6 /* 16 kHz */
+#define USBASP_ISP_SCK_32 7 /* 32 kHz */
+#define USBASP_ISP_SCK_93_75 8 /* 93.75 kHz */
+#define USBASP_ISP_SCK_187_5 9 /* 187.5 kHz */
+#define USBASP_ISP_SCK_375 10 /* 375 kHz */
+#define USBASP_ISP_SCK_750 11 /* 750 kHz */
+#define USBASP_ISP_SCK_1500 12 /* 1.5 MHz */
+
+/* macros for gpio functions */
+#define ledRedOn() PORTC &= ~(1 << PC1)
+#define ledRedOff() PORTC |= (1 << PC1)
+#define ledGreenOn() PORTC &= ~(1 << PC0)
+#define ledGreenOff() PORTC |= (1 << PC0)
+
+#endif /* USBASP_H_ */
* you use obdev's free shared VID/PID pair. Be sure to read the rules in
* USBID-License.txt!
*/
-#define USB_CFG_DEVICE_VERSION 0x02, 0x01
+#define USB_CFG_DEVICE_VERSION 0x03, 0x01
/* Version number of the device: Minor number first, then major number.
*/
#define USB_CFG_VENDOR_NAME 'w', 'w', 'w', '.', 'f', 'i', 's', 'c', 'h', 'l', '.', 'd', 'e'
- 16 MHz module: Do SE0 check in stuffed bits as well.
* Release 2007-07-07
+
+ - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary
+ for negative values.
+ - Added 15 MHz module contributed by V. Bosch.
+ - Interrupt vector name can now be configured. This is useful if somebody
+ wants to use a different hardware interrupt than INT0.
+
+* Release 2007-08-07
+
+ - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is
+ not exceeded.
+ - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN,
+ USB_COUNT_SOF
+ - USB_INTR_PENDING can now be a memory address, not just I/O
+
+* Release 2007-09-19
+
+ - Split out common parts of assembler modules into separate include file
+ - Made endpoint numbers configurable so that given interface definitions
+ can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h.
+ - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut()
+ can handle any number of endpoints.
+ - Define usbDeviceConnect() and usbDeviceDisconnect() even if no
+ USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this
+ case.
+
+* Release 2007-12-01
+
+ - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size
+ when USB_CFG_PULLUP_IOPORTNAME is not defined.
+
+* Release 2007-12-13
+
+ - Renamed all include-only assembler modules from *.S to *.inc so that
+ people don't add them to their project sources.
+ - Distribute leap bits in tx loop more evenly for 16 MHz module.
+ - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR
+ - Avoid compiler warnings for constant expr range by casting some values in
+ USB descriptors.
+
+* Release 2008-01-21
+
+ - Fixed bug in 15 and 16 MHz module where the new address set with
+ SET_ADDRESS was already accepted at the next NAK or ACK we send, not at
+ the next data packet we send. This caused problems when the host polled
+ too fast. Thanks to Alexander Neumann for his help and patience debugging
+ this issue!
+
+* Release 2008-02-05
+
+ - Fixed bug in 16.5 MHz module where a register was used in the interrupt
+ handler before it was pushed. This bug was introduced with version
+ 2007-09-19 when common parts were moved to a separate file.
+ - Optimized CRC routine (thanks to Reimar Doeffinger).
+
+* Release 2008-02-16
+
+ - Removed outdated IAR compatibility stuff (code sections).
+ - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK().
+ - Added optional routine usbMeasureFrameLength() for calibration of the
+ internal RC oscillator.
+
+* Release 2008-02-28
+
+ - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we
+ start with sending USBPID_DATA0.
+ - Changed defaults in usbconfig-prototype.h
+ - Added free USB VID/PID pair for MIDI class devices
+ - Restructured AVR-USB as separate package, not part of PowerSwitch any more.
+
+* Release 2008-04-18
+
+ - Restructured usbdrv.c so that it is easier to read and understand.
+ - Better code optimization with gcc 4.
+ - If a second interrupt in endpoint is enabled, also add it to config
+ descriptor.
+ - Added config option for long transfers (above 254 bytes), see
+ USB_CFG_LONG_TRANSFERS in usbconfig.h.
+ - Added 20 MHz module contributed by Jeroen Benschop.
+
+* Release 2008-05-13
+
+ - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length
+ was not incremented, pointer to length was incremented instead.
+ - Added code to command line tool(s) which claims an interface. This code
+ is disabled by default, but may be necessary on newer Linux kernels.
+ - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING".
+ - New header "usbportability.h" prepares ports to other development
+ environments.
+ - Long transfers (above 254 bytes) did not work when usbFunctionRead() was
+ used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!]
+ - In hiddata.c (example code for sending/receiving data over HID), use
+ USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so
+ that we need not claim the interface.
+ - in usbPoll() loop 20 times polling for RESET state instead of 10 times.
+ This accounts for the higher clock rates we now support.
+ - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop.
+ - Added hook to SOF code so that oscillator can be tuned to USB frame clock.
+ - Added timeout to waitForJ loop. Helps preventing unexpected hangs.
+ - Added example code for oscillator tuning to libs-device (thanks to
+ Henrik Haftmann for the idea to this routine).
+ - Implemented option USB_CFG_SUPPRESS_INTR_CODE.
+
+* Release 2008-10-22
+
+ - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and
+ similar, not offset of 0x20 needs to be added.
+ - Allow distribution under GPLv3 for those who have to link against other
+ code distributed under GPLv3.
+
+* Release 2008-11-26
AVR-USB Driver Software License Agreement
-Version 2006-07-24
+Version 2008-10-07
THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN
ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING
1.2 "You" shall mean the Licensee.
-1.3 "AVR-USB" shall mean the firmware-only USB device implementation for
-Atmel AVR microcontrollers distributed by OBJECTIVE DEVELOPMENT and
-consisting of the files usbdrv.c, usbdrv.h, usbdrvasm.S, oddebug.c,
-oddebug.h, usbdrvasm.asm, iarcompat.h and usbconfig-prototype.h.
+1.3 "AVR-USB" shall mean all files included in the package distributed under
+the name "avrusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/avrusb/)
+unless otherwise noted. This includes the firmware-only USB device
+implementation for Atmel AVR microcontrollers, some simple device examples
+and host side software examples and libraries.
2 LICENSE GRANTS
code of AVR-USB.
2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the
-non-exclusive right to use and distribute AVR-USB with your hardware
+non-exclusive right to use, copy and distribute AVR-USB with your hardware
product(s), restricted by the limitations in section 3 below.
2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify
-your copy of AVR-USB according to your needs.
+the source code and your copy of AVR-USB according to your needs.
2.4 USB IDs. OBJECTIVE DEVELOPMENT grants you the exclusive rights to use
USB Product ID(s) sent to you in e-mail after receiving your payment in
OBJECTIVE DEVELOPMENT GmbH's AVR-USB driver software is distributed under the
-terms and conditions of the GNU GPL version 2, see the text below. In addition
-to the requirements in the GPL, we STRONGLY ENCOURAGE you to do the following:
+terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is
+your choice whether you apply the terms of version 2 or version 3. The full
+text of GPLv2 is included below. In addition to the requirements in the GPL,
+we STRONGLY ENCOURAGE you to do the following:
(1) Publish your entire project on a web site and drop us a note with the URL.
Use the form at http://www.obdev.at/avrusb/feedback.html for your submission.
The precise terms and conditions for copying, distribution and
modification follow.
-
+\f
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
-
+\f
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
-
+\f
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
-
+\f
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
-
+\f
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
http://www.obdev.at/avrusb/
This directory contains the USB firmware only. Copy it as-is to your own
-project and add your own version of "usbconfig.h". A template for your own
-"usbconfig.h" can be found in "usbconfig-prototype.h" in this directory.
+project and add all .c and .S files to your project (these files are marked
+with an asterisk in the list below). Then copy usbconfig-prototype.h as
+usbconfig.h to your project and edit it according to your configuration.
TECHNICAL DOCUMENTATION
a stub and includes one of the usbdrvasm*.S files
depending on processor clock. Link this module to
your code!
- usbdrvasm12.S .......... 12 MHz version of the assembler routines. Included
- by usbdrvasm.S, don't link it directly!
- usbdrvasm16.S .......... 16 MHz version of the assembler routines. Included
- by usbdrvasm.S, don't link it directly!
- usbdrvasm165.S ......... 16.5 MHz version of the assembler routines including
- a PLL so that an 1% accurate RC oscillator can be
- used. Included by usbdrvasm.S, don't link directly!
+ usbdrvasm*.inc ......... Assembler routines for particular clock frequencies.
+ Included by usbdrvasm.S, don't link it directly!
+ asmcommon.inc .......... Common assembler routines. Included by
+ usbdrvasm*.inc, don't link it directly!
usbconfig-prototype.h .. Prototype for your own usbdrv.h file.
* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is
defined to a value greater than 0. Link this module
to your code!
oddebug.h .............. Interface definitions of the debug module.
- iarcompat.h ............ Compatibility definitions for IAR C-compiler.
+ usbportability.h ....... Header with compiler-dependent stuff.
usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this
module instead of usbdrvasm.S when you assembler
with IAR's tools.
CPU CORE CLOCK FREQUENCY
========================
-We supply assembler modules for clock frequencies of 12 MHz, 16 MHz and
-16.5 MHz. Other clock rates are not supported. The actual clock rate must be
-configured in usbdrv.h unless you use the default 12 MHz.
+We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz,
+16 MHz, 16.5 MHz and 20 MHz. Other clock rates are not supported. The actual
+clock rate must be configured in usbdrv.h unless you use the default 12 MHz.
12 MHz Clock
This is the traditional clock rate of AVR-USB because it's the lowest clock
rate where the timing constraints of the USB spec can be met.
+15 MHz Clock
+Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock
+rate allows for some loops which make the resulting code size somewhat smaller
+than the 12 MHz version.
+
16 MHz Clock
This clock rate has been added for users of the Arduino board and other
ready-made boards which come with a fixed 16 MHz crystal. It's also an option
16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code
is somewhat tricky and has to insert a leap cycle every third byte.
-16.5 MHz Clock
-The assembler module for this clock rate differs from the other modules because
-it has been built for an RC oscillator with only 1% precision. The receiver
-code inserts leap cycles to compensate for clock deviations. 1% is also the
-precision which can be achieved by calibrating the internal RC oscillator of
-the AVR. Please note that only AVRs with internal 64 MHz PLL oscillator can be
-used since the 8 MHz RC oscillator cannot be trimmed up to 16.5 MHz. This
-includes the very popular ATTiny25, ATTiny45, ATTiny85 series as well as the
-ATTiny26.
+12.8 MHz and 16.5 MHz Clock
+The assembler modules for these clock rates differ from the other modules
+because they have been built for an RC oscillator with only 1% precision. The
+receiver code inserts leap cycles to compensate for clock deviations. 1% is
+also the precision which can be achieved by calibrating the internal RC
+oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL
+oscillator can reach 16.5 MHz with the RC oscillator. This includes the very
+popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost
+all AVRs can reach 12.8 MHz, although this is outside the specified range.
+
+See the EasyLogger example at http://www.obdev.at/avrusb/easylogger.html for
+code which calibrates the RC oscillator based on the USB frame clock.
-We recommend that you obtain appropriate calibration values for 16.5 MHz core
-clock at programming time and store it in flash or EEPROM or compute the value
-from a reference clock at run time. However, since Atmel's 8 MHz calibration
-is much more precise than the guaranteed 10%, it's usually possible to add a
-fixed offset to this value.
+20 MHz Clock
+This module is for people who won't do it with less than the maximum. Since
+20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code
+uses similar tricks as the 16 MHz module to insert leap cycles.
USB IDENTIFIERS
can assign PIDs at will.
Since an entry level cost of 1,500 USD is too high for most small companies
-and hobbyists, we provide a single VID/PID pair for free. If you want to use
-your own VID and PID instead of our's, define the macros "USB_CFG_VENDOR_ID"
-and "USB_CFG_DEVICE_ID" accordingly in "usbconfig.h".
-
-To use our predefined VID/PID pair, you MUST conform to a couple of
-requirements. See the file "USBID-License.txt" for details.
-
-Objective Development also has some offerings which include product IDs. See
-http://www.obdev.at/avrusb/ for details.
-
+and hobbyists, we provide some VID/PID pairs for free. See the file
+USBID-License.txt for details.
-HOST DRIVER
-===========
-You have received this driver together with an example device implementation
-and an example host driver. The host driver is based on libusb and compiles
-on various Unix flavors (Linux, BSD, Mac OS X). It also compiles natively on
-Windows using MinGW (see www.mingw.org) and libusb-win32 (see
-libusb-win32.sourceforge.net). The "Automator" project contains a native
-Windows host driver (not based on libusb) for Human Interface Devices.
+Objective Development also has some license offerings which include product
+IDs. See http://www.obdev.at/avrusb/ for details.
DEVELOPMENT SYSTEM
==================
This driver has been developed and optimized for the GNU compiler version 3
-(gcc 3). It does work well with gcc 4 and future versions will probably be
-optimized for gcc 4. We recommend that you use the GNU compiler suite because
-it is freely available. AVR-USB has also been ported to the IAR compiler and
-assembler. It has been tested with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8
-with the "small" and "tiny" memory model. Please note that gcc is more
-efficient for usbdrv.c because this module has been deliberately optimized
-for gcc.
+(gcc 3). It does work well with gcc 4, but with bigger code size. We recommend
+that you use the GNU compiler suite because it is freely available. AVR-USB
+has also been ported to the IAR compiler and assembler. It has been tested
+with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the "small" and "tiny"
+memory model. Not every release is tested with IAR CC and the driver may
+therefore fail to compile with IAR. Please note that gcc is more efficient for
+usbdrv.c because this module has been deliberately optimized for gcc.
USING AVR-USB FOR FREE
======================
The AVR firmware driver is published under the GNU General Public License
-Version 2 (GPL2). See the file "License.txt" for details.
+Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is
+your choice whether you apply the terms of version 2 or version 3.
-If you decide for the free GPL2, we STRONGLY ENCOURAGE you to do the following
-things IN ADDITION to the obligations from the GPL2:
+If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the
+following things IN ADDITION to the obligations from the GPL:
(1) Publish your entire project on a web site and drop us a note with the URL.
Use the form at http://www.obdev.at/avrusb/feedback.html for your submission.
+If you don't have a web site, you can publish the project in obdev's
+documentation wiki at
+http://www.obdev.at/goto.php?t=avrusb-wiki&p=hosted-projects.
(2) Adhere to minimum publication standards. Please include AT LEAST:
- a circuit diagram in PDF, PNG or GIF format
COMMERCIAL LICENSES FOR AVR-USB
===============================
-If you don't want to publish your source code under the terms of the GPL2,
+If you don't want to publish your source code under the terms of the GPL,
you can simply pay money for AVR-USB. As an additional benefit you get
USB PIDs for free, licensed exclusively to you. See the file
"CommercialLicense.txt" for details.
Royalty-Free Non-Exclusive License USB Product-ID
=================================================
-Version 2006-06-19
+Version 2008-04-07
OBJECTIVE DEVELOPMENT Software GmbH hereby grants you the non-exclusive
right to use three USB.org vendor-ID (VID) / product-ID (PID) pairs with
* VID = 5824 (=0x16c0) / PID = 1505 (=0x5e1) for CDC class modem devices
Devices using this pair will be referred to as "CDC-ACM CLASS" devices.
+ * VID = 5824 (=0x16c0) / PID = 1508 (=0x5e4) for MIDI class devices
+ Devices using this pair will be referred to as "MIDI CLASS" devices.
+
Since the granted right is non-exclusive, the same VID/PID pairs may be
used by many companies and individuals for different products. To avoid
conflicts, your device and host driver software MUST adhere to the rules
VID/PID matching only (e.g. Windows kernel level drivers, automatic actions
when the device is plugged in etc) MUST NOT be used. The driver matching
MUST be a comparison of the entire strings, NOT a sub-string match. For
-CDC-ACM CLASS devices, a generic class driver should be used and the
-matching is based on the USB device class.
+CDC-ACM CLASS and MIDI CLASS devices, a generic class driver should be used
+and the matching is based on the USB device class.
(6) The extent to which VID/PID matching is allowed for non device-specific
drivers or features depends on the operating system and particular VID/PID
============================
The following rules are for VENDOR CLASS and HID CLASS devices. CDC-ACM
-CLASS devices use the operating system's class driver and don't need a
-custom driver.
+CLASS and MIDI CLASS devices use the operating system's class driver and
+don't need a custom driver.
The host driver MUST iterate over all devices with the given VID/PID
numbers in their device descriptors and query the string representation for
--- /dev/null
+/* Name: asmcommon.inc
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-11-05
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id$
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file contains assembler code which is shared among the USB driver
+implementations for different CPU cocks. Since the code must be inserted
+in the middle of the module, it's split out into this file and #included.
+
+Jump destinations called from outside:
+ sofError: Called when no start sequence was found.
+ se0: Called when a package has been successfully received.
+ overflow: Called when receive buffer overflows.
+ doReturn: Called after sending data.
+
+Outside jump destinations used by this module:
+ waitForJ: Called to receive an already arriving packet.
+ sendAckAndReti:
+ sendNakAndReti:
+ sendCntAndReti:
+ usbSendAndReti:
+
+The following macros must be defined before this file is included:
+ .macro POP_STANDARD
+ .endm
+ .macro POP_RETI
+ .endm
+*/
+
+#define token x1
+
+overflow:
+ ldi x2, 1<<USB_INTR_PENDING_BIT
+ USB_STORE_PENDING(x2) ; clear any pending interrupts
+ignorePacket:
+ clr token
+ rjmp storeTokenAndReturn
+
+;----------------------------------------------------------------------------
+; Processing of received packet (numbers in brackets are cycles after center of SE0)
+;----------------------------------------------------------------------------
+;This is the only non-error exit point for the software receiver loop
+;we don't check any CRCs here because there is no time left.
+se0:
+ subi cnt, USB_BUFSIZE ;[5]
+ neg cnt ;[6]
+ sub YL, cnt ;[7]
+ sbci YH, 0 ;[8]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;[9]
+ USB_STORE_PENDING(x2) ;[10] clear pending intr and check flag later. SE0 should be over.
+ ld token, y ;[11]
+ cpi token, USBPID_DATA0 ;[13]
+ breq handleData ;[14]
+ cpi token, USBPID_DATA1 ;[15]
+ breq handleData ;[16]
+ lds shift, usbDeviceAddr;[17]
+ ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
+ lsl x2 ;[21] shift out 1 bit endpoint number
+ cpse x2, shift ;[22]
+ rjmp ignorePacket ;[23]
+/* only compute endpoint number in x3 if required later */
+#if USB_CFG_HAVE_INTRIN_ENDPOINT || USB_CFG_IMPLEMENT_FN_WRITEOUT
+ ldd x3, y+2 ;[24] endpoint number + crc
+ rol x3 ;[26] shift in LSB of endpoint
+#endif
+ cpi token, USBPID_IN ;[27]
+ breq handleIn ;[28]
+ cpi token, USBPID_SETUP ;[29]
+ breq handleSetupOrOut ;[30]
+ cpi token, USBPID_OUT ;[31]
+ brne ignorePacket ;[32] must be ack, nak or whatever
+; rjmp handleSetupOrOut ; fallthrough
+
+;Setup and Out are followed by a data packet two bit times (16 cycles) after
+;the end of SE0. The sync code allows up to 40 cycles delay from the start of
+;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
+handleSetupOrOut: ;[32]
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for endpoint != 0, set usbCurrentTok to address */
+ andi x3, 0xf ;[32]
+ breq storeTokenAndReturn ;[33]
+ mov token, x3 ;[34] indicate that this is endpoint x OUT
+#endif
+storeTokenAndReturn:
+ sts usbCurrentTok, token;[35]
+doReturn:
+ POP_STANDARD ;[37] 12...16 cycles
+ USB_LOAD_PENDING(YL) ;[49]
+ sbrc YL, USB_INTR_PENDING_BIT;[50] check whether data is already arriving
+ rjmp waitForJ ;[51] save the pops and pushes -- a new interrupt is already pending
+sofError:
+ POP_RETI ;macro call
+ reti
+
+handleData:
+ lds shift, usbCurrentTok;[18]
+ tst shift ;[20]
+ breq doReturn ;[21]
+ lds x2, usbRxLen ;[22]
+ tst x2 ;[24]
+ brne sendNakAndReti ;[25]
+; 2006-03-11: The following two lines fix a problem where the device was not
+; recognized if usbPoll() was called less frequently than once every 4 ms.
+ cpi cnt, 4 ;[26] zero sized data packets are status phase only -- ignore and ack
+ brmi sendAckAndReti ;[27] keep rx buffer clean -- we must not NAK next SETUP
+#if USB_CFG_CHECK_DATA_TOGGLING
+ sts usbCurrentDataToken, token ; store for checking by C code
+#endif
+ sts usbRxLen, cnt ;[28] store received data, swap buffers
+ sts usbRxToken, shift ;[30]
+ lds x2, usbInputBufOffset;[32] swap buffers
+ ldi cnt, USB_BUFSIZE ;[34]
+ sub cnt, x2 ;[35]
+ sts usbInputBufOffset, cnt;[36] buffers now swapped
+ rjmp sendAckAndReti ;[38] 40 + 17 = 57 until SOP
+
+handleIn:
+;We don't send any data as long as the C code has not processed the current
+;input data and potentially updated the output data. That's more efficient
+;in terms of code size than clearing the tx buffers when a packet is received.
+ lds x1, usbRxLen ;[30]
+ cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
+ brge sendNakAndReti ;[33] unprocessed input packet?
+ ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+ andi x3, 0xf ;[35] x3 contains endpoint
+#if USB_CFG_SUPPRESS_INTR_CODE
+ brne sendNakAndReti ;[36]
+#else
+ brne handleIn1 ;[36]
+#endif
+#endif
+ lds cnt, usbTxLen ;[37]
+ sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
+ sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf) ;[43]
+ ldi YH, hi8(usbTxBuf) ;[44]
+ rjmp usbSendAndReti ;[45] 57 + 12 = 59 until SOP
+
+; Comment about when to set usbTxLen to USBPID_NAK:
+; We should set it back when we receive the ACK from the host. This would
+; be simple to implement: One static variable which stores whether the last
+; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
+; ACK. However, we set it back immediately when we send the package,
+; assuming that no error occurs and the host sends an ACK. We save one byte
+; RAM this way and avoid potential problems with endless retries. The rest of
+; the driver assumes error-free transfers anyway.
+
+#if !USB_CFG_SUPPRESS_INTR_CODE && USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
+handleIn1: ;[38]
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
+ cpi x3, USB_CFG_EP3_NUMBER;[38]
+ breq handleIn3 ;[39]
+#endif
+ lds cnt, usbTxLen1 ;[40]
+ sbrc cnt, 4 ;[42] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[43] 47 + 16 = 63 until SOP
+ sts usbTxLen1, x1 ;[44] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf1) ;[46]
+ ldi YH, hi8(usbTxBuf1) ;[47]
+ rjmp usbSendAndReti ;[48] 50 + 12 = 62 until SOP
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+handleIn3:
+ lds cnt, usbTxLen3 ;[41]
+ sbrc cnt, 4 ;[43]
+ rjmp sendCntAndReti ;[44] 49 + 16 = 65 until SOP
+ sts usbTxLen3, x1 ;[45] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf3) ;[47]
+ ldi YH, hi8(usbTxBuf3) ;[48]
+ rjmp usbSendAndReti ;[49] 51 + 12 = 63 until SOP
+#endif
+#endif
+++ /dev/null
-/* Name: iarcompat.h
- * Project: AVR USB driver
- * Author: Christian Starkjohann
- * Creation Date: 2006-03-01
- * Tabsize: 4
- * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: iarcompat.h 275 2007-03-20 09:58:28Z cs $
- */
-
-/*
-General Description:
-This header is included when we compile with the IAR C-compiler and assembler.
-It defines macros for cross compatibility between gcc and IAR-cc.
-
-Thanks to Oleg Semyonov for his help with the IAR tools port!
-*/
-
-#ifndef __iarcompat_h_INCLUDED__
-#define __iarcompat_h_INCLUDED__
-
-#if defined __IAR_SYSTEMS_ICC__ || defined __IAR_SYSTEMS_ASM__
-
-/* Enable bit definitions */
-#ifndef ENABLE_BIT_DEFINITIONS
-# define ENABLE_BIT_DEFINITIONS 1
-#endif
-
-/* Include IAR headers */
-#include <ioavr.h>
-#ifndef __IAR_SYSTEMS_ASM__
-# include <inavr.h>
-#endif
-
-#define __attribute__(arg)
-#define IAR_SECTION(section) @ section
-
-#ifndef USB_BUFFER_SECTION
-# define USB_BUFFER_SECTION "TINY_Z" /* if user has not selected a named section */
-#endif
-
-#ifdef __IAR_SYSTEMS_ASM__
-# define __ASSEMBLER__
-#endif
-
-#ifdef __HAS_ELPM__
-# define PROGMEM __farflash
-#else
-# define PROGMEM __flash
-#endif
-
-#define PRG_RDB(addr) (*(PROGMEM char *)(addr))
-
-/* The following definitions are not needed by the driver, but may be of some
- * help if you port a gcc based project to IAR.
- */
-#define cli() __disable_interrupt()
-#define sei() __enable_interrupt()
-#define wdt_reset() __watchdog_reset()
-
-/* Depending on the device you use, you may get problems with the way usbdrv.h
- * handles the differences between devices. Since IAR does not use #defines
- * for MCU registers, we can't check for the existence of a particular
- * register with an #ifdef. If the autodetection mechanism fails, include
- * definitions for the required USB_INTR_* macros in your usbconfig.h. See
- * usbconfig-prototype.h and usbdrv.h for details.
- */
-
-#endif /* defined __IAR_SYSTEMS_ICC__ || defined __IAR_SYSTEMS_ASM__ */
-#endif /* __iarcompat_h_INCLUDED__ */
* Creation Date: 2005-01-16
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: oddebug.c 275 2007-03-20 09:58:28Z cs $
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: oddebug.c 692 2008-11-07 15:07:40Z cs $
*/
#include "oddebug.h"
* Creation Date: 2005-01-16
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: oddebug.h 275 2007-03-20 09:58:28Z cs $
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $
*/
#ifndef __oddebug_h_included__
#endif
/* make sure we have the UART defines: */
-#include "iarcompat.h"
-#ifndef __IAR_SYSTEMS_ICC__
-# include <avr/io.h>
-#endif
+#include "usbportability.h"
#ifndef uchar
# define uchar unsigned char
* Creation Date: 2005-04-01
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: usbconfig-prototype.h 358 2007-06-23 13:30:30Z cs $
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbconfig-prototype.h 692 2008-11-07 15:07:40Z cs $
*/
#ifndef __usbconfig_h_included__
/*
General Description:
This file is an example configuration (with inline documentation) for the USB
-driver. It configures AVR-USB for an ATMega8 with USB D+ connected to Port D
-bit 2 (which is also hardware interrupt 0) and USB D- to Port D bit 0. You may
-wire the lines to any other port, as long as D+ is also wired to INT0.
-To create your own usbconfig.h file, copy this file to the directory
-containing "usbdrv" (that is your project firmware source directory) and
-rename it to "usbconfig.h". Then edit it accordingly.
+driver. It configures AVR-USB for USB D+ connected to Port D bit 2 (which is
+also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may
+wire the lines to any other port, as long as D+ is also wired to INT0 (or any
+other hardware interrupt, as long as it is the highest level interrupt, see
+section at the end of this file).
++ To create your own usbconfig.h file, copy this file to your project's
++ firmware source directory) and rename it to "usbconfig.h".
++ Then edit it accordingly.
*/
/* ---------------------------- Hardware Config ---------------------------- */
/* This is the port where the USB bus is connected. When you configure it to
* "B", the registers PORTB, PINB and DDRB will be used.
*/
-#define USB_CFG_DMINUS_BIT 0
+#define USB_CFG_DMINUS_BIT 4
/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected.
* This may be any bit in the port.
*/
#define USB_CFG_DPLUS_BIT 2
/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected.
* This may be any bit in the port. Please note that D+ must also be connected
- * to interrupt pin INT0!
+ * to interrupt pin INT0! [You can also use other interrupts, see section
+ * "Optional MCU Description" below, or you can connect D- to the interrupt, as
+ * it is required if you use the USB_COUNT_SOF feature. If you use D- for the
+ * interrupt, the USB interrupt will also be triggered at Start-Of-Frame
+ * markers every millisecond.]
*/
-/* #define USB_CFG_CLOCK_KHZ (F_CPU/1000) */
-/* Clock rate of the AVR in MHz. Legal values are 12000, 16000 or 16500.
- * The 16.5 MHz version of the code requires no crystal, it tolerates +/- 1%
- * deviation from the nominal frequency. All other rates require a precision
- * of 2000 ppm and thus a crystal!
+#define USB_CFG_CLOCK_KHZ (F_CPU/1000)
+/* Clock rate of the AVR in MHz. Legal values are 12000, 12800, 15000, 16000,
+ * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no
+ * crystal, they tolerate +/- 1% deviation from the nominal frequency. All
+ * other rates require a precision of 2000 ppm and thus a crystal!
* Default if not specified: 12 MHz
*/
/* --------------------------- Functional Range ---------------------------- */
-#define USB_CFG_HAVE_INTRIN_ENDPOINT 1
+#define USB_CFG_HAVE_INTRIN_ENDPOINT 0
/* Define this to 1 if you want to compile a version with two endpoints: The
- * default control endpoint 0 and an interrupt-in endpoint 1.
+ * default control endpoint 0 and an interrupt-in endpoint (any other endpoint
+ * number).
*/
#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0
/* Define this to 1 if you want to compile a version with three endpoints: The
- * default control endpoint 0, an interrupt-in endpoint 1 and an interrupt-in
- * endpoint 3. You must also enable endpoint 1 above.
+ * default control endpoint 0, an interrupt-in endpoint 3 (or the number
+ * configured below) and a catch-all default interrupt-in endpoint as above.
+ * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature.
+ */
+#define USB_CFG_EP3_NUMBER 3
+/* If the so-called endpoint 3 is used, it can now be configured to any other
+ * endpoint number (except 0) with this macro. Default if undefined is 3.
+ */
+/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */
+/* The above macro defines the startup condition for data toggling on the
+ * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1.
+ * Since the token is toggled BEFORE sending any data, the first packet is
+ * sent with the oposite value of this configuration!
*/
#define USB_CFG_IMPLEMENT_HALT 0
/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature
* it is required by the standard. We have made it a config option because it
* bloats the code considerably.
*/
-#define USB_CFG_INTR_POLL_INTERVAL 20
+#define USB_CFG_SUPPRESS_INTR_CODE 0
+/* Define this to 1 if you want to declare interrupt-in endpoints, but don't
+ * want to send any data over them. If this macro is defined to 1, functions
+ * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if
+ * you need the interrupt-in endpoints in order to comply to an interface
+ * (e.g. HID), but never want to send any data. This option saves a couple
+ * of bytes in flash memory and the transmit buffers in RAM.
+ */
+#define USB_CFG_INTR_POLL_INTERVAL 10
/* If you compile a version with endpoint 1 (interrupt-in), this is the poll
* interval. The value is in milliseconds and must not be less than 10 ms for
* low speed devices.
* usbFunctionSetup(). This saves a couple of bytes.
*/
#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0
-/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoint 1.
+/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints.
* You must implement the function usbFunctionWriteOut() which receives all
- * interrupt/bulk data sent to endpoint 1.
+ * interrupt/bulk data sent to any endpoint other than 0. The endpoint number
+ * can be found in 'usbRxToken'.
*/
#define USB_CFG_HAVE_FLOWCONTROL 0
/* Define this to 1 if you want flowcontrol over USB data. See the definition
* of the macros usbDisableAllRequests() and usbEnableAllRequests() in
* usbdrv.h.
*/
+#define USB_CFG_LONG_TRANSFERS 0
+/* Define this to 1 if you want to send/receive blocks of more than 254 bytes
+ * in a single control-in or control-out transfer. Note that the capability
+ * for long transfers increases the driver size.
+ */
+/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */
+/* This macro is a hook if you want to do unconventional things. If it is
+ * defined, it's inserted at the beginning of received message processing.
+ * If you eat the received message and don't want default processing to
+ * proceed, do a return after doing your things. One possible application
+ * (besides debugging) is to flash a status LED on each packet.
+ */
+/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */
+/* This macro is a hook if you need to know when an USB RESET occurs. It has
+ * one parameter which distinguishes between the start of RESET state and its
+ * end.
+ */
+/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */
+/* This macro (if defined) is executed when a USB SET_ADDRESS request was
+ * received.
+ */
+#define USB_COUNT_SOF 0
+/* define this macro to 1 if you need the global variable "usbSofCount" which
+ * counts SOF packets. This feature requires that the hardware interrupt is
+ * connected to D- instead of D+.
+ */
+/* #ifdef __ASSEMBLER__
+ * macro myAssemblerMacro
+ * in YL, TCNT0
+ * sts timer0Snapshot, YL
+ * endm
+ * #endif
+ * #define USB_SOF_HOOK myAssemblerMacro
+ * This macro (if defined) is executed in the assembler module when a
+ * Start Of Frame condition is detected. It is recommended to define it to
+ * the name of an assembler macro which is defined here as well so that more
+ * than one assembler instruction can be used. The macro may use the register
+ * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages
+ * immediately after an SOF pulse may be lost and must be retried by the host.
+ * What can you do with this hook? Since the SOF signal occurs exactly every
+ * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in
+ * designs running on the internal RC oscillator.
+ * Please note that Start Of Frame detection works only if D- is wired to the
+ * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES!
+ */
+#define USB_CFG_CHECK_DATA_TOGGLING 0
+/* define this macro to 1 if you want to filter out duplicate data packets
+ * sent by the host. Duplicates occur only as a consequence of communication
+ * errors, when the host does not receive an ACK. Please note that you need to
+ * implement the filtering yourself in usbFunctionWriteOut() and
+ * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable
+ * for each control- and out-endpoint to check for duplicate packets.
+ */
+#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0
+/* define this macro to 1 if you want the function usbMeasureFrameLength()
+ * compiled in. This function can be used to calibrate the AVR's RC oscillator.
+ */
/* -------------------------- Device Description --------------------------- */
#define USB_CFG_VENDOR_ID 0xc0, 0x16
/* USB vendor ID for the device, low byte first. If you have registered your
- * own Vendor ID, define it here. Otherwise you use obdev's free shared
- * VID/PID pair. Be sure to read USBID-License.txt for rules!
- * This template uses obdev's shared VID/PID pair for HIDs: 0x16c0/0x5df.
- * Use this VID/PID pair ONLY if you understand the implications!
+ * own Vendor ID, define it here. Otherwise you use one of obdev's free shared
+ * VID/PID pairs. Be sure to read USBID-License.txt for rules!
+ * + This template uses obdev's shared VID/PID pair: 0x16c0/0x5dc.
+ * + Use this VID/PID pair ONLY if you understand the implications!
*/
-#define USB_CFG_DEVICE_ID 0xdf, 0x05
+#define USB_CFG_DEVICE_ID 0xdc, 0x05
/* This is the ID of the product, low byte first. It is interpreted in the
* scope of the vendor ID. If you have registered your own VID with usb.org
* or if you have licensed a PID from somebody else, define it here. Otherwise
* you use obdev's free shared VID/PID pair. Be sure to read the rules in
* USBID-License.txt!
- * This template uses obdev's shared VID/PID pair for HIDs: 0x16c0/0x5df.
- * Use this VID/PID pair ONLY if you understand the implications!
+ * + This template uses obdev's shared VID/PID pair: 0x16c0/0x5dc.
+ * + Use this VID/PID pair ONLY if you understand the implications!
*/
#define USB_CFG_DEVICE_VERSION 0x00, 0x01
/* Version number of the device: Minor number first, then major number.
*/
-#define USB_CFG_VENDOR_NAME 'w', 'w', 'w', '.', 'o', 'b', 'd', 'e', 'v', '.', 'a', 't'
-#define USB_CFG_VENDOR_NAME_LEN 12
+#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't'
+#define USB_CFG_VENDOR_NAME_LEN 8
/* These two values define the vendor name returned by the USB device. The name
* must be given as a list of characters under single quotes. The characters
* are interpreted as Unicode (UTF-16) entities.
* to fine tune control over USB descriptors such as the string descriptor
* for the serial number.
*/
-#define USB_CFG_DEVICE_CLASS 0
+#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */
#define USB_CFG_DEVICE_SUBCLASS 0
/* See USB specification if you want to conform to an existing device class.
+ * Class 0xff is "vendor specific".
*/
-#define USB_CFG_INTERFACE_CLASS 3 /* HID */
+#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */
#define USB_CFG_INTERFACE_SUBCLASS 0
#define USB_CFG_INTERFACE_PROTOCOL 0
/* See USB specification if you want to conform to an existing device class or
- * protocol.
- * This template defines a HID class device. If you implement a vendor class
- * device, set USB_CFG_INTERFACE_CLASS to 0 and USB_CFG_DEVICE_CLASS to 0xff.
+ * protocol. The following classes must be set at interface level:
+ * HID class is 3, no subclass and protocol required (but may be useful!)
+ * CDC class is 2, use subclass 2 and protocol 1 for ACM
*/
-#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 /* total length of report descriptor */
+/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */
/* Define this to the length of the HID report descriptor, if you implement
* an HID device. Otherwise don't define it or define it to 0.
- * Since this template defines a HID device, it must also specify a HID
- * report descriptor length. You must add a PROGMEM character array named
+ * If you use this define, you must add a PROGMEM character array named
* "usbHidReportDescriptor" to your code which contains the report descriptor.
* Don't forget to keep the array and this define in sync!
*/
* no properties are defined or if they are 0, the default descriptor is used.
* Possible properties are:
* + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched
- * at runtime via usbFunctionDescriptor().
+ * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is
+ * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if
+ * you want RAM pointers.
* + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found
* in static memory is in RAM, not in flash memory.
* + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash),
* USB_CFG_DESCR_PROPS_HID_REPORT
* USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver)
*
+ * Note about string descriptors: String descriptors are not just strings, they
+ * are Unicode strings prefixed with a 2 byte header. Example:
+ * int serialNumberDescriptor[] = {
+ * USB_STRING_DESCRIPTOR_HEADER(6),
+ * 'S', 'e', 'r', 'i', 'a', 'l'
+ * };
*/
#define USB_CFG_DESCR_PROPS_DEVICE 0
/* #define USB_INTR_ENABLE_BIT INT0 */
/* #define USB_INTR_PENDING GIFR */
/* #define USB_INTR_PENDING_BIT INTF0 */
+/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */
#endif /* __usbconfig_h_included__ */
* Creation Date: 2004-12-29
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: usbdrv.c 350 2007-06-13 11:43:16Z cs $
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrv.c 692 2008-11-07 15:07:40Z cs $
*/
-#include "iarcompat.h"
-#ifndef __IAR_SYSTEMS_ICC__
-# include <avr/io.h>
-# include <avr/pgmspace.h>
-#endif
+#include "usbportability.h"
#include "usbdrv.h"
#include "oddebug.h"
documentation of the entire driver.
*/
-#ifndef IAR_SECTION
-#define IAR_SECTION(arg)
-#define __no_init
-#endif
-/* The macro IAR_SECTION is a hack to allow IAR-cc compatibility. On gcc, it
- * is defined to nothing. __no_init is required on IAR.
- */
-
/* ------------------------------------------------------------------------- */
/* raw USB registers / interface to assembler code: */
uchar usbNewDeviceAddr; /* device ID which should be set after status phase */
uchar usbConfiguration; /* currently selected configuration. Administered by driver, but not used */
volatile schar usbRxLen; /* = 0; number of bytes in usbRxBuf; 0 means free, -1 for flow control */
-uchar usbCurrentTok; /* last token received, if more than 1 rx endpoint: MSb=endpoint */
-uchar usbRxToken; /* token for data we received; if more than 1 rx endpoint: MSb=endpoint */
-uchar usbMsgLen = 0xff; /* remaining number of bytes, no msg to send if -1 (see usbMsgPtr) */
+uchar usbCurrentTok; /* last token received or endpoint number for last OUT token if != 0 */
+uchar usbRxToken; /* token for data we received; or endpont number for last OUT */
volatile uchar usbTxLen = USBPID_NAK; /* number of bytes to transmit with next IN token or handshake token */
uchar usbTxBuf[USB_BUFSIZE];/* data to transmit with next IN, free if usbTxLen contains handshake token */
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
-volatile uchar usbTxLen1 = USBPID_NAK; /* TX count for endpoint 1 */
-uchar usbTxBuf1[USB_BUFSIZE]; /* TX data for endpoint 1 */
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-volatile uchar usbTxLen3 = USBPID_NAK; /* TX count for endpoint 1 */
-uchar usbTxBuf3[USB_BUFSIZE]; /* TX data for endpoint 1 */
+#if USB_COUNT_SOF
+volatile uchar usbSofCount; /* incremented by assembler module every SOF */
+#endif
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+usbTxStatus_t usbTxStatus1;
+# if USB_CFG_HAVE_INTRIN_ENDPOINT3
+usbTxStatus_t usbTxStatus3;
+# endif
#endif
+#if USB_CFG_CHECK_DATA_TOGGLING
+uchar usbCurrentDataToken;/* when we check data toggling to ignore duplicate packets */
#endif
/* USB status registers / not shared with asm code */
-uchar *usbMsgPtr; /* data to transmit next -- ROM or RAM address */
-static uchar usbMsgFlags; /* flag values see below */
+uchar *usbMsgPtr; /* data to transmit next -- ROM or RAM address */
+static usbMsgLen_t usbMsgLen = USB_NO_MSG; /* remaining number of bytes */
+static uchar usbMsgFlags; /* flag values see below */
-#define USB_FLG_TX_PACKET (1<<0)
-/* Leave free 6 bits after TX_PACKET. This way we can increment usbMsgFlags to toggle TX_PACKET */
#define USB_FLG_MSGPTR_IS_ROM (1<<6)
-#define USB_FLG_USE_DEFAULT_RW (1<<7)
+#define USB_FLG_USE_USER_RW (1<<7)
/*
optimizing hints:
- do not post/pre inc/dec integer values in operations
-- assign value of PRG_RDB() to register variables and don't use side effects in arg
+- assign value of USB_READ_FLASH() to register variables and don't use side effects in arg
- use narrow scope for variables which should be in X/Y/Z register
- assign char sized expressions to variables to force 8 bit arithmetics
*/
-/* ------------------------------------------------------------------------- */
+/* -------------------------- String Descriptors --------------------------- */
#if USB_CFG_DESCR_PROPS_STRINGS == 0
#endif /* USB_CFG_DESCR_PROPS_STRINGS == 0 */
+/* --------------------------- Device Descriptor --------------------------- */
+
#if USB_CFG_DESCR_PROPS_DEVICE == 0
#undef USB_CFG_DESCR_PROPS_DEVICE
#define USB_CFG_DESCR_PROPS_DEVICE sizeof(usbDescriptorDevice)
USB_CFG_DEVICE_SUBCLASS,
0, /* protocol */
8, /* max packet size */
- USB_CFG_VENDOR_ID, /* 2 bytes */
- USB_CFG_DEVICE_ID, /* 2 bytes */
+ /* the following two casts affect the first byte of the constant only, but
+ * that's sufficient to avoid a warning with the default values.
+ */
+ (char)USB_CFG_VENDOR_ID,/* 2 bytes */
+ (char)USB_CFG_DEVICE_ID,/* 2 bytes */
USB_CFG_DEVICE_VERSION, /* 2 bytes */
USB_CFG_DESCR_PROPS_STRING_VENDOR != 0 ? 1 : 0, /* manufacturer string index */
USB_CFG_DESCR_PROPS_STRING_PRODUCT != 0 ? 2 : 0, /* product string index */
};
#endif
+/* ----------------------- Configuration Descriptor ------------------------ */
+
#if USB_CFG_DESCR_PROPS_HID_REPORT != 0 && USB_CFG_DESCR_PROPS_HID == 0
#undef USB_CFG_DESCR_PROPS_HID
#define USB_CFG_DESCR_PROPS_HID 9 /* length of HID descriptor in config descriptor below */
PROGMEM char usbDescriptorConfiguration[] = { /* USB configuration descriptor */
9, /* sizeof(usbDescriptorConfiguration): length of descriptor in bytes */
USBDESCR_CONFIG, /* descriptor type */
- 18 + 7 * USB_CFG_HAVE_INTRIN_ENDPOINT + (USB_CFG_DESCR_PROPS_HID & 0xff), 0,
+ 18 + 7 * USB_CFG_HAVE_INTRIN_ENDPOINT + 7 * USB_CFG_HAVE_INTRIN_ENDPOINT3 +
+ (USB_CFG_DESCR_PROPS_HID & 0xff), 0,
/* total length of data returned (including inlined descriptors) */
1, /* number of interfaces in this configuration */
1, /* index of this configuration */
0, /* configuration name string index */
#if USB_CFG_IS_SELF_POWERED
- USBATTR_SELFPOWER, /* attributes */
+ USBATTR_SELFPOWER, /* attributes */
#else
- USBATTR_BUSPOWER, /* attributes */
+ (char)USBATTR_BUSPOWER, /* attributes */
#endif
USB_CFG_MAX_BUS_POWER/2, /* max USB current in 2mA units */
/* interface descriptor follows inline: */
USBDESCR_INTERFACE, /* descriptor type */
0, /* index of this interface */
0, /* alternate setting for this interface */
- USB_CFG_HAVE_INTRIN_ENDPOINT, /* endpoints excl 0: number of endpoint descriptors to follow */
+ USB_CFG_HAVE_INTRIN_ENDPOINT + USB_CFG_HAVE_INTRIN_ENDPOINT3, /* endpoints excl 0: number of endpoint descriptors to follow */
USB_CFG_INTERFACE_CLASS,
USB_CFG_INTERFACE_SUBCLASS,
USB_CFG_INTERFACE_PROTOCOL,
#if USB_CFG_HAVE_INTRIN_ENDPOINT /* endpoint descriptor for endpoint 1 */
7, /* sizeof(usbDescrEndpoint) */
USBDESCR_ENDPOINT, /* descriptor type = endpoint */
- 0x81, /* IN endpoint number 1 */
+ (char)0x81, /* IN endpoint number 1 */
+ 0x03, /* attrib: Interrupt endpoint */
+ 8, 0, /* maximum packet size */
+ USB_CFG_INTR_POLL_INTERVAL, /* in ms */
+#endif
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3 /* endpoint descriptor for endpoint 3 */
+ 7, /* sizeof(usbDescrEndpoint) */
+ USBDESCR_ENDPOINT, /* descriptor type = endpoint */
+ (char)0x83, /* IN endpoint number 1 */
0x03, /* attrib: Interrupt endpoint */
8, 0, /* maximum packet size */
USB_CFG_INTR_POLL_INTERVAL, /* in ms */
};
#endif
-/* We don't use prog_int or prog_int16_t for compatibility with various libc
- * versions. Here's an other compatibility hack:
- */
-#ifndef PRG_RDB
-#define PRG_RDB(addr) pgm_read_byte(addr)
-#endif
-
-typedef union{
- unsigned word;
- uchar *ptr;
- uchar bytes[2];
-}converter_t;
-/* We use this union to do type conversions. This is better optimized than
- * type casts in gcc 3.4.3 and much better than using bit shifts to build
- * ints from chars. Byte ordering is not a problem on an 8 bit platform.
- */
+/* ------------------------------------------------------------------------- */
+
+static inline void usbResetDataToggling(void)
+{
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+ USB_SET_DATATOKEN1(USB_INITIAL_DATATOKEN); /* reset data toggling for interrupt endpoint */
+# if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ USB_SET_DATATOKEN3(USB_INITIAL_DATATOKEN); /* reset data toggling for interrupt endpoint */
+# endif
+#endif
+}
+
+static inline void usbResetStall(void)
+{
+#if USB_CFG_IMPLEMENT_HALT && USB_CFG_HAVE_INTRIN_ENDPOINT
+ usbTxLen1 = USBPID_NAK;
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ usbTxLen3 = USBPID_NAK;
+#endif
+#endif
+}
/* ------------------------------------------------------------------------- */
+#if !USB_CFG_SUPPRESS_INTR_CODE
#if USB_CFG_HAVE_INTRIN_ENDPOINT
-USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len)
+static void usbGenericSetInterrupt(uchar *data, uchar len, usbTxStatus_t *txStatus)
{
-uchar *p, i;
+uchar *p;
+char i;
#if USB_CFG_IMPLEMENT_HALT
if(usbTxLen1 == USBPID_STALL)
return;
#endif
-#if 0 /* No runtime checks! Caller is responsible for valid data! */
- if(len > 8) /* interrupt transfers are limited to 8 bytes */
- len = 8;
-#endif
- if(usbTxLen1 & 0x10){ /* packet buffer was empty */
- usbTxBuf1[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
+ if(txStatus->len & 0x10){ /* packet buffer was empty */
+ txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
}else{
- usbTxLen1 = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */
+ txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */
}
- p = usbTxBuf1 + 1;
- for(i=len;i--;)
+ p = txStatus->buffer + 1;
+ i = len;
+ do{ /* if len == 0, we still copy 1 byte, but that's no problem */
*p++ = *data++;
- usbCrc16Append(&usbTxBuf1[1], len);
- usbTxLen1 = len + 4; /* len must be given including sync byte */
- DBG2(0x21, usbTxBuf1, len + 3);
+ }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */
+ usbCrc16Append(&txStatus->buffer[1], len);
+ txStatus->len = len + 4; /* len must be given including sync byte */
+ DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3);
+}
+
+USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len)
+{
+ usbGenericSetInterrupt(data, len, &usbTxStatus1);
}
#endif
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len)
{
-uchar *p, i;
-
- if(usbTxLen3 & 0x10){ /* packet buffer was empty */
- usbTxBuf3[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
- }else{
- usbTxLen3 = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */
- }
- p = usbTxBuf3 + 1;
- for(i=len;i--;)
- *p++ = *data++;
- usbCrc16Append(&usbTxBuf3[1], len);
- usbTxLen3 = len + 4; /* len must be given including sync byte */
- DBG2(0x23, usbTxBuf3, len + 3);
+ usbGenericSetInterrupt(data, len, &usbTxStatus3);
}
#endif
+#endif /* USB_CFG_SUPPRESS_INTR_CODE */
+/* ------------------ utilities for code following below ------------------- */
-static uchar usbRead(uchar *data, uchar len)
-{
-#if USB_CFG_IMPLEMENT_FN_READ
- if(usbMsgFlags & USB_FLG_USE_DEFAULT_RW){
-#endif
- uchar i = len, *r = usbMsgPtr;
- if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */
- while(i--){
- uchar c = PRG_RDB(r); /* assign to char size variable to enforce byte ops */
- *data++ = c;
- r++;
- }
- }else{ /* RAM data */
- while(i--)
- *data++ = *r++;
- }
- usbMsgPtr = r;
- return len;
-#if USB_CFG_IMPLEMENT_FN_READ
- }else{
- if(len != 0) /* don't bother app with 0 sized reads */
- return usbFunctionRead(data, len);
- return 0;
- }
+/* Use defines for the switch statement so that we can choose between an
+ * if()else if() and a switch/case based implementation. switch() is more
+ * efficient for a LARGE set of sequential choices, if() is better in all other
+ * cases.
+ */
+#if USB_CFG_USE_SWITCH_STATEMENT
+# define SWITCH_START(cmd) switch(cmd){{
+# define SWITCH_CASE(value) }break; case (value):{
+# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{
+# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{
+# define SWITCH_DEFAULT }break; default:{
+# define SWITCH_END }}
+#else
+# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){
+# define SWITCH_CASE(value) }else if(_cmd == (value)){
+# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){
+# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){
+# define SWITCH_DEFAULT }else{
+# define SWITCH_END }}
#endif
-}
+#ifndef USB_RX_USER_HOOK
+#define USB_RX_USER_HOOK(data, len)
+#endif
+#ifndef USB_SET_ADDRESS_HOOK
+#define USB_SET_ADDRESS_HOOK()
+#endif
+
+/* ------------------------------------------------------------------------- */
+/* We use if() instead of #if in the macro below because #if can't be used
+ * in macros and the compiler optimizes constant conditions anyway.
+ * This may cause problems with undefined symbols if compiled without
+ * optimizing!
+ */
#define GET_DESCRIPTOR(cfgProp, staticName) \
if(cfgProp){ \
if((cfgProp) & USB_PROP_IS_RAM) \
- flags &= ~USB_FLG_MSGPTR_IS_ROM; \
+ flags = 0; \
if((cfgProp) & USB_PROP_IS_DYNAMIC){ \
- replyLen = usbFunctionDescriptor(rq); \
+ len = usbFunctionDescriptor(rq); \
}else{ \
- replyData = (uchar *)(staticName); \
- SET_REPLY_LEN((cfgProp) & 0xff); \
+ len = USB_PROP_LENGTH(cfgProp); \
+ usbMsgPtr = (uchar *)(staticName); \
} \
}
-/* We use if() instead of #if in the macro above because #if can't be used
- * in macros and the compiler optimizes constant conditions anyway.
+
+/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used
+ * internally for all types of descriptors.
+ */
+static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq)
+{
+usbMsgLen_t len = 0;
+uchar flags = USB_FLG_MSGPTR_IS_ROM;
+
+ SWITCH_START(rq->wValue.bytes[1])
+ SWITCH_CASE(USBDESCR_DEVICE) /* 1 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice)
+ SWITCH_CASE(USBDESCR_CONFIG) /* 2 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration)
+ SWITCH_CASE(USBDESCR_STRING) /* 3 */
+#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC
+ if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM)
+ flags = 0;
+ len = usbFunctionDescriptor(rq);
+#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
+ SWITCH_START(rq->wValue.bytes[0])
+ SWITCH_CASE(0)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0)
+ SWITCH_CASE(1)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor)
+ SWITCH_CASE(2)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice)
+ SWITCH_CASE(3)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber)
+ SWITCH_DEFAULT
+ if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
+ len = usbFunctionDescriptor(rq);
+ }
+ SWITCH_END
+#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
+#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */
+ SWITCH_CASE(USBDESCR_HID) /* 0x21 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18)
+ SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport)
+#endif
+ SWITCH_DEFAULT
+ if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
+ len = usbFunctionDescriptor(rq);
+ }
+ SWITCH_END
+ usbMsgFlags = flags;
+ return len;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for
+ * standard requests instead of class and custom requests.
*/
+static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq)
+{
+uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */
+uchar value = rq->wValue.bytes[0];
+#if USB_CFG_IMPLEMENT_HALT
+uchar index = rq->wIndex.bytes[0];
+#endif
+
+ dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */
+ SWITCH_START(rq->bRequest)
+ SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */
+ uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */
+ if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE)
+ dataPtr[0] = USB_CFG_IS_SELF_POWERED;
+#if USB_CFG_IMPLEMENT_HALT
+ if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */
+ dataPtr[0] = usbTxLen1 == USBPID_STALL;
+#endif
+ dataPtr[1] = 0;
+ len = 2;
+#if USB_CFG_IMPLEMENT_HALT
+ SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */
+ if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */
+ usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL;
+ usbResetDataToggling();
+ }
+#endif
+ SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */
+ usbNewDeviceAddr = value;
+ USB_SET_ADDRESS_HOOK();
+ SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */
+ len = usbDriverDescriptor(rq);
+ goto skipMsgPtrAssignment;
+ SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */
+ dataPtr = &usbConfiguration; /* send current configuration value */
+ len = 1;
+ SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */
+ usbConfiguration = value;
+ usbResetStall();
+ SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */
+ len = 1;
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+ SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */
+ usbResetDataToggling();
+ usbResetStall();
+#endif
+ SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */
+ /* Should we add an optional hook here? */
+ SWITCH_END
+ usbMsgPtr = dataPtr;
+skipMsgPtrAssignment:
+ return len;
+}
+/* ------------------------------------------------------------------------- */
-/* Don't make this function static to avoid inlining.
- * The entire function would become too large and exceed the range of
- * relative jumps.
- * 2006-02-25: Either gcc 3.4.3 is better than the gcc used when the comment
- * above was written, or other parts of the code have changed. We now get
- * better results with an inlined function. Test condition: PowerSwitch code.
+/* usbProcessRx() is called for every message received by the interrupt
+ * routine. It distinguishes between SETUP and DATA packets and processes
+ * them accordingly.
*/
-static void usbProcessRx(uchar *data, uchar len)
+static inline void usbProcessRx(uchar *data, uchar len)
{
usbRequest_t *rq = (void *)data;
-uchar replyLen = 0, flags = USB_FLG_USE_DEFAULT_RW;
-/* We use if() cascades because the compare is done byte-wise while switch()
- * is int-based. The if() cascades are therefore more efficient.
- */
+
/* usbRxToken can be:
- * 0x2d 00101101 (USBPID_SETUP for endpoint 0)
- * 0xe1 11100001 (USBPID_OUT for endpoint 0)
- * 0xff 11111111 (USBPID_OUT for endpoint 1)
+ * 0x2d 00101101 (USBPID_SETUP for setup data)
+ * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer)
+ * 0...0x0f for OUT on endpoint X
*/
- DBG2(0x10 + ((usbRxToken >> 1) & 3), data, len); /* SETUP0=12; OUT0=10; OUT1=13 */
+ DBG2(0x10 + (usbRxToken & 0xf), data, len); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */
+ USB_RX_USER_HOOK(data, len)
#if USB_CFG_IMPLEMENT_FN_WRITEOUT
- if(usbRxToken == 0xff){
+ if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */
usbFunctionWriteOut(data, len);
- return; /* no reply expected, hence no usbMsgPtr, usbMsgFlags, usbMsgLen set */
+ return;
}
#endif
if(usbRxToken == (uchar)USBPID_SETUP){
- usbTxLen = USBPID_NAK; /* abort pending transmit */
- if(len == 8){ /* Setup size must be always 8 bytes. Ignore otherwise. */
- uchar type = rq->bmRequestType & USBRQ_TYPE_MASK;
- if(type == USBRQ_TYPE_STANDARD){
- #define SET_REPLY_LEN(len) replyLen = (len); usbMsgPtr = replyData
- /* This macro ensures that replyLen and usbMsgPtr are always set in the same way.
- * That allows optimization of common code in if() branches */
- uchar *replyData = usbTxBuf + 9; /* there is 3 bytes free space at the end of the buffer */
- replyData[0] = 0; /* common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */
- if(rq->bRequest == USBRQ_GET_STATUS){ /* 0 */
- uchar __attribute__((__unused__)) recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */
-#if USB_CFG_IS_SELF_POWERED
- if(recipient == USBRQ_RCPT_DEVICE)
- replyData[0] = USB_CFG_IS_SELF_POWERED;
-#endif
-#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_IMPLEMENT_HALT
- if(recipient == USBRQ_RCPT_ENDPOINT && rq->wIndex.bytes[0] == 0x81) /* request status for endpoint 1 */
- replyData[0] = usbTxLen1 == USBPID_STALL;
-#endif
- replyData[1] = 0;
- SET_REPLY_LEN(2);
- }else if(rq->bRequest == USBRQ_SET_ADDRESS){ /* 5 */
- usbNewDeviceAddr = rq->wValue.bytes[0];
- }else if(rq->bRequest == USBRQ_GET_DESCRIPTOR){ /* 6 */
- flags = USB_FLG_MSGPTR_IS_ROM | USB_FLG_USE_DEFAULT_RW;
- if(rq->wValue.bytes[1] == USBDESCR_DEVICE){ /* 1 */
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice)
- }else if(rq->wValue.bytes[1] == USBDESCR_CONFIG){ /* 2 */
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration)
- }else if(rq->wValue.bytes[1] == USBDESCR_STRING){ /* 3 */
-#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC
- if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM)
- flags &= ~USB_FLG_MSGPTR_IS_ROM;
- replyLen = usbFunctionDescriptor(rq);
-#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
- if(rq->wValue.bytes[0] == 0){ /* descriptor index */
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0)
- }else if(rq->wValue.bytes[0] == 1){
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor)
- }else if(rq->wValue.bytes[0] == 2){
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice)
- }else if(rq->wValue.bytes[0] == 3){
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber)
- }else if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
- replyLen = usbFunctionDescriptor(rq);
- }
-#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
- }else if(rq->wValue.bytes[1] == USBDESCR_HID){ /* 0x21 */
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18)
- }else if(rq->wValue.bytes[1] == USBDESCR_HID_REPORT){ /* 0x22 */
- GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport)
- }else if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
- replyLen = usbFunctionDescriptor(rq);
- }
- }else if(rq->bRequest == USBRQ_GET_CONFIGURATION){ /* 8 */
- replyData = &usbConfiguration; /* send current configuration value */
- SET_REPLY_LEN(1);
- }else if(rq->bRequest == USBRQ_SET_CONFIGURATION){ /* 9 */
- usbConfiguration = rq->wValue.bytes[0];
-#if USB_CFG_IMPLEMENT_HALT
- usbTxLen1 = USBPID_NAK;
-#endif
- }else if(rq->bRequest == USBRQ_GET_INTERFACE){ /* 10 */
- SET_REPLY_LEN(1);
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
- }else if(rq->bRequest == USBRQ_SET_INTERFACE){ /* 11 */
- USB_SET_DATATOKEN1(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
-# if USB_CFG_HAVE_INTRIN_ENDPOINT3
- USB_SET_DATATOKEN3(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
-# endif
-# if USB_CFG_IMPLEMENT_HALT
- usbTxLen1 = USBPID_NAK;
- }else if(rq->bRequest == USBRQ_CLEAR_FEATURE || rq->bRequest == USBRQ_SET_FEATURE){ /* 1|3 */
- if(rq->wValue.bytes[0] == 0 && rq->wIndex.bytes[0] == 0x81){ /* feature 0 == HALT for endpoint == 1 */
- usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL;
- USB_SET_DATATOKEN1(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
-# if USB_CFG_HAVE_INTRIN_ENDPOINT3
- USB_SET_DATATOKEN3(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
-# endif
- }
-# endif
-#endif
+ if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */
+ return;
+ usbMsgLen_t replyLen;
+ usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */
+ usbTxLen = USBPID_NAK; /* abort pending transmit */
+ usbMsgFlags = 0;
+ uchar type = rq->bmRequestType & USBRQ_TYPE_MASK;
+ if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */
+ replyLen = usbFunctionSetup(data);
+ }else{
+ replyLen = usbDriverSetup(rq);
+ }
+#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE
+ if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */
+ /* do some conditioning on replyLen, but on IN transfers only */
+ if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){
+ if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */
+ replyLen = rq->wLength.bytes[0];
}else{
- /* the following requests can be ignored, send default reply */
- /* 1: CLEAR_FEATURE, 3: SET_FEATURE, 7: SET_DESCRIPTOR */
- /* 12: SYNCH_FRAME */
+ replyLen = rq->wLength.word;
}
- #undef SET_REPLY_LEN
- }else{ /* not a standard request -- must be vendor or class request */
- replyLen = usbFunctionSetup(data);
}
-#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE
- if(replyLen == 0xff){ /* use user-supplied read/write function */
- if((rq->bmRequestType & USBRQ_DIR_MASK) == USBRQ_DIR_DEVICE_TO_HOST){
- replyLen = rq->wLength.bytes[0]; /* IN transfers only */
- }
- flags &= ~USB_FLG_USE_DEFAULT_RW; /* we have no valid msg, use user supplied read/write functions */
- }else /* The 'else' prevents that we limit a replyLen of 0xff to the maximum transfer len. */
+ usbMsgFlags = USB_FLG_USE_USER_RW;
+ }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */
#endif
- if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */
+ if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */
+ if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */
replyLen = rq->wLength.bytes[0];
+ }else{
+ if(replyLen > rq->wLength.word) /* limit length to max */
+ replyLen = rq->wLength.word;
}
- /* make sure that data packets which are sent as ACK to an OUT transfer are always zero sized */
- }else{ /* DATA packet from out request */
+ usbMsgLen = replyLen;
+ }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */
#if USB_CFG_IMPLEMENT_FN_WRITE
- if(!(usbMsgFlags & USB_FLG_USE_DEFAULT_RW)){
+ if(usbMsgFlags & USB_FLG_USE_USER_RW){
uchar rval = usbFunctionWrite(data, len);
- replyLen = 0xff;
- if(rval == 0xff){ /* an error occurred */
- usbMsgLen = 0xff; /* cancel potentially pending data packet for ACK */
+ if(rval == 0xff){ /* an error occurred */
usbTxLen = USBPID_STALL;
}else if(rval != 0){ /* This was the final package */
- replyLen = 0; /* answer with a zero-sized data packet */
+ usbMsgLen = 0; /* answer with a zero-sized data packet */
}
- flags = 0; /* start with a DATA1 package, stay with user supplied write() function */
}
#endif
}
- usbMsgFlags = flags;
- usbMsgLen = replyLen;
}
/* ------------------------------------------------------------------------- */
-static void usbBuildTxBlock(void)
+/* This function is similar to usbFunctionRead(), but it's also called for
+ * data handled automatically by the driver (e.g. descriptor reads).
+ */
+static uchar usbDeviceRead(uchar *data, uchar len)
{
-uchar wantLen, len, txLen, token;
+ if(len > 0){ /* don't bother app with 0 sized reads */
+#if USB_CFG_IMPLEMENT_FN_READ
+ if(usbMsgFlags & USB_FLG_USE_USER_RW){
+ len = usbFunctionRead(data, len);
+ }else
+#endif
+ {
+ uchar i = len, *r = usbMsgPtr;
+ if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */
+ do{
+ uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */
+ *data++ = c;
+ r++;
+ }while(--i);
+ }else{ /* RAM data */
+ do{
+ *data++ = *r++;
+ }while(--i);
+ }
+ usbMsgPtr = r;
+ }
+ }
+ return len;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* usbBuildTxBlock() is called when we have data to transmit and the
+ * interrupt routine's transmit buffer is empty.
+ */
+static inline void usbBuildTxBlock(void)
+{
+usbMsgLen_t wantLen;
+uchar len;
wantLen = usbMsgLen;
if(wantLen > 8)
wantLen = 8;
usbMsgLen -= wantLen;
- token = USBPID_DATA1;
- if(usbMsgFlags & USB_FLG_TX_PACKET)
- token = USBPID_DATA0;
- usbMsgFlags++;
- len = usbRead(usbTxBuf + 1, wantLen);
+ usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */
+ len = usbDeviceRead(usbTxBuf + 1, wantLen);
if(len <= 8){ /* valid data packet */
usbCrc16Append(&usbTxBuf[1], len);
- txLen = len + 4; /* length including sync byte */
- if(len < 8) /* a partial package identifies end of message */
- usbMsgLen = 0xff;
+ len += 4; /* length including sync byte */
+ if(len < 12) /* a partial package identifies end of message */
+ usbMsgLen = USB_NO_MSG;
}else{
- txLen = USBPID_STALL; /* stall the endpoint */
- usbMsgLen = 0xff;
+ len = USBPID_STALL; /* stall the endpoint */
+ usbMsgLen = USB_NO_MSG;
}
- usbTxBuf[0] = token;
- usbTxLen = txLen;
- DBG2(0x20, usbTxBuf, txLen-1);
+ usbTxLen = len;
+ DBG2(0x20, usbTxBuf, len-1);
}
-static inline uchar isNotSE0(void)
+/* ------------------------------------------------------------------------- */
+
+static inline void usbHandleResetHook(uchar notResetState)
{
-uchar rval;
-/* We want to do
- * return (USBIN & USBMASK);
- * here, but the compiler does int-expansion acrobatics.
- * We can avoid this by assigning to a char-sized variable.
- */
- rval = USBIN & USBMASK;
- return rval;
+#ifdef USB_RESET_HOOK
+static uchar wasReset;
+uchar isReset = !notResetState;
+
+ if(wasReset != isReset){
+ USB_RESET_HOOK(isReset);
+ wasReset = isReset;
+ }
+#endif
}
/* ------------------------------------------------------------------------- */
schar len;
uchar i;
- if((len = usbRxLen) > 0){
+ len = usbRxLen - 3;
+ if(len >= 0){
/* We could check CRC16 here -- but ACK has already been sent anyway. If you
* need data integrity checks with this driver, check the CRC in your app
* code and report errors back to the host. Since the ACK was already sent,
* retries must be handled on application level.
* unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3);
*/
- usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len - 3);
+ usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len);
#if USB_CFG_HAVE_FLOWCONTROL
if(usbRxLen > 0) /* only mark as available if not inactivated */
usbRxLen = 0;
usbRxLen = 0; /* mark rx buffer as available */
#endif
}
- if(usbTxLen & 0x10){ /* transmit system idle */
- if(usbMsgLen != 0xff){ /* transmit data pending? */
+ if(usbTxLen & 0x10){ /* transmit system idle */
+ if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */
usbBuildTxBlock();
}
}
- for(i = 10; i > 0; i--){
- if(isNotSE0())
- break;
- }
- if(i == 0){ /* RESET condition, called multiple times during reset */
- usbNewDeviceAddr = 0;
- usbDeviceAddr = 0;
-#if USB_CFG_IMPLEMENT_HALT
- usbTxLen1 = USBPID_NAK;
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
- usbTxLen3 = USBPID_NAK;
-#endif
-#endif
- DBG1(0xff, 0, 0);
+ for(i = 20; i > 0; i--){
+ uchar usbLineStatus = USBIN & USBMASK;
+ if(usbLineStatus != 0) /* SE0 has ended */
+ goto isNotReset;
}
+ /* RESET condition, called multiple times during reset */
+ usbNewDeviceAddr = 0;
+ usbDeviceAddr = 0;
+ usbResetStall();
+ DBG1(0xff, 0, 0);
+isNotReset:
+ usbHandleResetHook(i);
}
/* ------------------------------------------------------------------------- */
USB_INTR_CFG &= ~(USB_INTR_CFG_CLR);
#endif
USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT);
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
- USB_SET_DATATOKEN1(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
-# if USB_CFG_HAVE_INTRIN_ENDPOINT3
- USB_SET_DATATOKEN3(USBPID_DATA0); /* reset data toggling for interrupt endpoint */
-# endif
+ usbResetDataToggling();
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+ usbTxLen1 = USBPID_NAK;
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ usbTxLen3 = USBPID_NAK;
+#endif
#endif
}
* Creation Date: 2004-12-29
* Tabsize: 4
* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: usbdrv.h 375 2007-07-07 12:01:52Z cs $
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrv.h 697 2008-11-26 17:24:43Z cs $
*/
#ifndef __usbdrv_h_included__
#define __usbdrv_h_included__
#include "usbconfig.h"
-#include "iarcompat.h"
+#include "usbportability.h"
/*
Hardware Prerequisites:
=======================
-USB lines D+ and D- MUST be wired to the same I/O port. D+ must (also) be
-connected to INT0. D- requires a pullup of 1.5k to +3.5V (and the device
-must be powered at 3.5V) to identify as low-speed USB device. A pullup of
-1M SHOULD be connected from D+ to +3.5V to prevent interference when no USB
-master is connected. We use D+ as interrupt source and not D- because it
-does not trigger on keep-alive and RESET states.
-
-As a compile time option, the 1.5k pullup resistor on D- can be made
+USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+
+triggers the interrupt (best achieved by using INT0 for D+), but it is also
+possible to trigger the interrupt from D-. If D- is used, interrupts are also
+triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the
+device must be powered at 3.5V) to identify as low-speed USB device. A
+pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent
+interference when no USB master is connected. If you use Zener diodes to limit
+the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up.
+We use D+ as interrupt source and not D- because it does not trigger on
+keep-alive and RESET states. If you want to count keep-alive events with
+USB_COUNT_SOF, you MUST use D- as an interrupt source.
+
+As a compile time option, the 1.5k pull-up resistor on D- can be made
switchable to allow the device to disconnect at will. See the definition of
usbDeviceConnect() and usbDeviceDisconnect() further down in this file.
Please adapt the values in usbconfig.h according to your hardware!
-The device MUST be clocked at exactly 12 MHz or 16 MHz or at 16.5 MHz +/- 1%.
-See usbconfig-prototype.h for details.
+The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz
+or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details.
Limitations:
requires detection of asymmetric states at high bit rate for SE0 detection.
Number of endpoints:
-The driver supports up to four endpoints: One control endpoint (endpoint 0),
-two interrupt-in (or bulk-in) endpoints (endpoint 1 and 3) and one
-interrupt-out (or bulk-out) endpoint (endpoint 1). Please note that the USB
-standard forbids bulk endpoints for low speed devices! Most operating systems
-allow them anyway, but the AVR will spend 90% of the CPU time in the USB
-interrupt polling for bulk data.
-By default, only the control endpoint 0 is enabled. To get the other endpoints,
-define USB_CFG_HAVE_INTRIN_ENDPOINT, USB_CFG_HAVE_INTRIN_ENDPOINT3 and/or
-USB_CFG_IMPLEMENT_FN_WRITEOUT respectively (see usbconfig-prototype.h for
-details).
+The driver supports the following endpoints:
+
+- Endpoint 0, the default control endpoint.
+- Any number of interrupt- or bulk-out endpoints. The data is sent to
+ usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined
+ to 1 to activate this feature. The endpoint number can be found in the
+ global variable 'usbRxToken'.
+- One default interrupt- or bulk-in endpoint. This endpoint is used for
+ interrupt- or bulk-in transfers which are not handled by any other endpoint.
+ You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this
+ feature and call usbSetInterrupt() to send interrupt/bulk data.
+- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in
+ previous versions of this driver but can now be configured to any endpoint
+ number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate
+ this feature and call usbSetInterrupt3() to send interrupt/bulk data. The
+ endpoint number can be set with USB_CFG_EP3_NUMBER.
+
+Please note that the USB standard forbids bulk endpoints for low speed devices!
+Most operating systems allow them anyway, but the AVR will spend 90% of the CPU
+time in the USB interrupt polling for bulk data.
Maximum data payload:
Data payload of control in and out transfers may be up to 254 bytes. In order
CPU in sleep mode. The driver does not implement suspend handling by itself.
However, the application may implement activity monitoring and wakeup from
sleep. The host sends regular SE0 states on the bus to keep it active. These
-SE0 states can be detected by wiring the INT1 pin to D-. It is not necessary
-to enable the interrupt, checking the interrupt pending flag should suffice.
-Before entering sleep mode, the application should enable INT1 for a wakeup
-on the next bus activity.
+SE0 states can be detected by using D- as the interrupt source. Define
+USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus
+activity.
Operation without an USB master:
The driver behaves neutral without connection to an USB master if D- reads
as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M)
-pullup resistor on D+. If D- becomes statically 0, the driver may block in
-the interrupt routine.
+pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used,
+use a pull-down. If D- becomes statically 0, the driver may block in the
+interrupt routine.
Interrupt latency:
The application must ensure that the USB interrupt is not disabled for more
-than 20 cycles. This implies that all interrupt routines must either be
-declared as "INTERRUPT" instead of "SIGNAL" (see "avr/signal.h") or that they
-are written in assembler with "sei" as the first instruction.
+than 25 cycles (this is for 12 MHz, faster clocks allow longer latency).
+This implies that all interrupt routines must either be declared as "INTERRUPT"
+instead of "SIGNAL" (see "avr/signal.h") or that they are written in assembler
+with "sei" as the first instruction.
Maximum interrupt duration / CPU cycle consumption:
The driver handles all USB communication during the interrupt service
/* --------------------------- Module Interface ---------------------------- */
/* ------------------------------------------------------------------------- */
-#define USBDRV_VERSION 20070707
+#define USBDRV_VERSION 20081126
/* This define uniquely identifies a driver version. It is a decimal number
* constructed from the driver's release date in the form YYYYMMDD. If the
* driver's behavior or interface changes, you can use this constant to
#endif
/* shortcuts for well defined 8 bit integer types */
+#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */
+# define usbMsgLen_t unsigned
+#else
+# define usbMsgLen_t uchar
+#endif
+/* usbMsgLen_t is the data type used for transfer lengths. By default, it is
+ * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for
+ * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1,
+ * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used
+ * for flags in the descriptor configuration).
+ */
+#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */
+
struct usbRequest; /* forward declaration */
USB_PUBLIC void usbInit(void);
* implementation of usbFunctionWrite(). It is also used internally by the
* driver for standard control requests.
*/
-USB_PUBLIC uchar usbFunctionSetup(uchar data[8]);
+USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]);
/* This function is called when the driver receives a SETUP transaction from
* the host which is not answered by the driver itself (in practice: class and
* vendor requests). All control transfers start with a SETUP transaction where
* requested data to the driver. There are two ways to transfer this data:
* (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data
* block and return the length of the data in 'usbFunctionSetup()'. The driver
- * will handle the rest. Or (2) return 0xff in 'usbFunctionSetup()'. The driver
- * will then call 'usbFunctionRead()' when data is needed. See the
+ * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The
+ * driver will then call 'usbFunctionRead()' when data is needed. See the
* documentation for usbFunctionRead() for details.
*
* If the SETUP indicates a control-out transfer, the only way to receive the
* data from the host is through the 'usbFunctionWrite()' call. If you
- * implement this function, you must return 0xff in 'usbFunctionSetup()' to
- * indicate that 'usbFunctionWrite()' should be used. See the documentation of
- * this function for more information. If you just want to ignore the data sent
- * by the host, return 0 in 'usbFunctionSetup()'.
+ * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()'
+ * to indicate that 'usbFunctionWrite()' should be used. See the documentation
+ * of this function for more information. If you just want to ignore the data
+ * sent by the host, return 0 in 'usbFunctionSetup()'.
*
* Note that calls to the functions usbFunctionRead() and usbFunctionWrite()
* are only done if enabled by the configuration in usbconfig.h.
*/
-USB_PUBLIC uchar usbFunctionDescriptor(struct usbRequest *rq);
+USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq);
/* You need to implement this function ONLY if you provide USB descriptors at
* runtime (which is an expert feature). It is very similar to
* usbFunctionSetup() above, but it is called only to request USB descriptor
* interrupt status to the host.
* If you need to transfer more bytes, use a control read after the interrupt.
*/
-extern volatile uchar usbTxLen1;
#define usbInterruptIsReady() (usbTxLen1 & 0x10)
/* This macro indicates whether the last interrupt message has already been
* sent. If you set a new interrupt message before the old was sent, the
*/
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len);
-extern volatile uchar usbTxLen3;
#define usbInterruptIsReady3() (usbTxLen3 & 0x10)
/* Same as above for endpoint 3 */
#endif
#endif /* USB_CFG_IMPLEMENT_FN_READ */
#if USB_CFG_IMPLEMENT_FN_WRITEOUT
USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len);
-/* This function is called by the driver when data on interrupt-out or bulk-
- * out endpoint 1 is received. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT
- * to 1 in usbconfig.h to get this function called.
+/* This function is called by the driver when data is received on an interrupt-
+ * or bulk-out endpoint. The endpoint number can be found in the global
+ * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in
+ * usbconfig.h to get this function called.
*/
#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */
#ifdef USB_CFG_PULLUP_IOPORTNAME
#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<<USB_CFG_PULLUP_BIT)), \
(USB_PULLUP_OUT |= (1<<USB_CFG_PULLUP_BIT)))
-/* This macro (intended to look like a function) connects the device to the
- * USB bus. It is only available if you have defined the constants
- * USB_CFG_PULLUP_IOPORT and USB_CFG_PULLUP_BIT in usbconfig.h.
- */
#define usbDeviceDisconnect() ((USB_PULLUP_DDR &= ~(1<<USB_CFG_PULLUP_BIT)), \
(USB_PULLUP_OUT &= ~(1<<USB_CFG_PULLUP_BIT)))
-/* This macro (intended to look like a function) disconnects the device from
- * the USB bus. It is only available if you have defined the constants
- * USB_CFG_PULLUP_IOPORT and USB_CFG_PULLUP_BIT in usbconfig.h.
+#else /* USB_CFG_PULLUP_IOPORTNAME */
+#define usbDeviceConnect() (USBDDR &= ~(1<<USBMINUS))
+#define usbDeviceDisconnect() (USBDDR |= (1<<USBMINUS))
+#endif /* USB_CFG_PULLUP_IOPORTNAME */
+/* The macros usbDeviceConnect() and usbDeviceDisconnect() (intended to look
+ * like a function) connect resp. disconnect the device from the host's USB.
+ * If the constants USB_CFG_PULLUP_IOPORT and USB_CFG_PULLUP_BIT are defined
+ * in usbconfig.h, a disconnect consists of removing the pull-up resisitor
+ * from D-, otherwise the disconnect is done by brute-force pulling D- to GND.
+ * This does not conform to the spec, but it works.
+ * Please note that the USB interrupt must be disabled while the device is
+ * in disconnected state, or the interrupt handler will hang! You can either
+ * turn off the USB interrupt selectively with
+ * USB_INTR_ENABLE &= ~(1 << USB_INTR_ENABLE_BIT)
+ * or use cli() to disable interrupts globally.
*/
-#endif /* USB_CFG_PULLUP_IOPORT */
extern unsigned usbCrc16(unsigned data, uchar len);
#define usbCrc16(data, len) usbCrc16((unsigned)(data), len)
/* This function calculates the binary complement of the data CRC used in
* the 2 bytes CRC (lowbyte first) in the 'data' buffer after reading 'len'
* bytes.
*/
+#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH
+extern unsigned usbMeasureFrameLength(void);
+/* This function MUST be called IMMEDIATELY AFTER USB reset and measures 1/7 of
+ * the number of CPU cycles during one USB frame minus one low speed bit
+ * length. In other words: return value = 1499 * (F_CPU / 10.5 MHz)
+ * Since this is a busy wait, you MUST disable all interrupts with cli() before
+ * calling this function.
+ * This can be used to calibrate the AVR's RC oscillator.
+ */
+#endif
extern uchar usbConfiguration;
/* This value contains the current configuration set by the host. The driver
* allows setting and querying of this variable with the USB SET_CONFIGURATION
* You may want to reflect the "configured" status with a LED on the device or
* switch on high power parts of the circuit only if the device is configured.
*/
+#if USB_COUNT_SOF
+extern volatile uchar usbSofCount;
+/* This variable is incremented on every SOF packet. It is only available if
+ * the macro USB_COUNT_SOF is defined to a value != 0.
+ */
+#endif
+#if USB_CFG_CHECK_DATA_TOGGLING
+extern uchar usbCurrentDataToken;
+/* This variable can be checked in usbFunctionWrite() and usbFunctionWriteOut()
+ * to ignore duplicate packets.
+ */
+#endif
+
#define USB_STRING_DESCRIPTOR_HEADER(stringLength) ((2*(stringLength)+2) | (3<<8))
/* This macro builds a descriptor header for a string descriptor given the
* string's length. See usbdrv.c for an example how to use it.
#define USB_SET_DATATOKEN1(token) usbTxBuf1[0] = token
#define USB_SET_DATATOKEN3(token) usbTxBuf3[0] = token
/* These two macros can be used by application software to reset data toggling
- * for interrupt-in endpoints 1 and 3.
+ * for interrupt-in endpoints 1 and 3. Since the token is toggled BEFORE
+ * sending data, you must set the opposite value of the token which should come
+ * first.
*/
#endif /* __ASSEMBLER__ */
* about the various methods to define USB descriptors. If you do nothing,
* the default descriptors will be used.
*/
-#define USB_PROP_IS_DYNAMIC (1 << 8)
+#define USB_PROP_IS_DYNAMIC (1 << 14)
/* If this property is set for a descriptor, usbFunctionDescriptor() will be
- * used to obtain the particular descriptor.
+ * used to obtain the particular descriptor. Data directly returned via
+ * usbMsgPtr are FLASH data by default, combine (OR) with USB_PROP_IS_RAM to
+ * return RAM data.
*/
-#define USB_PROP_IS_RAM (1 << 9)
+#define USB_PROP_IS_RAM (1 << 15)
/* If this property is set for a descriptor, the data is read from RAM
* memory instead of Flash. The property is used for all methods to provide
* external descriptors.
*/
-#define USB_PROP_LENGTH(len) ((len) & 0xff)
+#define USB_PROP_LENGTH(len) ((len) & 0x3fff)
/* If a static external descriptor is used, this is the total length of the
* descriptor in bytes.
*/
#define USB_CFG_PULLUP_IOPORT USB_OUTPORT(USB_CFG_PULLUP_IOPORTNAME)
#endif
+#ifndef USB_CFG_EP3_NUMBER /* if not defined in usbconfig.h */
+#define USB_CFG_EP3_NUMBER 3
+#endif
+
+#ifndef USB_CFG_HAVE_INTRIN_ENDPOINT3
+#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0
+#endif
#define USB_BUFSIZE 11 /* PID, 8 bytes data, 2 bytes CRC */
# endif
#endif
#ifndef USB_INTR_CFG_SET /* allow user to override our default */
-# define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) /* cfg for rising edge */
+# if defined(USB_COUNT_SOF) || defined(USB_SOF_HOOK)
+# define USB_INTR_CFG_SET (1 << ISC01) /* cfg for falling edge */
+ /* If any SOF logic is used, the interrupt must be wired to D- where
+ * we better trigger on falling edge
+ */
+# else
+# define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) /* cfg for rising edge */
+# endif
#endif
#ifndef USB_INTR_CFG_CLR /* allow user to override our default */
# define USB_INTR_CFG_CLR 0 /* no bits to clear */
#define USBPID_NAK 0x5a
#define USBPID_STALL 0x1e
+#ifndef USB_INITIAL_DATATOKEN
+#define USB_INITIAL_DATATOKEN USBPID_DATA1
+#endif
+
#ifndef __ASSEMBLER__
-extern uchar usbTxBuf1[USB_BUFSIZE], usbTxBuf3[USB_BUFSIZE];
+typedef struct usbTxStatus{
+ volatile uchar len;
+ uchar buffer[USB_BUFSIZE];
+}usbTxStatus_t;
+
+extern usbTxStatus_t usbTxStatus1, usbTxStatus3;
+#define usbTxLen1 usbTxStatus1.len
+#define usbTxBuf1 usbTxStatus1.buffer
+#define usbTxLen3 usbTxStatus3.len
+#define usbTxBuf3 usbTxStatus3.buffer
+
typedef union usbWord{
unsigned word;
* Creation Date: 2007-06-13
* Tabsize: 4
* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * Revision: $Id$
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm.S 692 2008-11-07 15:07:40Z cs $
*/
/*
the file appropriate for the given clock rate.
*/
-#include "iarcompat.h"
-#ifndef __IAR_SYSTEMS_ASM__
- /* configs for io.h */
-# define __SFR_OFFSET 0
-# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */
-# include <avr/io.h> /* for CPU I/O register definitions and vectors */
-#endif /* __IAR_SYSTEMS_ASM__ */
-#include "usbdrv.h" /* for common defs */
-
+#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */
+#include "usbportability.h"
+#include "usbdrv.h" /* for common defs */
/* register names */
#define x1 r16
/* Some assembler dependent definitions and declarations: */
#ifdef __IAR_SYSTEMS_ASM__
-
-# define nop2 rjmp $+2 /* jump to next instruction */
-# define XL r26
-# define XH r27
-# define YL r28
-# define YH r29
-# define ZL r30
-# define ZH r31
-# define lo8(x) LOW(x)
-# define hi8(x) ((x)>>8) /* not HIGH to allow XLINK to make a proper range check */
-
extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset
extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen
- extern usbTxBuf, usbMsgLen, usbTxLen1, usbTxBuf1, usbTxLen3, usbTxBuf3
+ extern usbTxBuf, usbTxStatus1, usbTxStatus3
+# if USB_COUNT_SOF
+ extern usbSofCount
+# endif
public usbCrc16
public usbCrc16Append
COMMON INTVEC
- ORG INT0_vect
- rjmp SIG_INTERRUPT0
+# ifndef USB_INTR_VECTOR
+ ORG INT0_vect
+# else /* USB_INTR_VECTOR */
+ ORG USB_INTR_VECTOR
+# undef USB_INTR_VECTOR
+# endif /* USB_INTR_VECTOR */
+# define USB_INTR_VECTOR usbInterruptHandler
+ rjmp USB_INTR_VECTOR
RSEG CODE
#else /* __IAR_SYSTEMS_ASM__ */
-# define nop2 rjmp .+0 /* jump to next instruction */
-
+# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */
+# define USB_INTR_VECTOR SIG_INTERRUPT0
+# endif
.text
- .global SIG_INTERRUPT0
- .type SIG_INTERRUPT0, @function
+ .global USB_INTR_VECTOR
+ .type USB_INTR_VECTOR, @function
.global usbCrc16
.global usbCrc16Append
-
#endif /* __IAR_SYSTEMS_ASM__ */
+
+#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */
+# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING
+# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg
+#else /* It's a memory address, use lds and sts */
+# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING
+# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg
+#endif
+
+#define usbTxLen1 usbTxStatus1
+#define usbTxBuf1 (usbTxStatus1 + 1)
+#define usbTxLen3 usbTxStatus3
+#define usbTxBuf3 (usbTxStatus3 + 1)
+
+
;----------------------------------------------------------------------------
; Utility functions
;----------------------------------------------------------------------------
usbCrc16:
mov ptrL, argPtrL
mov ptrH, argPtrH
- ldi resCrcL, 0xff
- ldi resCrcH, 0xff
+ ldi resCrcL, 0
+ ldi resCrcH, 0
ldi polyL, lo8(0xa001)
ldi polyH, hi8(0xa001)
+ com argLen ; argLen = -argLen - 1
crcByteLoop:
- subi argLen, 1
- brcs crcReady
+ subi argLen, -1
+ brcc crcReady ; modified loop to ensure that carry is set below
ld byte, ptr+
- ldi bitCnt, 8
+ ldi bitCnt, -8 ; strange loop counter to ensure that carry is set where we need it
+ eor resCrcL, byte
crcBitLoop:
- mov scratch, byte
- eor scratch, resCrcL
- lsr resCrcH
+ ror resCrcH ; carry is always set here
ror resCrcL
- lsr byte
- sbrs scratch, 0
- rjmp crcNoXor
+ brcs crcNoXor
eor resCrcL, polyL
eor resCrcH, polyH
crcNoXor:
- dec bitCnt
- brne crcBitLoop
+ subi bitCnt, -1
+ brcs crcBitLoop
rjmp crcByteLoop
crcReady:
- com resCrcL
- com resCrcH
ret
+; Thanks to Reimar Doeffinger for optimizing this CRC routine!
; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len);
usbCrc16Append:
st ptr+, resCrcH
ret
+#undef argLen
+#undef argPtrL
+#undef argPtrH
+#undef resCrcL
+#undef resCrcH
+#undef ptrL
+#undef ptrH
+#undef ptr
+#undef byte
+#undef bitCnt
+#undef polyL
+#undef polyH
+#undef scratch
+
+
+#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH
+#ifdef __IAR_SYSTEMS_ASM__
+/* Register assignments for usbMeasureFrameLength on IAR cc */
+/* Calling conventions on IAR:
+ * First parameter passed in r16/r17, second in r18/r19 and so on.
+ * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer)
+ * Result is passed in r16/r17
+ * In case of the "tiny" memory model, pointers are only 8 bit with no
+ * padding. We therefore pass argument 1 as "16 bit unsigned".
+ */
+# define resL r16
+# define resH r17
+# define cnt16L r30
+# define cnt16H r31
+# define cntH r18
+
+#else /* __IAR_SYSTEMS_ASM__ */
+/* Register assignments for usbMeasureFrameLength on gcc */
+/* Calling conventions on gcc:
+ * First parameter passed in r24/r25, second in r22/23 and so on.
+ * Callee must preserve r1-r17, r28/r29
+ * Result is passed in r24/r25
+ */
+# define resL r24
+# define resH r25
+# define cnt16L r24
+# define cnt16H r25
+# define cntH r26
+#endif
+# define cnt16 cnt16L
+
+; extern unsigned usbMeasurePacketLength(void);
+; returns time between two idle strobes in multiples of 7 CPU clocks
+.global usbMeasureFrameLength
+usbMeasureFrameLength:
+ ldi cntH, 6 ; wait ~ 10 ms for D- == 0
+ clr cnt16L
+ clr cnt16H
+usbMFTime16:
+ dec cntH
+ breq usbMFTimeout
+usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe)
+ sbiw cnt16, 1 ;[0] [6]
+ breq usbMFTime16 ;[2]
+ sbic USBIN, USBMINUS ;[3]
+ rjmp usbMFWaitStrobe ;[4]
+usbMFWaitIdle: ; then wait until idle again
+ sbis USBIN, USBMINUS ;1 wait for D- == 1
+ rjmp usbMFWaitIdle ;2
+ ldi cnt16L, 1 ;1 represents cycles so far
+ clr cnt16H ;1
+usbMFWaitLoop:
+ in cntH, USBIN ;[0] [7]
+ adiw cnt16, 1 ;[1]
+ breq usbMFTimeout ;[3]
+ andi cntH, USBMASK ;[4]
+ brne usbMFWaitLoop ;[5]
+usbMFTimeout:
+#if resL != cnt16L
+ mov resL, cnt16L
+ mov resH, cnt16H
+#endif
+ ret
+
+#undef resL
+#undef resH
+#undef cnt16
+#undef cnt16L
+#undef cnt16H
+#undef cntH
+
+#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */
;----------------------------------------------------------------------------
; Now include the clock rate specific code
#endif
#if USB_CFG_CLOCK_KHZ == 12000
-# include "usbdrvasm12.S"
+# include "usbdrvasm12.inc"
+#elif USB_CFG_CLOCK_KHZ == 12800
+# include "usbdrvasm128.inc"
+#elif USB_CFG_CLOCK_KHZ == 15000
+# include "usbdrvasm15.inc"
#elif USB_CFG_CLOCK_KHZ == 16000
-# include "usbdrvasm16.S"
+# include "usbdrvasm16.inc"
#elif USB_CFG_CLOCK_KHZ == 16500
-# include "usbdrvasm165.S"
+# include "usbdrvasm165.inc"
+#elif USB_CFG_CLOCK_KHZ == 20000
+# include "usbdrvasm20.inc"
#else
# error "USB_CFG_CLOCK_KHZ is not one of the supported rates!"
#endif
* Creation Date: 2006-03-01
* Tabsize: 4
* Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
* This Revision: $Id$
*/
+++ /dev/null
-/* Name: usbdrvasm12.S
- * Project: AVR USB driver
- * Author: Christian Starkjohann
- * Creation Date: 2004-12-29
- * Tabsize: 4
- * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * This Revision: $Id: usbdrvasm12.S 353 2007-06-21 19:05:08Z cs $
- */
-
-/* Do not link this file! Link usbdrvasm.S instead, which includes the
- * appropriate implementation!
- */
-
-/*
-General Description:
-This file is the 12 MHz version of the asssembler part of the USB driver. It
-requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
-oscillator).
-
-See usbdrv.h for a description of the entire driver.
-
-Since almost all of this code is timing critical, don't change unless you
-really know what you are doing! Many parts require not only a maximum number
-of CPU cycles, but even an exact number of cycles!
-
-
-Timing constraints according to spec (in bit times):
-timing subject min max CPUcycles
----------------------------------------------------------------------------
-EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
-EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
-DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
-*/
-
-;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
-;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
-;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
-;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
-;Numbers in brackets are maximum cycles since SOF.
-SIG_INTERRUPT0:
-;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
- push YL ;2 [35] push only what is necessary to sync with edge ASAP
- in YL, SREG ;1 [37]
- push YL ;2 [39]
-;----------------------------------------------------------------------------
-; Synchronize with sync pattern:
-;----------------------------------------------------------------------------
-;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
-;sync up with J to K edge during sync pattern -- use fastest possible loops
-;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
-waitForJ:
- sbis USBIN, USBMINUS ;1 [40] wait for D- == 1
- rjmp waitForJ ;2
-waitForK:
-;The following code results in a sampling window of 1/4 bit which meets the spec.
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- rjmp sofError
-foundK:
-;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
-;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
-;are cycles from center of first sync (double K) bit after the instruction
- push YH ;2 [2]
- lds YL, usbInputBufOffset;2 [4]
- clr YH ;1 [5]
- subi YL, lo8(-(usbRxBuf));1 [6]
- sbci YH, hi8(-(usbRxBuf));1 [7]
-
- sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
- rjmp haveTwoBitsK ;2 [10]
- pop YH ;2 [11] undo the push from before
- rjmp waitForK ;2 [13] this was not the end of sync, retry
-haveTwoBitsK:
-;----------------------------------------------------------------------------
-; push more registers and initialize values while we sample the first bits:
-;----------------------------------------------------------------------------
- push shift ;2 [16]
- push x1 ;2 [12]
- push x2 ;2 [14]
-
- in x1, USBIN ;1 [17] <-- sample bit 0
- ldi shift, 0xff ;1 [18]
- bst x1, USBMINUS ;1 [19]
- bld shift, 0 ;1 [20]
- push x3 ;2 [22]
- push cnt ;2 [24]
-
- in x2, USBIN ;1 [25] <-- sample bit 1
- ser x3 ;1 [26] [inserted init instruction]
- eor x1, x2 ;1 [27]
- bst x1, USBMINUS ;1 [28]
- bld shift, 1 ;1 [29]
- ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
- rjmp rxbit2 ;2 [32]
-
-;----------------------------------------------------------------------------
-; Receiver loop (numbers in brackets are cycles within byte after instr)
-;----------------------------------------------------------------------------
-
-unstuff0: ;1 (branch taken)
- andi x3, ~0x01 ;1 [15]
- mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
- in x2, USBIN ;1 [17] <-- sample bit 1 again
- ori shift, 0x01 ;1 [18]
- rjmp didUnstuff0 ;2 [20]
-
-unstuff1: ;1 (branch taken)
- mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
- andi x3, ~0x02 ;1 [22]
- ori shift, 0x02 ;1 [23]
- nop ;1 [24]
- in x1, USBIN ;1 [25] <-- sample bit 2 again
- rjmp didUnstuff1 ;2 [27]
-
-unstuff2: ;1 (branch taken)
- andi x3, ~0x04 ;1 [29]
- ori shift, 0x04 ;1 [30]
- mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
- nop ;1 [32]
- in x2, USBIN ;1 [33] <-- sample bit 3
- rjmp didUnstuff2 ;2 [35]
-
-unstuff3: ;1 (branch taken)
- in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
- andi x3, ~0x08 ;1 [35]
- ori shift, 0x08 ;1 [36]
- rjmp didUnstuff3 ;2 [38]
-
-unstuff4: ;1 (branch taken)
- andi x3, ~0x10 ;1 [40]
- in x1, USBIN ;1 [41] <-- sample stuffed bit 4
- ori shift, 0x10 ;1 [42]
- rjmp didUnstuff4 ;2 [44]
-
-unstuff5: ;1 (branch taken)
- andi x3, ~0x20 ;1 [48]
- in x2, USBIN ;1 [49] <-- sample stuffed bit 5
- ori shift, 0x20 ;1 [50]
- rjmp didUnstuff5 ;2 [52]
-
-unstuff6: ;1 (branch taken)
- andi x3, ~0x40 ;1 [56]
- in x1, USBIN ;1 [57] <-- sample stuffed bit 6
- ori shift, 0x40 ;1 [58]
- rjmp didUnstuff6 ;2 [60]
-
-; extra jobs done during bit interval:
-; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
-; bit 1: se0 check
-; bit 2: overflow check
-; bit 3: recovery from delay [bit 0 tasks took too long]
-; bit 4: none
-; bit 5: none
-; bit 6: none
-; bit 7: jump, eor
-rxLoop:
- eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
- in x1, USBIN ;1 [1] <-- sample bit 0
- st y+, x3 ;2 [3] store data
- ser x3 ;1 [4]
- nop ;1 [5]
- eor x2, x1 ;1 [6]
- bst x2, USBMINUS;1 [7]
- bld shift, 0 ;1 [8]
- in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
- andi x2, USBMASK ;1 [10]
- breq se0 ;1 [11] SE0 check for bit 1
- andi shift, 0xf9 ;1 [12]
-didUnstuff0:
- breq unstuff0 ;1 [13]
- eor x1, x2 ;1 [14]
- bst x1, USBMINUS;1 [15]
- bld shift, 1 ;1 [16]
-rxbit2:
- in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
- andi shift, 0xf3 ;1 [18]
- breq unstuff1 ;1 [19] do remaining work for bit 1
-didUnstuff1:
- subi cnt, 1 ;1 [20]
- brcs overflow ;1 [21] loop control
- eor x2, x1 ;1 [22]
- bst x2, USBMINUS;1 [23]
- bld shift, 2 ;1 [24]
- in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
- andi shift, 0xe7 ;1 [26]
- breq unstuff2 ;1 [27]
-didUnstuff2:
- eor x1, x2 ;1 [28]
- bst x1, USBMINUS;1 [29]
- bld shift, 3 ;1 [30]
-didUnstuff3:
- andi shift, 0xcf ;1 [31]
- breq unstuff3 ;1 [32]
- in x1, USBIN ;1 [33] <-- sample bit 4
- eor x2, x1 ;1 [34]
- bst x2, USBMINUS;1 [35]
- bld shift, 4 ;1 [36]
-didUnstuff4:
- andi shift, 0x9f ;1 [37]
- breq unstuff4 ;1 [38]
- nop2 ;2 [40]
- in x2, USBIN ;1 [41] <-- sample bit 5
- eor x1, x2 ;1 [42]
- bst x1, USBMINUS;1 [43]
- bld shift, 5 ;1 [44]
-didUnstuff5:
- andi shift, 0x3f ;1 [45]
- breq unstuff5 ;1 [46]
- nop2 ;2 [48]
- in x1, USBIN ;1 [49] <-- sample bit 6
- eor x2, x1 ;1 [50]
- bst x2, USBMINUS;1 [51]
- bld shift, 6 ;1 [52]
-didUnstuff6:
- cpi shift, 0x02 ;1 [53]
- brlo unstuff6 ;1 [54]
- nop2 ;2 [56]
- in x2, USBIN ;1 [57] <-- sample bit 7
- eor x1, x2 ;1 [58]
- bst x1, USBMINUS;1 [59]
- bld shift, 7 ;1 [60]
-didUnstuff7:
- cpi shift, 0x04 ;1 [61]
- brsh rxLoop ;2 [63] loop control
-unstuff7:
- andi x3, ~0x80 ;1 [63]
- ori shift, 0x80 ;1 [64]
- in x2, USBIN ;1 [65] <-- sample stuffed bit 7
- nop ;1 [66]
- rjmp didUnstuff7 ;2 [68]
-
-
-;----------------------------------------------------------------------------
-; Processing of received packet (numbers in brackets are cycles after end of SE0)
-;----------------------------------------------------------------------------
-;This is the only non-error exit point for the software receiver loop
-;we don't check any CRCs here because there is no time left.
-#define token x1
-se0: ; [0]
- subi cnt, USB_BUFSIZE ;1 [1]
- neg cnt ;1 [2]
- cpi cnt, 3 ;1 [3]
- ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [4]
- out USB_INTR_PENDING, x2;1 [5] clear pending intr and check flag later. SE0 should be over.
- brlo doReturn ;1 [6] this is probably an ACK, NAK or similar packet
- sub YL, cnt ;1 [7]
- sbci YH, 0 ;1 [8]
- ld token, y ;2 [10]
- cpi token, USBPID_DATA0 ;1 [11]
- breq handleData ;1 [12]
- cpi token, USBPID_DATA1 ;1 [13]
- breq handleData ;1 [14]
- ldd x2, y+1 ;2 [16] ADDR and 1 bit endpoint number
- mov x3, x2 ;1 [17] store for endpoint number
- andi x2, 0x7f ;1 [18] x2 is now ADDR
- lds shift, usbDeviceAddr;2 [20]
- cp x2, shift ;1 [21]
-overflow: ; This is a hack: brcs overflow will never have Z flag set
- brne ignorePacket ;1 [22] packet for different address
- cpi token, USBPID_IN ;1 [23]
- breq handleIn ;1 [24]
- cpi token, USBPID_SETUP ;1 [25]
- breq handleSetupOrOut ;1 [26]
- cpi token, USBPID_OUT ;1 [27]
- breq handleSetupOrOut ;1 [28]
-; rjmp ignorePacket ;fallthrough, should not happen anyway.
-
-ignorePacket:
- clr shift
- sts usbCurrentTok, shift
-doReturn:
- pop cnt
- pop x3
- pop x2
- pop x1
- pop shift
- pop YH
-sofError:
- pop YL
- out SREG, YL
- pop YL
- reti
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
-handleIn3: ;1 [38] (branch taken)
- lds cnt, usbTxLen3 ;2 [40]
- sbrc cnt, 4 ;2 [42]
- rjmp sendCntAndReti ;0 43 + 17 = 60 until SOP
- sts usbTxLen3, x1 ;2 [44] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf3) ;1 [45]
- ldi YH, hi8(usbTxBuf3) ;1 [46]
- rjmp usbSendAndReti ;2 [48] + 13 = 61 until SOP (violates the spec by 1 cycle)
-#endif
-
-;Setup and Out are followed by a data packet two bit times (16 cycles) after
-;the end of SE0. The sync code allows up to 40 cycles delay from the start of
-;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
-handleSetupOrOut: ;1 [29] (branch taken)
-#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
- sbrc x3, 7 ;1 [30] skip if endpoint 0
- ldi token, -1 ;1 [31] indicate that this is endpoint 1 OUT
-#endif
- sts usbCurrentTok, token;2 [33]
- pop cnt ;2 [35]
- pop x3 ;2 [37]
- pop x2 ;2 [39]
- pop x1 ;2 [41]
- pop shift ;2 [43]
- pop YH ;2 [45]
- in YL, USB_INTR_PENDING;1 [46]
- sbrc YL, USB_INTR_PENDING_BIT;1 [47] check whether data is already arriving
- rjmp waitForJ ;2 [49] save the pops and pushes -- a new interrupt is aready pending
- rjmp sofError ;2 not an error, but it does the pops and reti we want
-
-
-handleData: ;1 [15] (branch taken)
- lds token, usbCurrentTok;2 [17]
- tst token ;1 [18]
- breq doReturn ;1 [19]
- lds x2, usbRxLen ;2 [21]
- tst x2 ;1 [22]
- brne sendNakAndReti ;1 [23]
-; 2006-03-11: The following two lines fix a problem where the device was not
-; recognized if usbPoll() was called less frequently than once every 4 ms.
- cpi cnt, 4 ;1 [24] zero sized data packets are status phase only -- ignore and ack
- brmi sendAckAndReti ;1 [25] keep rx buffer clean -- we must not NAK next SETUP
- sts usbRxLen, cnt ;2 [27] store received data, swap buffers
- sts usbRxToken, token ;2 [29]
- lds x2, usbInputBufOffset;2 [31] swap buffers
- ldi cnt, USB_BUFSIZE ;1 [32]
- sub cnt, x2 ;1 [33]
- sts usbInputBufOffset, cnt;2 [35] buffers now swapped
- rjmp sendAckAndReti ;2 [37] + 19 = 56 until SOP
-
-handleIn: ;1 [25] (branch taken)
-;We don't send any data as long as the C code has not processed the current
-;input data and potentially updated the output data. That's more efficient
-;in terms of code size than clearing the tx buffers when a packet is received.
- lds x1, usbRxLen ;2 [27]
- cpi x1, 1 ;1 [28] negative values are flow control, 0 means "buffer free"
- brge sendNakAndReti ;1 [29] unprocessed input packet?
- ldi x1, USBPID_NAK ;1 [30] prepare value for usbTxLen
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
- sbrc x3, 7 ;2 [33] x3 contains addr + endpoint
- rjmp handleIn1 ;0
-#endif
- lds cnt, usbTxLen ;2 [34]
- sbrc cnt, 4 ;2 [36] all handshake tokens have bit 4 set
- rjmp sendCntAndReti ;0 37 + 17 = 54 until SOP
- sts usbTxLen, x1 ;2 [38] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf) ;1 [39]
- ldi YH, hi8(usbTxBuf) ;1 [40]
- rjmp usbSendAndReti ;2 [42] + 14 = 56 until SOP
-
-; Comment about when to set usbTxLen to USBPID_NAK:
-; We should set it back when we receive the ACK from the host. This would
-; be simple to implement: One static variable which stores whether the last
-; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
-; ACK. However, we set it back immediately when we send the package,
-; assuming that no error occurs and the host sends an ACK. We save one byte
-; RAM this way and avoid potential problems with endless retries. The rest of
-; the driver assumes error-free transfers anyway.
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
-handleIn1: ;1 [33] (branch taken)
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
- ldd x2, y+2 ;2 [35]
- sbrc x2, 0 ;2 [37]
- rjmp handleIn3 ;0
-#endif
- lds cnt, usbTxLen1 ;2 [39]
- sbrc cnt, 4 ;2 [41] all handshake tokens have bit 4 set
- rjmp sendCntAndReti ;0 42 + 17 = 59 until SOP
- sts usbTxLen1, x1 ;2 [43] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf1) ;1 [44]
- ldi YH, hi8(usbTxBuf1) ;1 [45]
- rjmp usbSendAndReti ;2 [47] + 13 = 60 until SOP
-#endif
-
-
-;----------------------------------------------------------------------------
-; Transmitting data
-;----------------------------------------------------------------------------
-
-bitstuff0: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- out USBOUT, x1 ;1 <-- out
- rjmp didStuff0 ;2 branch back 2 cycles earlier
-bitstuff1: ;1 (for branch taken)
- eor x1, x4 ;1
- rjmp didStuff1 ;2 we know that C is clear, jump back to do OUT and ror 0 into x2
-bitstuff2: ;1 (for branch taken)
- eor x1, x4 ;1
- rjmp didStuff2 ;2 jump back 4 cycles earlier and do out and ror 0 into x2
-bitstuff3: ;1 (for branch taken)
- eor x1, x4 ;1
- rjmp didStuff3 ;2 jump back earlier and ror 0 into x2
-bitstuff4: ;1 (for branch taken)
- eor x1, x4 ;1
- ldi x2, 0 ;1
- out USBOUT, x1 ;1 <-- out
- rjmp didStuff4 ;2 jump back 2 cycles earlier
-
-sendNakAndReti: ;0 [-19] 19 cycles until SOP
- ldi x3, USBPID_NAK ;1 [-18]
- rjmp usbSendX3 ;2 [-16]
-sendAckAndReti: ;0 [-19] 19 cycles until SOP
- ldi x3, USBPID_ACK ;1 [-18]
- rjmp usbSendX3 ;2 [-16]
-sendCntAndReti: ;0 [-17] 17 cycles until SOP
- mov x3, cnt ;1 [-16]
-usbSendX3: ;0 [-16]
- ldi YL, 20 ;1 [-15] 'x3' is R20
- ldi YH, 0 ;1 [-14]
- ldi cnt, 2 ;1 [-13]
-; rjmp usbSendAndReti fallthrough
-
-; USB spec says:
-; idle = J
-; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
-; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
-; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
-
-;usbSend:
-;pointer to data in 'Y'
-;number of bytes in 'cnt' -- including sync byte
-;uses: x1...x4, shift, cnt, Y
-;Numbers in brackets are time since first bit of sync pattern is sent
-usbSendAndReti: ;0 [-13] timing: 13 cycles until SOP
- in x2, USBDDR ;1 [-12]
- ori x2, USBMASK ;1 [-11]
- sbi USBOUT, USBMINUS;2 [-9] prepare idle state; D+ and D- must have been 0 (no pullups)
- in x1, USBOUT ;1 [-8] port mirror for tx loop
- out USBDDR, x2 ;1 [-7] <- acquire bus
-; need not init x2 (bitstuff history) because sync starts with 0
- push x4 ;2 [-5]
- ldi x4, USBMASK ;1 [-4] exor mask
- ldi shift, 0x80 ;1 [-3] sync byte is first byte sent
-txLoop: ; [62]
- sbrs shift, 0 ;1 [-2] [62]
- eor x1, x4 ;1 [-1] [63]
- out USBOUT, x1 ;1 [0] <-- out bit 0
- ror shift ;1 [1]
- ror x2 ;1 [2]
-didStuff0:
- cpi x2, 0xfc ;1 [3]
- brsh bitstuff0 ;1 [4]
- sbrs shift, 0 ;1 [5]
- eor x1, x4 ;1 [6]
- ror shift ;1 [7]
-didStuff1:
- out USBOUT, x1 ;1 [8] <-- out bit 1
- ror x2 ;1 [9]
- cpi x2, 0xfc ;1 [10]
- brsh bitstuff1 ;1 [11]
- sbrs shift, 0 ;1 [12]
- eor x1, x4 ;1 [13]
- ror shift ;1 [14]
-didStuff2:
- ror x2 ;1 [15]
- out USBOUT, x1 ;1 [16] <-- out bit 2
- cpi x2, 0xfc ;1 [17]
- brsh bitstuff2 ;1 [18]
- sbrs shift, 0 ;1 [19]
- eor x1, x4 ;1 [20]
- ror shift ;1 [21]
-didStuff3:
- ror x2 ;1 [22]
- cpi x2, 0xfc ;1 [23]
- out USBOUT, x1 ;1 [24] <-- out bit 3
- brsh bitstuff3 ;1 [25]
- nop2 ;2 [27]
- ld x3, y+ ;2 [29]
- sbrs shift, 0 ;1 [30]
- eor x1, x4 ;1 [31]
- out USBOUT, x1 ;1 [32] <-- out bit 4
- ror shift ;1 [33]
- ror x2 ;1 [34]
-didStuff4:
- cpi x2, 0xfc ;1 [35]
- brsh bitstuff4 ;1 [36]
- sbrs shift, 0 ;1 [37]
- eor x1, x4 ;1 [38]
- ror shift ;1 [39]
-didStuff5:
- out USBOUT, x1 ;1 [40] <-- out bit 5
- ror x2 ;1 [41]
- cpi x2, 0xfc ;1 [42]
- brsh bitstuff5 ;1 [43]
- sbrs shift, 0 ;1 [44]
- eor x1, x4 ;1 [45]
- ror shift ;1 [46]
-didStuff6:
- ror x2 ;1 [47]
- out USBOUT, x1 ;1 [48] <-- out bit 6
- cpi x2, 0xfc ;1 [49]
- brsh bitstuff6 ;1 [50]
- sbrs shift, 0 ;1 [51]
- eor x1, x4 ;1 [52]
- ror shift ;1 [53]
-didStuff7:
- ror x2 ;1 [54]
- cpi x2, 0xfc ;1 [55]
- out USBOUT, x1 ;1 [56] <-- out bit 7
- brsh bitstuff7 ;1 [57]
- mov shift, x3 ;1 [58]
- dec cnt ;1 [59]
- brne txLoop ;1/2 [60/61]
-;make SE0:
- cbr x1, USBMASK ;1 [61] prepare SE0 [spec says EOP may be 15 to 18 cycles]
- pop x4 ;2 [63]
-;brackets are cycles from start of SE0 now
- out USBOUT, x1 ;1 [0] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
- nop2 ;2 [2]
-;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
-;set address only after data packet was sent, not after handshake
- lds x2, usbNewDeviceAddr;2 [4]
- subi YL, 20 + 2 ;1 [5]
- sbci YH, 0 ;1 [6]
- breq skipAddrAssign ;2 [8]
- sts usbDeviceAddr, x2;0 if not skipped: SE0 is one cycle longer
-skipAddrAssign:
-;end of usbDeviceAddress transfer
- ldi x2, 1<<USB_INTR_PENDING_BIT;1 [9] int0 occurred during TX -- clear pending flag
- out USB_INTR_PENDING, x2;1 [10]
- ori x1, USBIDLE ;1 [11]
- in x2, USBDDR ;1 [12]
- cbr x2, USBMASK ;1 [13] set both pins to input
- mov x3, x1 ;1 [14]
- cbr x3, USBMASK ;1 [15] configure no pullup on both pins
- out USBOUT, x1 ;1 [16] <-- out J (idle) -- end of SE0 (EOP signal)
- out USBDDR, x2 ;1 [17] <-- release bus now
- out USBOUT, x3 ;1 [18] <-- ensure no pull-up resistors are active
- rjmp doReturn
-
-bitstuff5: ;1 (for branch taken)
- eor x1, x4 ;1
- rjmp didStuff5 ;2 same trick as above...
-bitstuff6: ;1 (for branch taken)
- eor x1, x4 ;1
- rjmp didStuff6 ;2 same trick as above...
-bitstuff7: ;1 (for branch taken)
- eor x1, x4 ;1
- rjmp didStuff7 ;2 same trick as above...
--- /dev/null
+/* Name: usbdrvasm12.inc
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2004-12-29
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrvasm12.inc 692 2008-11-07 15:07:40Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 12 MHz version of the asssembler part of the USB driver. It
+requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+
+
+Timing constraints according to spec (in bit times):
+timing subject min max CPUcycles
+---------------------------------------------------------------------------
+EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
+EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
+DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
+*/
+
+;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
+;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
+;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
+;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
+;Numbers in brackets are maximum cycles since SOF.
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
+ push YL ;2 [35] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1 [37]
+ push YL ;2 [39]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK:
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push YH ;2 [2]
+ lds YL, usbInputBufOffset;2 [4]
+ clr YH ;1 [5]
+ subi YL, lo8(-(usbRxBuf));1 [6]
+ sbci YH, hi8(-(usbRxBuf));1 [7]
+
+ sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
+ rjmp haveTwoBitsK ;2 [10]
+ pop YH ;2 [11] undo the push from before
+ rjmp waitForK ;2 [13] this was not the end of sync, retry
+haveTwoBitsK:
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+ push shift ;2 [16]
+ push x1 ;2 [12]
+ push x2 ;2 [14]
+
+ in x1, USBIN ;1 [17] <-- sample bit 0
+ ldi shift, 0xff ;1 [18]
+ bst x1, USBMINUS ;1 [19]
+ bld shift, 0 ;1 [20]
+ push x3 ;2 [22]
+ push cnt ;2 [24]
+
+ in x2, USBIN ;1 [25] <-- sample bit 1
+ ser x3 ;1 [26] [inserted init instruction]
+ eor x1, x2 ;1 [27]
+ bst x1, USBMINUS ;1 [28]
+ bld shift, 1 ;1 [29]
+ ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
+ rjmp rxbit2 ;2 [32]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+
+unstuff0: ;1 (branch taken)
+ andi x3, ~0x01 ;1 [15]
+ mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
+ in x2, USBIN ;1 [17] <-- sample bit 1 again
+ ori shift, 0x01 ;1 [18]
+ rjmp didUnstuff0 ;2 [20]
+
+unstuff1: ;1 (branch taken)
+ mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
+ andi x3, ~0x02 ;1 [22]
+ ori shift, 0x02 ;1 [23]
+ nop ;1 [24]
+ in x1, USBIN ;1 [25] <-- sample bit 2 again
+ rjmp didUnstuff1 ;2 [27]
+
+unstuff2: ;1 (branch taken)
+ andi x3, ~0x04 ;1 [29]
+ ori shift, 0x04 ;1 [30]
+ mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
+ nop ;1 [32]
+ in x2, USBIN ;1 [33] <-- sample bit 3
+ rjmp didUnstuff2 ;2 [35]
+
+unstuff3: ;1 (branch taken)
+ in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
+ andi x3, ~0x08 ;1 [35]
+ ori shift, 0x08 ;1 [36]
+ rjmp didUnstuff3 ;2 [38]
+
+unstuff4: ;1 (branch taken)
+ andi x3, ~0x10 ;1 [40]
+ in x1, USBIN ;1 [41] <-- sample stuffed bit 4
+ ori shift, 0x10 ;1 [42]
+ rjmp didUnstuff4 ;2 [44]
+
+unstuff5: ;1 (branch taken)
+ andi x3, ~0x20 ;1 [48]
+ in x2, USBIN ;1 [49] <-- sample stuffed bit 5
+ ori shift, 0x20 ;1 [50]
+ rjmp didUnstuff5 ;2 [52]
+
+unstuff6: ;1 (branch taken)
+ andi x3, ~0x40 ;1 [56]
+ in x1, USBIN ;1 [57] <-- sample stuffed bit 6
+ ori shift, 0x40 ;1 [58]
+ rjmp didUnstuff6 ;2 [60]
+
+; extra jobs done during bit interval:
+; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
+; bit 1: se0 check
+; bit 2: overflow check
+; bit 3: recovery from delay [bit 0 tasks took too long]
+; bit 4: none
+; bit 5: none
+; bit 6: none
+; bit 7: jump, eor
+rxLoop:
+ eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ in x1, USBIN ;1 [1] <-- sample bit 0
+ st y+, x3 ;2 [3] store data
+ ser x3 ;1 [4]
+ nop ;1 [5]
+ eor x2, x1 ;1 [6]
+ bst x2, USBMINUS;1 [7]
+ bld shift, 0 ;1 [8]
+ in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
+ andi x2, USBMASK ;1 [10]
+ breq se0 ;1 [11] SE0 check for bit 1
+ andi shift, 0xf9 ;1 [12]
+didUnstuff0:
+ breq unstuff0 ;1 [13]
+ eor x1, x2 ;1 [14]
+ bst x1, USBMINUS;1 [15]
+ bld shift, 1 ;1 [16]
+rxbit2:
+ in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
+ andi shift, 0xf3 ;1 [18]
+ breq unstuff1 ;1 [19] do remaining work for bit 1
+didUnstuff1:
+ subi cnt, 1 ;1 [20]
+ brcs overflow ;1 [21] loop control
+ eor x2, x1 ;1 [22]
+ bst x2, USBMINUS;1 [23]
+ bld shift, 2 ;1 [24]
+ in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
+ andi shift, 0xe7 ;1 [26]
+ breq unstuff2 ;1 [27]
+didUnstuff2:
+ eor x1, x2 ;1 [28]
+ bst x1, USBMINUS;1 [29]
+ bld shift, 3 ;1 [30]
+didUnstuff3:
+ andi shift, 0xcf ;1 [31]
+ breq unstuff3 ;1 [32]
+ in x1, USBIN ;1 [33] <-- sample bit 4
+ eor x2, x1 ;1 [34]
+ bst x2, USBMINUS;1 [35]
+ bld shift, 4 ;1 [36]
+didUnstuff4:
+ andi shift, 0x9f ;1 [37]
+ breq unstuff4 ;1 [38]
+ nop2 ;2 [40]
+ in x2, USBIN ;1 [41] <-- sample bit 5
+ eor x1, x2 ;1 [42]
+ bst x1, USBMINUS;1 [43]
+ bld shift, 5 ;1 [44]
+didUnstuff5:
+ andi shift, 0x3f ;1 [45]
+ breq unstuff5 ;1 [46]
+ nop2 ;2 [48]
+ in x1, USBIN ;1 [49] <-- sample bit 6
+ eor x2, x1 ;1 [50]
+ bst x2, USBMINUS;1 [51]
+ bld shift, 6 ;1 [52]
+didUnstuff6:
+ cpi shift, 0x02 ;1 [53]
+ brlo unstuff6 ;1 [54]
+ nop2 ;2 [56]
+ in x2, USBIN ;1 [57] <-- sample bit 7
+ eor x1, x2 ;1 [58]
+ bst x1, USBMINUS;1 [59]
+ bld shift, 7 ;1 [60]
+didUnstuff7:
+ cpi shift, 0x04 ;1 [61]
+ brsh rxLoop ;2 [63] loop control
+unstuff7:
+ andi x3, ~0x80 ;1 [63]
+ ori shift, 0x80 ;1 [64]
+ in x2, USBIN ;1 [65] <-- sample stuffed bit 7
+ nop ;1 [66]
+ rjmp didUnstuff7 ;2 [68]
+
+macro POP_STANDARD ; 12 cycles
+ pop cnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+;----------------------------------------------------------------------------
+; Transmitting data
+;----------------------------------------------------------------------------
+
+txByteLoop:
+txBitloop:
+stuffN1Delay: ; [03]
+ ror shift ;[-5] [11] [59]
+ brcc doExorN1 ;[-4] [60]
+ subi x4, 1 ;[-3]
+ brne commonN1 ;[-2]
+ lsl shift ;[-1] compensate ror after rjmp stuffDelay
+ nop ;[00] stuffing consists of just waiting 8 cycles
+ rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
+
+sendNakAndReti: ;0 [-19] 19 cycles until SOP
+ ldi x3, USBPID_NAK ;1 [-18]
+ rjmp usbSendX3 ;2 [-16]
+sendAckAndReti: ;0 [-19] 19 cycles until SOP
+ ldi x3, USBPID_ACK ;1 [-18]
+ rjmp usbSendX3 ;2 [-16]
+sendCntAndReti: ;0 [-17] 17 cycles until SOP
+ mov x3, cnt ;1 [-16]
+usbSendX3: ;0 [-16]
+ ldi YL, 20 ;1 [-15] 'x3' is R20
+ ldi YH, 0 ;1 [-14]
+ ldi cnt, 2 ;1 [-13]
+; rjmp usbSendAndReti fallthrough
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
+; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
+; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte
+;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt]
+;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
+usbSendAndReti:
+ in x2, USBDDR ;[-12] 12 cycles until SOP
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ out USBDDR, x2 ;[-8] <--- acquire bus
+ in x1, USBOUT ;[-7] port mirror for tx loop
+ ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror)
+ ldi x2, USBMASK ;[-5]
+ push x4 ;[-4]
+doExorN1:
+ eor x1, x2 ;[-2] [06] [62]
+ ldi x4, 6 ;[-1] [07] [63]
+commonN1:
+stuffN2Delay:
+ out USBOUT, x1 ;[00] [08] [64] <--- set bit
+ ror shift ;[01]
+ brcc doExorN2 ;[02]
+ subi x4, 1 ;[03]
+ brne commonN2 ;[04]
+ lsl shift ;[05] compensate ror after rjmp stuffDelay
+ rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
+doExorN2:
+ eor x1, x2 ;[04] [12]
+ ldi x4, 6 ;[05] [13]
+commonN2:
+ nop ;[06] [14]
+ subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1
+ out USBOUT, x1 ;[08] [16] <--- set bit
+ brcs txBitloop ;[09] [25] [41]
+
+stuff6Delay:
+ ror shift ;[42] [50]
+ brcc doExor6 ;[43]
+ subi x4, 1 ;[44]
+ brne common6 ;[45]
+ lsl shift ;[46] compensate ror after rjmp stuffDelay
+ nop ;[47] stuffing consists of just waiting 8 cycles
+ rjmp stuff6Delay ;[48] after ror, C bit is reliably clear
+doExor6:
+ eor x1, x2 ;[45] [53]
+ ldi x4, 6 ;[46]
+common6:
+stuff7Delay:
+ ror shift ;[47] [55]
+ out USBOUT, x1 ;[48] <--- set bit
+ brcc doExor7 ;[49]
+ subi x4, 1 ;[50]
+ brne common7 ;[51]
+ lsl shift ;[52] compensate ror after rjmp stuffDelay
+ rjmp stuff7Delay ;[53] after ror, C bit is reliably clear
+doExor7:
+ eor x1, x2 ;[51] [59]
+ ldi x4, 6 ;[52]
+common7:
+ ld shift, y+ ;[53]
+ tst cnt ;[55]
+ out USBOUT, x1 ;[56] <--- set bit
+ brne txByteLoop ;[57]
+
+;make SE0:
+ cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles]
+ lds x2, usbNewDeviceAddr;[59]
+ lsl x2 ;[61] we compare with left shifted address
+ subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[63]
+ out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[01]
+ sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[04]
+ ori x1, USBIDLE ;[05]
+ in x2, USBDDR ;[06]
+ cbr x2, USBMASK ;[07] set both pins to input
+ mov x3, x1 ;[08]
+ cbr x3, USBMASK ;[09] configure no pullup on both pins
+ pop x4 ;[10]
+ nop2 ;[12]
+ nop2 ;[14]
+ out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[17] <-- release bus now
+ out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm128.inc
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2008-10-11
+ * Tabsize: 4
+ * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrvasm128.inc 692 2008-11-07 15:07:40Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 12.8 MHz version of the USB driver. It is intended for use
+with the internal RC oscillator. Although 12.8 MHz is outside the guaranteed
+calibration range of the oscillator, almost all AVRs can reach this frequency.
+This version contains a phase locked loop in the receiver routine to cope with
+slight clock rate deviations of up to +/- 1%.
+
+See usbdrv.h for a description of the entire driver.
+
+LIMITATIONS
+===========
+Although it may seem very handy to save the crystal and use the internal
+RC oscillator of the CPU, this method (and this module) has some serious
+limitations:
+(1) The guaranteed calibration range of the oscillator is only 8.1 MHz.
+They typical range is 14.5 MHz and most AVRs can actually reach this rate.
+(2) Writing EEPROM and Flash may be unreliable (short data lifetime) since
+the write procedure is timed from the RC oscillator.
+(3) End Of Packet detection is between bit 0 and bit 1 where the EOP condition
+may not be reliable when a hub is used. It should be in bit 1.
+(4) Code size is much larger than that of the other modules.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+
+Implementation notes:
+======================
+min frequency: 67 cycles for 8 bit -> 12.5625 MHz
+max frequency: 69.286 cycles for 8 bit -> 12.99 MHz
+nominal frequency: 12.77 MHz ( = sqrt(min * max))
+
+sampling positions: (next even number in range [+/- 0.5])
+cycle index range: 0 ... 66
+bits:
+.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125
+[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59]
+
+bit number: 0 1 2 3 4 5 6 7
+spare cycles 1 2 1 2 1 1 1 0
+
+operations to perform: duration cycle
+ ----------------
+ eor fix, shift 1 -> 00
+ andi phase, USBMASK 1 -> 08
+ breq se0 1 -> 16 (moved to 11)
+ st y+, data 2 -> 24, 25
+ mov data, fix 1 -> 33
+ ser data 1 -> 41
+ subi cnt, 1 1 -> 49
+ brcs overflow 1 -> 50
+
+layout of samples and operations:
+[##] = sample bit
+<##> = sample phase
+*##* = operation
+
+0: *00* [01] 02 03 04 <05> 06 07
+1: *08* [09] 10 11 12 <13> 14 15 *16*
+2: [17] 18 19 20 <21> 22 23
+3: *24* *25* [26] 27 28 29 <30> 31 32
+4: *33* [34] 35 36 37 <38> 39 40
+5: *41* [42] 43 44 45 <46> 47 48
+6: *49* *50* [51] 52 53 54 <55> 56 57 58
+7: [59] 60 61 62 <63> 64 65 66
+*****************************************************************************/
+
+/* we prefer positive expressions (do if condition) instead of negative
+ * (skip if condition), therefore use defines for skip instructions:
+ */
+#define ifioclr sbis
+#define ifioset sbic
+#define ifrclr sbrs
+#define ifrset sbrc
+
+/* The registers "fix" and "data" swap their meaning during the loop. Use
+ * defines to keep their name constant.
+ */
+#define fix x2
+#define data x1
+#undef phase /* phase has a default definition to x4 */
+#define phase x3
+
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0
+ push YL ;2 push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1
+ push YL ;2
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS ;[0]
+ rjmp foundK ;[1]
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+
+foundK:
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push YH ;[2]
+ lds YL, usbInputBufOffset;[4]
+ clr YH ;[6]
+ subi YL, lo8(-(usbRxBuf));[7]
+ sbci YH, hi8(-(usbRxBuf));[8]
+
+ sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5]
+ rjmp haveTwoBitsK ;[10]
+ pop YH ;[11] undo the push from before
+ rjmp waitForK ;[13] this was not the end of sync, retry
+haveTwoBitsK:
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+#define fix x2
+#define data x1
+
+ push shift ;[12]
+ push x1 ;[14]
+ push x2 ;[16]
+ ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0
+ ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5]
+ ori shift, 1<<0 ;[02]
+ push x3 ;[03]
+ push cnt ;[05]
+ push r0 ;[07]
+ ifioset USBIN, USBMINUS ;[09] <--- bit 1
+ ori shift, 1<<1 ;[10]
+ ser fix ;[11]
+ ldi cnt, USB_BUFSIZE ;[12]
+ mov data, shift ;[13]
+ lsl shift ;[14]
+ nop2 ;[15]
+ ifioset USBIN, USBMINUS ;[17] <--- bit 2
+ ori data, 3<<2 ;[18] store in bit 2 AND bit 3
+ eor shift, data ;[19] do nrzi decoding
+ andi data, 1<<3 ;[20]
+ in phase, USBIN ;[21] <- phase
+ brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1
+ nop ;[23]
+ rjmp entryAfterClr ;[24]
+jumpToEntryAfterSet:
+ rjmp entryAfterSet ;[24]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+#undef fix
+#define fix x1
+#undef data
+#define data x2
+
+bit7IsSet:
+ ifrclr phase, USBMINUS ;[62] check phase only if D- changed
+ lpm ;[63]
+ in phase, USBIN ;[64] <- phase (one cycle too late)
+ ori shift, 1 << 7 ;[65]
+ nop ;[66]
+;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump
+bit0AfterSet:
+ eor fix, shift ;[00]
+#undef fix
+#define fix x2
+#undef data
+#define data x1 /* we now have result in data, fix is reset to 0xff */
+ ifioclr USBIN, USBMINUS ;[01] <--- sample 0
+ rjmp bit0IsClr ;[02]
+ andi shift, ~(7 << 0) ;[03]
+ breq unstuff0s ;[04]
+ in phase, USBIN ;[05] <- phase
+ rjmp bit1AfterSet ;[06]
+unstuff0s:
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ andi fix, ~(1 << 0) ;[07]
+ ifioclr USBIN, USBMINUS ;[00]
+ ifioset USBIN, USBPLUS ;[01]
+ rjmp bit0IsClr ;[02] executed if first expr false or second true
+jumpToSe0AndStore:
+ rjmp se0AndStore ;[03] executed only if both bits 0
+bit0IsClr:
+ ifrset phase, USBMINUS ;[04] check phase only if D- changed
+ lpm ;[05]
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ ori shift, 1 << 0 ;[07]
+bit1AfterClr:
+ andi phase, USBMASK ;[08]
+ ifioset USBIN, USBMINUS ;[09] <--- sample 1
+ rjmp bit1IsSet ;[10]
+ breq jumpToSe0AndStore ;[11]
+ andi shift, ~(7 << 1) ;[12]
+ in phase, USBIN ;[13] <- phase
+ breq unstuff1c ;[14]
+ rjmp bit2AfterClr ;[15]
+unstuff1c:
+ andi fix, ~(1 << 1) ;[16]
+ nop2 ;[08]
+ nop2 ;[10]
+bit1IsSet:
+ ifrclr phase, USBMINUS ;[12] check phase only if D- changed
+ lpm ;[13]
+ in phase, USBIN ;[14] <- phase (one cycle too late)
+ ori shift, 1 << 1 ;[15]
+ nop ;[16]
+bit2AfterSet:
+ ifioclr USBIN, USBMINUS ;[17] <--- sample 2
+ rjmp bit2IsClr ;[18]
+ andi shift, ~(7 << 2) ;[19]
+ breq unstuff2s ;[20]
+ in phase, USBIN ;[21] <- phase
+ rjmp bit3AfterSet ;[22]
+unstuff2s:
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ andi fix, ~(1 << 2) ;[23]
+ nop2 ;[16]
+ nop2 ;[18]
+bit2IsClr:
+ ifrset phase, USBMINUS ;[20] check phase only if D- changed
+ lpm ;[21]
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ ori shift, 1 << 2 ;[23]
+bit3AfterClr:
+ st y+, data ;[24]
+entryAfterClr:
+ ifioset USBIN, USBMINUS ;[26] <--- sample 3
+ rjmp bit3IsSet ;[27]
+ andi shift, ~(7 << 3) ;[28]
+ breq unstuff3c ;[29]
+ in phase, USBIN ;[30] <- phase
+ rjmp bit4AfterClr ;[31]
+unstuff3c:
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ andi fix, ~(1 << 3) ;[32]
+ nop2 ;[25]
+ nop2 ;[27]
+bit3IsSet:
+ ifrclr phase, USBMINUS ;[29] check phase only if D- changed
+ lpm ;[30]
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ ori shift, 1 << 3 ;[32]
+bit4AfterSet:
+ mov data, fix ;[33] undo this move by swapping defines
+#undef fix
+#define fix x1
+#undef data
+#define data x2
+ ifioclr USBIN, USBMINUS ;[34] <--- sample 4
+ rjmp bit4IsClr ;[35]
+ andi shift, ~(7 << 4) ;[36]
+ breq unstuff4s ;[37]
+ in phase, USBIN ;[38] <- phase
+ rjmp bit5AfterSet ;[39]
+unstuff4s:
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ andi fix, ~(1 << 4) ;[40]
+ nop2 ;[33]
+ nop2 ;[35]
+bit4IsClr:
+ ifrset phase, USBMINUS ;[37] check phase only if D- changed
+ lpm ;[38]
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ ori shift, 1 << 4 ;[40]
+bit5AfterClr:
+ ser data ;[41]
+ ifioset USBIN, USBMINUS ;[42] <--- sample 5
+ rjmp bit5IsSet ;[43]
+ andi shift, ~(7 << 5) ;[44]
+ breq unstuff5c ;[45]
+ in phase, USBIN ;[46] <- phase
+ rjmp bit6AfterClr ;[47]
+unstuff5c:
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ andi fix, ~(1 << 5) ;[48]
+ nop2 ;[41]
+ nop2 ;[43]
+bit5IsSet:
+ ifrclr phase, USBMINUS ;[45] check phase only if D- changed
+ lpm ;[46]
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ ori shift, 1 << 5 ;[48]
+bit6AfterSet:
+ subi cnt, 1 ;[49]
+ brcs jumpToOverflow ;[50]
+ ifioclr USBIN, USBMINUS ;[51] <--- sample 6
+ rjmp bit6IsClr ;[52]
+ andi shift, ~(3 << 6) ;[53]
+ cpi shift, 2 ;[54]
+ in phase, USBIN ;[55] <- phase
+ brlt unstuff6s ;[56]
+ rjmp bit7AfterSet ;[57]
+
+jumpToOverflow:
+ rjmp overflow
+
+unstuff6s:
+ andi fix, ~(1 << 6) ;[50]
+ lpm ;[51]
+bit6IsClr:
+ ifrset phase, USBMINUS ;[54] check phase only if D- changed
+ lpm ;[55]
+ in phase, USBIN ;[56] <- phase (one cycle too late)
+ ori shift, 1 << 6 ;[57]
+ nop ;[58]
+bit7AfterClr:
+ ifioset USBIN, USBMINUS ;[59] <--- sample 7
+ rjmp bit7IsSet ;[60]
+ andi shift, ~(1 << 7) ;[61]
+ cpi shift, 4 ;[62]
+ in phase, USBIN ;[63] <- phase
+ brlt unstuff7c ;[64]
+ rjmp bit0AfterClr ;[65] -> [00] == [67]
+unstuff7c:
+ andi fix, ~(1 << 7) ;[58]
+ nop ;[59]
+ rjmp bit7IsSet ;[60]
+
+se0AndStore:
+ st y+, x1 ;[15/17] cycles after start of byte
+ rjmp se0 ;[17/19]
+
+bit7IsClr:
+ ifrset phase, USBMINUS ;[62] check phase only if D- changed
+ lpm ;[63]
+ in phase, USBIN ;[64] <- phase (one cycle too late)
+ ori shift, 1 << 7 ;[65]
+ nop ;[66]
+;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump
+bit0AfterClr:
+ eor fix, shift ;[00]
+#undef fix
+#define fix x2
+#undef data
+#define data x1 /* we now have result in data, fix is reset to 0xff */
+ ifioset USBIN, USBMINUS ;[01] <--- sample 0
+ rjmp bit0IsSet ;[02]
+ andi shift, ~(7 << 0) ;[03]
+ breq unstuff0c ;[04]
+ in phase, USBIN ;[05] <- phase
+ rjmp bit1AfterClr ;[06]
+unstuff0c:
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ andi fix, ~(1 << 0) ;[07]
+ ifioclr USBIN, USBMINUS ;[00]
+ ifioset USBIN, USBPLUS ;[01]
+ rjmp bit0IsSet ;[02] executed if first expr false or second true
+ rjmp se0AndStore ;[03] executed only if both bits 0
+bit0IsSet:
+ ifrclr phase, USBMINUS ;[04] check phase only if D- changed
+ lpm ;[05]
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ ori shift, 1 << 0 ;[07]
+bit1AfterSet:
+ andi phase, USBMASK ;[08]
+ ifioclr USBIN, USBMINUS ;[09] <--- sample 1
+ rjmp bit1IsClr ;[10]
+ andi shift, ~(7 << 1) ;[11]
+ breq unstuff1s ;[12]
+ in phase, USBIN ;[13] <- phase
+ nop ;[14]
+ rjmp bit2AfterSet ;[15]
+unstuff1s:
+ in phase, USBIN ;[14] <- phase (one cycle too late)
+ andi fix, ~(1 << 1) ;[15]
+ nop2 ;[08]
+ nop2 ;[10]
+bit1IsClr:
+ ifrset phase, USBMINUS ;[12] check phase only if D- changed
+ lpm ;[13]
+ in phase, USBIN ;[14] <- phase (one cycle too late)
+ breq se0AndStore ;[15] if we come from unstuff1s, Z bit is never set
+ ori shift, 1 << 1 ;[16]
+bit2AfterClr:
+ ifioset USBIN, USBMINUS ;[17] <--- sample 2
+ rjmp bit2IsSet ;[18]
+ andi shift, ~(7 << 2) ;[19]
+ breq unstuff2c ;[20]
+ in phase, USBIN ;[21] <- phase
+ rjmp bit3AfterClr ;[22]
+unstuff2c:
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ andi fix, ~(1 << 2) ;[23]
+ nop2 ;[16]
+ nop2 ;[18]
+bit2IsSet:
+ ifrclr phase, USBMINUS ;[20] check phase only if D- changed
+ lpm ;[21]
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ ori shift, 1 << 2 ;[23]
+bit3AfterSet:
+ st y+, data ;[24]
+entryAfterSet:
+ ifioclr USBIN, USBMINUS ;[26] <--- sample 3
+ rjmp bit3IsClr ;[27]
+ andi shift, ~(7 << 3) ;[28]
+ breq unstuff3s ;[29]
+ in phase, USBIN ;[30] <- phase
+ rjmp bit4AfterSet ;[31]
+unstuff3s:
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ andi fix, ~(1 << 3) ;[32]
+ nop2 ;[25]
+ nop2 ;[27]
+bit3IsClr:
+ ifrset phase, USBMINUS ;[29] check phase only if D- changed
+ lpm ;[30]
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ ori shift, 1 << 3 ;[32]
+bit4AfterClr:
+ mov data, fix ;[33] undo this move by swapping defines
+#undef fix
+#define fix x1
+#undef data
+#define data x2
+ ifioset USBIN, USBMINUS ;[34] <--- sample 4
+ rjmp bit4IsSet ;[35]
+ andi shift, ~(7 << 4) ;[36]
+ breq unstuff4c ;[37]
+ in phase, USBIN ;[38] <- phase
+ rjmp bit5AfterClr ;[39]
+unstuff4c:
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ andi fix, ~(1 << 4) ;[40]
+ nop2 ;[33]
+ nop2 ;[35]
+bit4IsSet:
+ ifrclr phase, USBMINUS ;[37] check phase only if D- changed
+ lpm ;[38]
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ ori shift, 1 << 4 ;[40]
+bit5AfterSet:
+ ser data ;[41]
+ ifioclr USBIN, USBMINUS ;[42] <--- sample 5
+ rjmp bit5IsClr ;[43]
+ andi shift, ~(7 << 5) ;[44]
+ breq unstuff5s ;[45]
+ in phase, USBIN ;[46] <- phase
+ rjmp bit6AfterSet ;[47]
+unstuff5s:
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ andi fix, ~(1 << 5) ;[48]
+ nop2 ;[41]
+ nop2 ;[43]
+bit5IsClr:
+ ifrset phase, USBMINUS ;[45] check phase only if D- changed
+ lpm ;[46]
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ ori shift, 1 << 5 ;[48]
+bit6AfterClr:
+ subi cnt, 1 ;[49]
+ brcs overflow ;[50]
+ ifioset USBIN, USBMINUS ;[51] <--- sample 6
+ rjmp bit6IsSet ;[52]
+ andi shift, ~(3 << 6) ;[53]
+ cpi shift, 2 ;[54]
+ in phase, USBIN ;[55] <- phase
+ brlt unstuff6c ;[56]
+ rjmp bit7AfterClr ;[57]
+unstuff6c:
+ andi fix, ~(1 << 6) ;[50]
+ lpm ;[51]
+bit6IsSet:
+ ifrclr phase, USBMINUS ;[54] check phase only if D- changed
+ lpm ;[55]
+ in phase, USBIN ;[56] <- phase (one cycle too late)
+ ori shift, 1 << 6 ;[57]
+bit7AfterSet:
+ ifioclr USBIN, USBMINUS ;[59] <--- sample 7
+ rjmp bit7IsClr ;[60]
+ andi shift, ~(1 << 7) ;[61]
+ cpi shift, 4 ;[62]
+ in phase, USBIN ;[63] <- phase
+ brlt unstuff7s ;[64]
+ rjmp bit0AfterSet ;[65] -> [00] == [67]
+unstuff7s:
+ andi fix, ~(1 << 7) ;[58]
+ nop ;[59]
+ rjmp bit7IsClr ;[60]
+
+macro POP_STANDARD ; 14 cycles
+ pop r0
+ pop cnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+;----------------------------------------------------------------------------
+; Transmitting data
+;----------------------------------------------------------------------------
+
+txByteLoop:
+txBitloop:
+stuffN1Delay: ; [03]
+ ror shift ;[-5] [11] [63]
+ brcc doExorN1 ;[-4] [64]
+ subi x3, 1 ;[-3]
+ brne commonN1 ;[-2]
+ lsl shift ;[-1] compensate ror after rjmp stuffDelay
+ nop ;[00] stuffing consists of just waiting 8 cycles
+ rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
+
+sendNakAndReti:
+ ldi cnt, USBPID_NAK ;[-19]
+ rjmp sendCntAndReti ;[-18]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov r0, cnt ;[-16]
+ ldi YL, 0 ;[-15] R0 address is 0
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
+; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
+; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte
+;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt]
+;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
+usbSendAndReti:
+ in x2, USBDDR ;[-10] 10 cycles until SOP
+ ori x2, USBMASK ;[-9]
+ sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups)
+ out USBDDR, x2 ;[-6] <--- acquire bus
+ in x1, USBOUT ;[-5] port mirror for tx loop
+ ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror)
+ ldi x2, USBMASK ;[-3]
+doExorN1:
+ eor x1, x2 ;[-2] [06] [62]
+ ldi x3, 6 ;[-1] [07] [63]
+commonN1:
+stuffN2Delay:
+ out USBOUT, x1 ;[00] [08] [64] <--- set bit
+ ror shift ;[01]
+ brcc doExorN2 ;[02]
+ subi x3, 1 ;[03]
+ brne commonN2 ;[04]
+ lsl shift ;[05] compensate ror after rjmp stuffDelay
+ rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
+doExorN2:
+ eor x1, x2 ;[04] [12]
+ ldi x3, 6 ;[05] [13]
+commonN2:
+ nop2 ;[06] [14]
+ subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1
+ out USBOUT, x1 ;[09] [17] <--- set bit
+ brcs txBitloop ;[10] [27] [44]
+
+stuff6Delay:
+ ror shift ;[45] [53]
+ brcc doExor6 ;[46]
+ subi x3, 1 ;[47]
+ brne common6 ;[48]
+ lsl shift ;[49] compensate ror after rjmp stuffDelay
+ nop ;[50] stuffing consists of just waiting 8 cycles
+ rjmp stuff6Delay ;[51] after ror, C bit is reliably clear
+doExor6:
+ eor x1, x2 ;[48] [56]
+ ldi x3, 6 ;[49]
+common6:
+stuff7Delay:
+ ror shift ;[50] [58]
+ out USBOUT, x1 ;[51] <--- set bit
+ brcc doExor7 ;[52]
+ subi x3, 1 ;[53]
+ brne common7 ;[54]
+ lsl shift ;[55] compensate ror after rjmp stuffDelay
+ rjmp stuff7Delay ;[56] after ror, C bit is reliably clear
+doExor7:
+ eor x1, x2 ;[54] [62]
+ ldi x3, 6 ;[55]
+common7:
+ ld shift, y+ ;[56]
+ nop ;[58]
+ tst cnt ;[59]
+ out USBOUT, x1 ;[60] [00]<--- set bit
+ brne txByteLoop ;[61] [01]
+;make SE0:
+ cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles]
+ lds x2, usbNewDeviceAddr;[03]
+ lsl x2 ;[05] we compare with left shifted address
+ subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0
+ sbci YH, 0 ;[07]
+ out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[01]
+ sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[04]
+ ori x1, USBIDLE ;[05]
+ in x2, USBDDR ;[06]
+ cbr x2, USBMASK ;[07] set both pins to input
+ mov x3, x1 ;[08]
+ cbr x3, USBMASK ;[09] configure no pullup on both pins
+ lpm ;[10]
+ lpm ;[13]
+ out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[17] <-- release bus now
+ out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
+ rjmp doReturn
+
+
+
+/*****************************************************************************
+The following PHP script generates a code skeleton for the receiver routine:
+
+<?php
+
+function printCmdBuffer($thisBit)
+{
+global $cycle;
+
+ $nextBit = ($thisBit + 1) % 8;
+ $s = ob_get_contents();
+ ob_end_clean();
+ $s = str_replace("#", $thisBit, $s);
+ $s = str_replace("@", $nextBit, $s);
+ $lines = explode("\n", $s);
+ for($i = 0; $i < count($lines); $i++){
+ $s = $lines[$i];
+ if(ereg("\\[([0-9-][0-9])\\]", $s, $regs)){
+ $c = $cycle + (int)$regs[1];
+ $s = ereg_replace("\\[[0-9-][0-9]\\]", sprintf("[%02d]", $c), $s);
+ }
+ if(strlen($s) > 0)
+ echo "$s\n";
+ }
+}
+
+function printBit($isAfterSet, $bitNum)
+{
+ ob_start();
+ if($isAfterSet){
+?>
+ ifioclr USBIN, USBMINUS ;[00] <--- sample
+ rjmp bit#IsClr ;[01]
+ andi shift, ~(7 << #) ;[02]
+ breq unstuff#s ;[03]
+ in phase, USBIN ;[04] <- phase
+ rjmp bit@AfterSet ;[05]
+unstuff#s:
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ andi fix, ~(1 << #) ;[06]
+ nop2 ;[-1]
+ nop2 ;[01]
+bit#IsClr:
+ ifrset phase, USBMINUS ;[03] check phase only if D- changed
+ lpm ;[04]
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ ori shift, 1 << # ;[06]
+<?php
+ }else{
+?>
+ ifioset USBIN, USBMINUS ;[00] <--- sample
+ rjmp bit#IsSet ;[01]
+ andi shift, ~(7 << #) ;[02]
+ breq unstuff#c ;[03]
+ in phase, USBIN ;[04] <- phase
+ rjmp bit@AfterClr ;[05]
+unstuff#c:
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ andi fix, ~(1 << #) ;[06]
+ nop2 ;[-1]
+ nop2 ;[01]
+bit#IsSet:
+ ifrclr phase, USBMINUS ;[03] check phase only if D- changed
+ lpm ;[04]
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ ori shift, 1 << # ;[06]
+<?php
+ }
+ printCmdBuffer($bitNum);
+}
+
+$bitStartCycles = array(1, 9, 17, 26, 34, 42, 51, 59);
+for($i = 0; $i < 16; $i++){
+ $bit = $i % 8;
+ $emitClrCode = ($i + (int)($i / 8)) % 2;
+ $cycle = $bitStartCycles[$bit];
+ if($emitClrCode){
+ printf("bit%dAfterClr:\n", $bit);
+ }else{
+ printf("bit%dAfterSet:\n", $bit);
+ }
+ ob_start();
+ echo " ***** ;[-1]\n";
+ printCmdBuffer($bit);
+ printBit(!$emitClrCode, $bit);
+ if($i == 7)
+ echo "\n";
+}
+
+?>
+*****************************************************************************/
--- /dev/null
+/* Name: usbdrvasm15.inc
+ * Project: AVR USB driver
+ * Author: contributed by V. Bosch
+ * Creation Date: 2007-08-06
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm15.inc 692 2008-11-07 15:07:40Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 15 MHz version of the asssembler part of the USB driver. It
+requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+;----------------------------------------------------------------------------
+; order of registers pushed:
+; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
+;----------------------------------------------------------------------------
+USB_INTR_VECTOR:
+ push YL ;2 push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1
+ push YL ;2
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;
+; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+; sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+;-------------------------------------------------------------------------------
+; The following code results in a sampling window of < 1/4 bit
+; which meets the spec.
+;-------------------------------------------------------------------------------
+waitForK: ;-
+ sbis USBIN, USBMINUS ;1 [00] <-- sample
+ rjmp foundK ;2 [01]
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+;------------------------------------------------------------------------------
+; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
+; center sampling]
+; we have 1 bit time for setup purposes, then sample again.
+; Numbers in brackets are cycles from center of first sync (double K)
+; bit after the instruction
+;------------------------------------------------------------------------------
+foundK: ;- [02]
+ lds YL, usbInputBufOffset;2 [03+04] tx loop
+ push YH ;2 [05+06]
+ clr YH ;1 [07]
+ subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
+ push shift ;2 [10+11]
+ ser shift ;1 [12]
+ sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
+ rjmp haveTwoBitsK ;2 [00] [14]
+ pop shift ;2 [15+16] undo the push from before
+ pop YH ;2 [17+18] undo the push from before
+ rjmp waitForK ;2 [19+20] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 20 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK: ;- [01]
+ push x1 ;2 [02+03]
+ push x2 ;2 [04+05]
+ push x3 ;2 [06+07]
+ push bitcnt ;2 [08+09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 0
+ bst x1, USBMINUS ;1 [01]
+ bld shift, 0 ;1 [02]
+ push cnt ;2 [03+04]
+ ldi cnt, USB_BUFSIZE ;1 [05]
+ push x4 ;2 [06+07] tx loop
+ rjmp rxLoop ;2 [08]
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+unstuff0: ;- [07] (branch taken)
+ andi x3, ~0x01 ;1 [08]
+ mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
+ in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
+ andi x2, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 1
+ ori shift, 0x01 ;1 [03] 0b00000001
+ nop ;1 [04]
+ rjmp didUnstuff0 ;2 [05]
+;-----------------------------------------------------
+unstuff1: ;- [05] (branch taken)
+ mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
+ andi x3, ~0x02 ;1 [07]
+ ori shift, 0x02 ;1 [08] 0b00000010
+ nop ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
+ andi x1, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 2
+ rjmp didUnstuff1 ;2 [03]
+;-----------------------------------------------------
+unstuff2: ;- [05] (branch taken)
+ andi x3, ~0x04 ;1 [06]
+ ori shift, 0x04 ;1 [07] 0b00000100
+ mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
+ nop ;1 [09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 3
+ andi x2, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 3
+ rjmp didUnstuff2 ;2 [03]
+;-----------------------------------------------------
+unstuff3: ;- [00] [10] (branch taken)
+ in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
+ andi x2, USBMASK ;1 [02]
+ breq se0Hop ;1 [03] SE0 check for stuffed bit 3
+ andi x3, ~0x08 ;1 [04]
+ ori shift, 0x08 ;1 [05] 0b00001000
+ rjmp didUnstuff3 ;2 [06]
+;----------------------------------------------------------------------------
+; extra jobs done during bit interval:
+;
+; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
+; overflow check, jump to the head of rxLoop
+; bit 1: SE0 check
+; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
+; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
+; bit 4: SE0 check, none
+; bit 5: SE0 check, none
+; bit 6: SE0 check, none
+; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
+;----------------------------------------------------------------------------
+rxLoop: ;- [09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
+ andi x2, USBMASK ;1 [01]
+ brne SkipSe0Hop ;1 [02]
+se0Hop: ;- [02]
+ rjmp se0 ;2 [03] SE0 check for bit 1
+SkipSe0Hop: ;- [03]
+ ser x3 ;1 [04]
+ andi shift, 0xf9 ;1 [05] 0b11111001
+ breq unstuff0 ;1 [06]
+didUnstuff0: ;- [06]
+ eor x1, x2 ;1 [07]
+ bst x1, USBMINUS ;1 [08]
+ bld shift, 1 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
+ andi x1, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 2
+ andi shift, 0xf3 ;1 [03] 0b11110011
+ breq unstuff1 ;1 [04] do remaining work for bit 1
+didUnstuff1: ;- [04]
+ eor x2, x1 ;1 [05]
+ bst x2, USBMINUS ;1 [06]
+ bld shift, 2 ;1 [07]
+ nop2 ;2 [08+09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
+ andi x2, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 3
+ andi shift, 0xe7 ;1 [03] 0b11100111
+ breq unstuff2 ;1 [04]
+didUnstuff2: ;- [04]
+ eor x1, x2 ;1 [05]
+ bst x1, USBMINUS ;1 [06]
+ bld shift, 3 ;1 [07]
+didUnstuff3: ;- [07]
+ andi shift, 0xcf ;1 [08] 0b11001111
+ breq unstuff3 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 4
+ andi x1, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 4
+ eor x2, x1 ;1 [03]
+ bst x2, USBMINUS ;1 [04]
+ bld shift, 4 ;1 [05]
+didUnstuff4: ;- [05]
+ andi shift, 0x9f ;1 [06] 0b10011111
+ breq unstuff4 ;1 [07]
+ nop2 ;2 [08+09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 5
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for bit 5
+ eor x1, x2 ;1 [03]
+ bst x1, USBMINUS ;1 [04]
+ bld shift, 5 ;1 [05]
+didUnstuff5: ;- [05]
+ andi shift, 0x3f ;1 [06] 0b00111111
+ breq unstuff5 ;1 [07]
+ nop2 ;2 [08+09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 6
+ andi x1, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for bit 6
+ eor x2, x1 ;1 [03]
+ bst x2, USBMINUS ;1 [04]
+ bld shift, 6 ;1 [05]
+didUnstuff6: ;- [05]
+ cpi shift, 0x02 ;1 [06] 0b00000010
+ brlo unstuff6 ;1 [07]
+ nop2 ;2 [08+09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 7
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for bit 7
+ eor x1, x2 ;1 [03]
+ bst x1, USBMINUS ;1 [04]
+ bld shift, 7 ;1 [05]
+didUnstuff7: ;- [05]
+ cpi shift, 0x04 ;1 [06] 0b00000100
+ brlo unstuff7 ;1 [07]
+ eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ nop ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 0
+ st y+, x3 ;2 [01+02] store data
+ eor x2, x1 ;1 [03]
+ bst x2, USBMINUS ;1 [04]
+ bld shift, 0 ;1 [05]
+ subi cnt, 1 ;1 [06]
+ brcs overflow ;1 [07]
+ rjmp rxLoop ;2 [08]
+;-----------------------------------------------------
+unstuff4: ;- [08]
+ andi x3, ~0x10 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
+ andi x1, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 4
+ ori shift, 0x10 ;1 [03]
+ rjmp didUnstuff4 ;2 [04]
+;-----------------------------------------------------
+unstuff5: ;- [08]
+ ori shift, 0x20 ;1 [09]
+ in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 5
+ andi x3, ~0x20 ;1 [03]
+ rjmp didUnstuff5 ;2 [04]
+;-----------------------------------------------------
+unstuff6: ;- [08]
+ andi x3, ~0x40 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
+ andi x1, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 6
+ ori shift, 0x40 ;1 [03]
+ rjmp didUnstuff6 ;2 [04]
+;-----------------------------------------------------
+unstuff7: ;- [08]
+ andi x3, ~0x80 ;1 [09]
+ in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 7
+ ori shift, 0x80 ;1 [03]
+ rjmp didUnstuff7 ;2 [04]
+
+macro POP_STANDARD ; 16 cycles
+ pop x4
+ pop cnt
+ pop bitcnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+;---------------------------------------------------------------------------
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+;---------------------------------------------------------------------------
+bitstuffN: ;- [04]
+ eor x1, x4 ;1 [05]
+ clr x2 ;1 [06]
+ nop ;1 [07]
+ rjmp didStuffN ;1 [08]
+;---------------------------------------------------------------------------
+bitstuff6: ;- [04]
+ eor x1, x4 ;1 [05]
+ clr x2 ;1 [06]
+ rjmp didStuff6 ;1 [07]
+;---------------------------------------------------------------------------
+bitstuff7: ;- [02]
+ eor x1, x4 ;1 [03]
+ clr x2 ;1 [06]
+ nop ;1 [05]
+ rjmp didStuff7 ;1 [06]
+;---------------------------------------------------------------------------
+sendNakAndReti: ;- [-19]
+ ldi x3, USBPID_NAK ;1 [-18]
+ rjmp sendX3AndReti ;1 [-17]
+;---------------------------------------------------------------------------
+sendAckAndReti: ;- [-17]
+ ldi cnt, USBPID_ACK ;1 [-16]
+sendCntAndReti: ;- [-16]
+ mov x3, cnt ;1 [-15]
+sendX3AndReti: ;- [-15]
+ ldi YL, 20 ;1 [-14] x3==r20 address is 20
+ ldi YH, 0 ;1 [-13]
+ ldi cnt, 2 ;1 [-12]
+; rjmp usbSendAndReti fallthrough
+;---------------------------------------------------------------------------
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We need not to match the transfer rate exactly because the spec demands
+;only 1.5% precision anyway.
+usbSendAndReti: ;- [-13] 13 cycles until SOP
+ in x2, USBDDR ;1 [-12]
+ ori x2, USBMASK ;1 [-11]
+ sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;1 [-08] port mirror for tx loop
+ out USBDDR, x2 ;1 [-07] <- acquire bus
+ ; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;1 [-06] exor mask
+ ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
+ ldi bitcnt, 6 ;1 [-04]
+txBitLoop: ;- [-04] [06]
+ sbrs shift, 0 ;1 [-03] [07]
+ eor x1, x4 ;1 [-02] [08]
+ ror shift ;1 [-01] [09]
+didStuffN: ;- [09]
+ out USBOUT, x1 ;1 [00] [10] <-- out N
+ ror x2 ;1 [01]
+ cpi x2, 0xfc ;1 [02]
+ brcc bitstuffN ;1 [03]
+ dec bitcnt ;1 [04]
+ brne txBitLoop ;1 [05]
+ sbrs shift, 0 ;1 [06]
+ eor x1, x4 ;1 [07]
+ ror shift ;1 [08]
+didStuff6: ;- [08]
+ nop ;1 [09]
+ out USBOUT, x1 ;1 [00] [10] <-- out 6
+ ror x2 ;1 [01]
+ cpi x2, 0xfc ;1 [02]
+ brcc bitstuff6 ;1 [03]
+ sbrs shift, 0 ;1 [04]
+ eor x1, x4 ;1 [05]
+ ror shift ;1 [06]
+ ror x2 ;1 [07]
+didStuff7: ;- [07]
+ ldi bitcnt, 6 ;1 [08]
+ cpi x2, 0xfc ;1 [09]
+ out USBOUT, x1 ;1 [00] [10] <-- out 7
+ brcc bitstuff7 ;1 [01]
+ ld shift, y+ ;2 [02+03]
+ dec cnt ;1 [04]
+ brne txBitLoop ;1 [05]
+makeSE0:
+ cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
+ lds x2, usbNewDeviceAddr;2 [07+08]
+ lsl x2 ;1 [09] we compare with left shifted address
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
+ subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;1 [02]
+ breq skipAddrAssign ;1 [03]
+ sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
+;----------------------------------------------------------------------------
+;end of usbDeviceAddress transfer
+skipAddrAssign: ;- [03/04]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;1 [06]
+ ori x1, USBIDLE ;1 [07]
+ in x2, USBDDR ;1 [08]
+ cbr x2, USBMASK ;1 [09] set both pins to input
+ mov x3, x1 ;1 [10]
+ cbr x3, USBMASK ;1 [11] configure no pullup on both pins
+ ldi x4, 3 ;1 [12]
+se0Delay: ;- [12] [15]
+ dec x4 ;1 [13] [16]
+ brne se0Delay ;1 [14] [17]
+ nop2 ;2 [18+19]
+ out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
+ out USBDDR, x2 ;1 [21] <--release bus now
+ out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
+ rjmp doReturn ;1 [23]
+;---------------------------------------------------------------------------
+++ /dev/null
-/* Name: usbdrvasm16.S
- * Project: AVR USB driver
- * Author: Christian Starkjohann
- * Creation Date: 2007-06-15
- * Tabsize: 4
- * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * Revision: $Id$
- */
-
-/* Do not link this file! Link usbdrvasm.S instead, which includes the
- * appropriate implementation!
- */
-
-/*
-General Description:
-This file is the 16 MHz version of the asssembler part of the USB driver. It
-requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
-oscillator).
-
-See usbdrv.h for a description of the entire driver.
-
-Since almost all of this code is timing critical, don't change unless you
-really know what you are doing! Many parts require not only a maximum number
-of CPU cycles, but even an exact number of cycles!
-*/
-
-;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
-;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
-; Numbers in brackets are clocks counted from center of last sync bit
-; when instruction starts
-
-SIG_INTERRUPT0:
-;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
- push YL ;[-25] push only what is necessary to sync with edge ASAP
- in YL, SREG ;[-23]
- push YL ;[-22]
- push YH ;[-20]
-;----------------------------------------------------------------------------
-; Synchronize with sync pattern:
-;----------------------------------------------------------------------------
-;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
-;sync up with J to K edge during sync pattern -- use fastest possible loops
-;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
-waitForJ:
- sbis USBIN, USBMINUS ;[-18] wait for D- == 1
- rjmp waitForJ
-waitForK:
-;The following code results in a sampling window of < 1/4 bit which meets the spec.
- sbis USBIN, USBMINUS ;[-15]
- rjmp foundK ;[-14]
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- rjmp sofError
-foundK: ;[-12]
-;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
-;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
-;are cycles from center of first sync (double K) bit after the instruction
- push bitcnt ;[-12]
-; [---] ;[-11]
- lds YL, usbInputBufOffset;[-10]
-; [---] ;[-9]
- clr YH ;[-8]
- subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
- sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
- push shift ;[-5]
-; [---] ;[-4]
- ldi bitcnt, 0x55 ;[-3] [rx loop init]
- sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
- rjmp haveTwoBitsK ;[-1]
- pop shift ;[0] undo the push from before
- pop bitcnt ;[2] undo the push from before
- rjmp waitForK ;[4] this was not the end of sync, retry
-; The entire loop from waitForK until rjmp waitForK above must not exceed two
-; bit times (= 21 cycles).
-
-;----------------------------------------------------------------------------
-; push more registers and initialize values while we sample the first bits:
-;----------------------------------------------------------------------------
-haveTwoBitsK:
- push x1 ;[1]
- push x2 ;[3]
- push x3 ;[5]
- ldi shift, 0 ;[7]
- ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
- push x4 ;[9] == leap
-
- in x1, USBIN ;[11] <-- sample bit 0
- andi x1, USBMASK ;[12]
- bst x1, USBMINUS ;[13]
- bld shift, 7 ;[14]
- push cnt ;[15]
- ldi leap, 0 ;[17] [rx loop init]
- ldi cnt, USB_BUFSIZE;[18] [rx loop init]
- rjmp rxbit1 ;[19] arrives at [21]
-
-;----------------------------------------------------------------------------
-; Receiver loop (numbers in brackets are cycles within byte after instr)
-;----------------------------------------------------------------------------
-
-unstuff6:
- andi x2, USBMASK ;[03]
- ori x3, 1<<6 ;[04] will not be shifted any more
- andi shift, ~0x80;[05]
- mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
- subi leap, 3 ;[07] since this is a short (10 cycle) bit, enforce leap bit
- rjmp didUnstuff6 ;[08]
-
-unstuff7:
- ori x3, 1<<7 ;[09] will not be shifted any more
- in x2, USBIN ;[00] [10] re-sample bit 7
- andi x2, USBMASK ;[01]
- andi shift, ~0x80;[02]
- subi leap, 3 ;[03] since this is a short (10 cycle) bit, enforce leap bit
- rjmp didUnstuff7 ;[04]
-
-unstuffEven:
- ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
- in x1, USBIN ;[00] [10]
- andi shift, ~0x80;[01]
- andi x1, USBMASK ;[02]
- breq se0 ;[03]
- subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
- nop ;[05]
- rjmp didUnstuffE ;[06]
-
-unstuffOdd:
- ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
- in x2, USBIN ;[00] [10]
- andi shift, ~0x80;[01]
- andi x2, USBMASK ;[02]
- breq se0 ;[03]
- subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
- nop ;[05]
- rjmp didUnstuffO ;[06]
-
-rxByteLoop:
- andi x1, USBMASK ;[03]
- eor x2, x1 ;[04]
- subi leap, 1 ;[05]
- brpl skipLeap ;[06]
- subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
- nop ;1
-skipLeap:
- subi x2, 1 ;[08]
- ror shift ;[09]
-didUnstuff6:
- cpi shift, 0xfc ;[10]
- in x2, USBIN ;[00] [11] <-- sample bit 7
- brcc unstuff6 ;[01]
- andi x2, USBMASK ;[02]
- eor x1, x2 ;[03]
- subi x1, 1 ;[04]
- ror shift ;[05]
-didUnstuff7:
- cpi shift, 0xfc ;[06]
- brcc unstuff7 ;[07]
- eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
- st y+, x3 ;[09] store data
-rxBitLoop:
- in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
- andi x1, USBMASK ;[01]
- eor x2, x1 ;[02]
- andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
- subi x2, 1 ;[04]
- ror shift ;[05]
- cpi shift, 0xfc ;[06]
- brcc unstuffEven ;[07]
-didUnstuffE:
- lsr x3 ;[08]
- lsr x3 ;[09]
-rxbit1:
- in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
- andi x2, USBMASK ;[01]
- breq se0 ;[02]
- eor x1, x2 ;[03]
- subi x1, 1 ;[04]
- ror shift ;[05]
- cpi shift, 0xfc ;[06]
- brcc unstuffOdd ;[07]
-didUnstuffO:
- subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
- brcs rxBitLoop ;[09]
-
- subi cnt, 1 ;[10]
- in x1, USBIN ;[00] [11] <-- sample bit 6
- brcc rxByteLoop ;[01]
- rjmp ignorePacket; overflow
-
-;----------------------------------------------------------------------------
-; Processing of received packet (numbers in brackets are cycles after center of SE0)
-;----------------------------------------------------------------------------
-;This is the only non-error exit point for the software receiver loop
-;we don't check any CRCs here because there is no time left.
-#define token x1
-se0:
- subi cnt, USB_BUFSIZE ;[5]
- neg cnt ;[6]
- cpi cnt, 3 ;[7]
- ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
- out USB_INTR_PENDING, x2;[9] clear pending intr and check flag later. SE0 should be over.
- brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
- sub YL, cnt ;[11]
- sbci YH, 0 ;[12]
- ld token, y ;[13]
- cpi token, USBPID_DATA0 ;[15]
- breq handleData ;[16]
- cpi token, USBPID_DATA1 ;[17]
- breq handleData ;[18]
- ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
- mov x3, x2 ;[21] store for endpoint number
- andi x2, 0x7f ;[22] x2 is now ADDR
- lds shift, usbDeviceAddr;[23]
- cp x2, shift ;[25]
-overflow: ; This is a hack: brcs overflow will never have Z flag set
- brne ignorePacket ;[26] packet for different address
- cpi token, USBPID_IN ;[27]
- breq handleIn ;[28]
- cpi token, USBPID_SETUP ;[29]
- breq handleSetupOrOut ;[30]
- cpi token, USBPID_OUT ;[31]
- breq handleSetupOrOut ;[32]
-; rjmp ignorePacket ;fallthrough, should not happen anyway.
-
-ignorePacket:
- clr shift
- sts usbCurrentTok, shift
-doReturn:
- pop cnt
- pop x4
- pop x3
- pop x2
- pop x1
- pop shift
- pop bitcnt
-sofError:
- pop YH
- pop YL
- out SREG, YL
- pop YL
- reti
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
-handleIn3:
- lds cnt, usbTxLen3 ;[43]
- sbrc cnt, 4 ;[45]
- rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
- sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf3) ;[49]
- ldi YH, hi8(usbTxBuf3) ;[50]
- rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
-#endif
-
-;Setup and Out are followed by a data packet two bit times (16 cycles) after
-;the end of SE0. The sync code allows up to 40 cycles delay from the start of
-;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
-handleSetupOrOut: ;[34]
-#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
- sbrc x3, 7 ;[34] skip if endpoint 0
- ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
-#endif
- sts usbCurrentTok, token;[36]
- pop cnt ;[38]
- pop x4 ;[40]
- pop x3 ;[42]
- pop x2 ;[44]
- pop x1 ;[46]
- pop shift ;[48]
- pop bitcnt ;[50]
- in YL, USB_INTR_PENDING;[52]
- sbrc YL, USB_INTR_PENDING_BIT;[53] check whether data is already arriving
- rjmp waitForJ ;[54] save the pops and pushes -- a new interrupt is aready pending
- rjmp sofError ;[55] not an error, but it does the pops and reti we want
-
-
-handleData:
- lds token, usbCurrentTok;[20]
- tst token ;[22]
- breq doReturn ;[23]
- lds x2, usbRxLen ;[24]
- tst x2 ;[26]
- brne sendNakAndReti ;[27]
-; 2006-03-11: The following two lines fix a problem where the device was not
-; recognized if usbPoll() was called less frequently than once every 4 ms.
- cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
- brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
- sts usbRxLen, cnt ;[30] store received data, swap buffers
- sts usbRxToken, token ;[32]
- lds x2, usbInputBufOffset;[34] swap buffers
- ldi cnt, USB_BUFSIZE ;[36]
- sub cnt, x2 ;[37]
- sts usbInputBufOffset, cnt;[38] buffers now swapped
- rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
-
-handleIn:
-;We don't send any data as long as the C code has not processed the current
-;input data and potentially updated the output data. That's more efficient
-;in terms of code size than clearing the tx buffers when a packet is received.
- lds x1, usbRxLen ;[30]
- cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
- brge sendNakAndReti ;[33] unprocessed input packet?
- ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
- sbrc x3, 7 ;[35] x3 contains addr + endpoint
- rjmp handleIn1 ;[36]
-#endif
- lds cnt, usbTxLen ;[37]
- sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
- rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
- sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf) ;[43]
- ldi YH, hi8(usbTxBuf) ;[44]
- rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
-
-; Comment about when to set usbTxLen to USBPID_NAK:
-; We should set it back when we receive the ACK from the host. This would
-; be simple to implement: One static variable which stores whether the last
-; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
-; ACK. However, we set it back immediately when we send the package,
-; assuming that no error occurs and the host sends an ACK. We save one byte
-; RAM this way and avoid potential problems with endless retries. The rest of
-; the driver assumes error-free transfers anyway.
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
-handleIn1: ;[38]
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
- ldd x2, y+2 ;[38]
- sbrc x2, 0 ;[40]
- rjmp handleIn3 ;[41]
-#endif
- lds cnt, usbTxLen1 ;[42]
- sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
- rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
- sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf1) ;[48]
- ldi YH, hi8(usbTxBuf1) ;[49]
- rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
-#endif
-
-
-; USB spec says:
-; idle = J
-; J = (D+ = 0), (D- = 1)
-; K = (D+ = 1), (D- = 0)
-; Spec allows 7.5 bit times from EOP to SOP for replies
-
-bitstuffN:
- eor x1, x4 ;[5]
- ldi x2, 0 ;[6]
- nop2 ;[7]
- nop ;[9]
- out USBOUT, x1 ;[10] <-- out
- rjmp didStuffN ;[0]
-
-bitstuff6:
- eor x1, x4 ;[4]
- ldi x2, 0 ;[5]
- nop2 ;[6] C is zero (brcc)
- rjmp didStuff6 ;[8]
-
-bitstuff7:
- eor x1, x4 ;[3]
- ldi x2, 0 ;[4]
- rjmp didStuff7 ;[5]
-
-
-sendNakAndReti:
- ldi x3, USBPID_NAK ;[-18]
- rjmp sendX3AndReti ;[-17]
-sendAckAndReti:
- ldi cnt, USBPID_ACK ;[-17]
-sendCntAndReti:
- mov x3, cnt ;[-16]
-sendX3AndReti:
- ldi YL, 20 ;[-15] x3==r20 address is 20
- ldi YH, 0 ;[-14]
- ldi cnt, 2 ;[-13]
-; rjmp usbSendAndReti fallthrough
-
-;usbSend:
-;pointer to data in 'Y'
-;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
-;uses: x1...x4, btcnt, shift, cnt, Y
-;Numbers in brackets are time since first bit of sync pattern is sent
-;We don't match the transfer rate exactly (don't insert leap cycles every third
-;byte) because the spec demands only 1.5% precision anyway.
-usbSendAndReti: ; 12 cycles until SOP
- in x2, USBDDR ;[-12]
- ori x2, USBMASK ;[-11]
- sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
- in x1, USBOUT ;[-8] port mirror for tx loop
- out USBDDR, x2 ;[-7] <- acquire bus
-; need not init x2 (bitstuff history) because sync starts with 0
- ldi x4, USBMASK ;[-6] exor mask
- ldi shift, 0x80 ;[-5] sync byte is first byte sent
-txByteLoop:
- ldi bitcnt, 0x2a ;[-4] [6] binary 00101010
-txBitLoop:
- sbrs shift, 0 ;[-3] [7]
- eor x1, x4 ;[-2] [8]
- out USBOUT, x1 ;[-1] [9] <-- out N
- ror shift ;[0] [10]
- ror x2 ;[1]
-didStuffN:
- cpi x2, 0xfc ;[2]
- brcc bitstuffN ;[3]
- lsr bitcnt ;[4]
- brcc txBitLoop ;[5]
- brne txBitLoop ;[6]
-
- sbrs shift, 0 ;[7]
- eor x1, x4 ;[8]
- ror shift ;[9]
-didStuff6:
- out USBOUT, x1 ;[-1] [10] <-- out 6
- ror x2 ;[0] [11]
- cpi x2, 0xfc ;[1]
- brcc bitstuff6 ;[2]
- sbrs shift, 0 ;[3]
- eor x1, x4 ;[4]
- ror shift ;[5]
- ror x2 ;[6]
-didStuff7:
- nop ;[7]
- nop2 ;[8]
- out USBOUT, x1 ;[-1][10] <-- out 7
- cpi x2, 0xfc ;[0] [11]
- brcc bitstuff7 ;[1]
- ld shift, y+ ;[2]
- dec cnt ;[4]
- brne txByteLoop ;[4]
-;make SE0:
- cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
- lds x2, usbNewDeviceAddr;[8]
- out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
-;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
-;set address only after data packet was sent, not after handshake
- subi YL, 2 ;[0]
- sbci YH, 0 ;[1]
- breq skipAddrAssign ;[2]
- sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
-skipAddrAssign:
-;end of usbDeviceAddress transfer
- ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
- out USB_INTR_PENDING, x2;[5]
- ori x1, USBIDLE ;[6]
- in x2, USBDDR ;[7]
- cbr x2, USBMASK ;[8] set both pins to input
- mov x3, x1 ;[9]
- cbr x3, USBMASK ;[10] configure no pullup on both pins
- ldi x4, 4 ;[11]
-se0Delay:
- dec x4 ;[12] [15] [18] [21]
- brne se0Delay ;[13] [16] [19] [22]
- out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
- out USBDDR, x2 ;[24] <-- release bus now
- out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
- rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm16.inc
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-06-15
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm16.inc 692 2008-11-07 15:07:40Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 16 MHz version of the asssembler part of the USB driver. It
+requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
+ push YL ;[-25] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-23]
+ push YL ;[-22]
+ push YH ;[-20]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-15]
+ rjmp foundK ;[-14]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-12]
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push bitcnt ;[-12]
+; [---] ;[-11]
+ lds YL, usbInputBufOffset;[-10]
+; [---] ;[-9]
+ clr YH ;[-8]
+ subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
+ push shift ;[-5]
+; [---] ;[-4]
+ ldi bitcnt, 0x55 ;[-3] [rx loop init]
+ sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
+ rjmp haveTwoBitsK ;[-1]
+ pop shift ;[0] undo the push from before
+ pop bitcnt ;[2] undo the push from before
+ rjmp waitForK ;[4] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 21 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK:
+ push x1 ;[1]
+ push x2 ;[3]
+ push x3 ;[5]
+ ldi shift, 0 ;[7]
+ ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
+ push x4 ;[9] == leap
+
+ in x1, USBIN ;[11] <-- sample bit 0
+ andi x1, USBMASK ;[12]
+ bst x1, USBMINUS ;[13]
+ bld shift, 7 ;[14]
+ push cnt ;[15]
+ ldi leap, 0 ;[17] [rx loop init]
+ ldi cnt, USB_BUFSIZE;[18] [rx loop init]
+ rjmp rxbit1 ;[19] arrives at [21]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+
+unstuff6:
+ andi x2, USBMASK ;[03]
+ ori x3, 1<<6 ;[04] will not be shifted any more
+ andi shift, ~0x80;[05]
+ mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
+ subi leap, 3 ;[07] since this is a short (10 cycle) bit, enforce leap bit
+ rjmp didUnstuff6 ;[08]
+
+unstuff7:
+ ori x3, 1<<7 ;[09] will not be shifted any more
+ in x2, USBIN ;[00] [10] re-sample bit 7
+ andi x2, USBMASK ;[01]
+ andi shift, ~0x80;[02]
+ subi leap, 3 ;[03] since this is a short (10 cycle) bit, enforce leap bit
+ rjmp didUnstuff7 ;[04]
+
+unstuffEven:
+ ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
+ in x1, USBIN ;[00] [10]
+ andi shift, ~0x80;[01]
+ andi x1, USBMASK ;[02]
+ breq se0 ;[03]
+ subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
+ nop ;[05]
+ rjmp didUnstuffE ;[06]
+
+unstuffOdd:
+ ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
+ in x2, USBIN ;[00] [10]
+ andi shift, ~0x80;[01]
+ andi x2, USBMASK ;[02]
+ breq se0 ;[03]
+ subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
+ nop ;[05]
+ rjmp didUnstuffO ;[06]
+
+rxByteLoop:
+ andi x1, USBMASK ;[03]
+ eor x2, x1 ;[04]
+ subi leap, 1 ;[05]
+ brpl skipLeap ;[06]
+ subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
+ nop ;1
+skipLeap:
+ subi x2, 1 ;[08]
+ ror shift ;[09]
+didUnstuff6:
+ cpi shift, 0xfc ;[10]
+ in x2, USBIN ;[00] [11] <-- sample bit 7
+ brcc unstuff6 ;[01]
+ andi x2, USBMASK ;[02]
+ eor x1, x2 ;[03]
+ subi x1, 1 ;[04]
+ ror shift ;[05]
+didUnstuff7:
+ cpi shift, 0xfc ;[06]
+ brcc unstuff7 ;[07]
+ eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
+ st y+, x3 ;[09] store data
+rxBitLoop:
+ in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
+ andi x1, USBMASK ;[01]
+ eor x2, x1 ;[02]
+ andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
+ subi x2, 1 ;[04]
+ ror shift ;[05]
+ cpi shift, 0xfc ;[06]
+ brcc unstuffEven ;[07]
+didUnstuffE:
+ lsr x3 ;[08]
+ lsr x3 ;[09]
+rxbit1:
+ in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
+ andi x2, USBMASK ;[01]
+ breq se0 ;[02]
+ eor x1, x2 ;[03]
+ subi x1, 1 ;[04]
+ ror shift ;[05]
+ cpi shift, 0xfc ;[06]
+ brcc unstuffOdd ;[07]
+didUnstuffO:
+ subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
+ brcs rxBitLoop ;[09]
+
+ subi cnt, 1 ;[10]
+ in x1, USBIN ;[00] [11] <-- sample bit 6
+ brcc rxByteLoop ;[01]
+ rjmp overflow
+
+macro POP_STANDARD ; 14 cycles
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop bitcnt
+ endm
+macro POP_RETI ; 7 cycles
+ pop YH
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+
+bitstuffN:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6]
+ nop2 ;[7]
+ nop ;[9]
+ out USBOUT, x1 ;[10] <-- out
+ rjmp didStuffN ;[0]
+
+bitstuff6:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6] Carry is zero due to brcc
+ rol shift ;[7] compensate for ror shift at branch destination
+ rjmp didStuff6 ;[8]
+
+bitstuff7:
+ ldi x2, 0 ;[2] Carry is zero due to brcc
+ rjmp didStuff7 ;[3]
+
+
+sendNakAndReti:
+ ldi x3, USBPID_NAK ;[-18]
+ rjmp sendX3AndReti ;[-17]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov x3, cnt ;[-16]
+sendX3AndReti:
+ ldi YL, 20 ;[-15] x3==r20 address is 20
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We don't match the transfer rate exactly (don't insert leap cycles every third
+;byte) because the spec demands only 1.5% precision anyway.
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+txByteLoop:
+ ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101
+txBitLoop:
+ sbrs shift, 0 ;[-3] [7]
+ eor x1, x4 ;[-2] [8]
+ out USBOUT, x1 ;[-1] [9] <-- out N
+ ror shift ;[0] [10]
+ ror x2 ;[1]
+didStuffN:
+ cpi x2, 0xfc ;[2]
+ brcc bitstuffN ;[3]
+ lsr bitcnt ;[4]
+ brcc txBitLoop ;[5]
+ brne txBitLoop ;[6]
+
+ sbrs shift, 0 ;[7]
+ eor x1, x4 ;[8]
+didStuff6:
+ out USBOUT, x1 ;[-1] [9] <-- out 6
+ ror shift ;[0] [10]
+ ror x2 ;[1]
+ cpi x2, 0xfc ;[2]
+ brcc bitstuff6 ;[3]
+ ror shift ;[4]
+didStuff7:
+ ror x2 ;[5]
+ sbrs x2, 7 ;[6]
+ eor x1, x4 ;[7]
+ nop ;[8]
+ cpi x2, 0xfc ;[9]
+ out USBOUT, x1 ;[-1][10] <-- out 7
+ brcc bitstuff7 ;[0] [11]
+ ld shift, y+ ;[1]
+ dec cnt ;[3]
+ brne txByteLoop ;[4]
+;make SE0:
+ cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles]
+ lds x2, usbNewDeviceAddr;[6]
+ lsl x2 ;[8] we compare with left shifted address
+ subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[10]
+ out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[0]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[2] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[3]
+ ori x1, USBIDLE ;[4]
+ in x2, USBDDR ;[5]
+ cbr x2, USBMASK ;[6] set both pins to input
+ mov x3, x1 ;[7]
+ cbr x3, USBMASK ;[8] configure no pullup on both pins
+ ldi x4, 4 ;[9]
+se0Delay:
+ dec x4 ;[10] [13] [16] [19]
+ brne se0Delay ;[11] [14] [17] [20]
+ out USBOUT, x1 ;[21] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[22] <-- release bus now
+ out USBOUT, x3 ;[23] <-- ensure no pull-up resistors are active
+ rjmp doReturn
+++ /dev/null
-/* Name: usbdrvasm165.S
- * Project: AVR USB driver
- * Author: Christian Starkjohann
- * Creation Date: 2007-04-22
- * Tabsize: 4
- * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
- * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
- * Revision: $Id$
- */
-
-/* Do not link this file! Link usbdrvasm.S instead, which includes the
- * appropriate implementation!
- */
-
-/*
-General Description:
-This file is the 16.5 MHz version of the USB driver. It is intended for the
-ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
-This version contains a phase locked loop in the receiver routine to cope with
-slight clock rate deviations of up to +/- 1%.
-
-See usbdrv.h for a description of the entire driver.
-
-Since almost all of this code is timing critical, don't change unless you
-really know what you are doing! Many parts require not only a maximum number
-of CPU cycles, but even an exact number of cycles!
-*/
-
-;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
-;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
-;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
-;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
-;nominal frequency: 16.5 MHz -> 11 cycles per bit
-; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
-; Numbers in brackets are clocks counted from center of last sync bit
-; when instruction starts
-
-
-SIG_INTERRUPT0:
-;order of registers pushed: r0, SREG [sofError], YL, YH, shift, x1, x2, x3, x4, cnt
- push r0 ;[-23] push only what is necessary to sync with edge ASAP
- in r0, SREG ;[-21]
- push r0 ;[-20]
-;----------------------------------------------------------------------------
-; Synchronize with sync pattern:
-;----------------------------------------------------------------------------
-;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
-;sync up with J to K edge during sync pattern -- use fastest possible loops
-;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
-waitForJ:
- sbis USBIN, USBMINUS ;[-18] wait for D- == 1
- rjmp waitForJ
-waitForK:
-;The following code results in a sampling window of < 1/4 bit which meets the spec.
- sbis USBIN, USBMINUS ;[-15]
- rjmp foundK ;[-14]
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- sbis USBIN, USBMINUS
- rjmp foundK
- rjmp sofError
-foundK: ;[-12]
-;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
-;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
-;are cycles from center of first sync (double K) bit after the instruction
- push YL ;[-12]
-; [---] ;[-11]
- push YH ;[-10]
-; [---] ;[-9]
- lds YL, usbInputBufOffset;[-8]
-; [---] ;[-7]
- clr YH ;[-6]
- subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
- sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
- mov r0, x2 ;[-3] [rx loop init]
- sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
- rjmp haveTwoBitsK ;[-1]
- pop YH ;[0] undo the pushes from before
- pop YL ;[2]
- rjmp waitForK ;[4] this was not the end of sync, retry
-; The entire loop from waitForK until rjmp waitForK above must not exceed two
-; bit times (= 22 cycles).
-
-;----------------------------------------------------------------------------
-; push more registers and initialize values while we sample the first bits:
-;----------------------------------------------------------------------------
-haveTwoBitsK: ;[1]
- push shift ;[1]
- push x1 ;[3]
- push x2 ;[5]
- push x3 ;[7]
- ldi shift, 0xff ;[9] [rx loop init]
- ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
-
- in x1, USBIN ;[11] <-- sample bit 0
- bst x1, USBMINUS ;[12]
- bld shift, 0 ;[13]
- push x4 ;[14] == phase
-; [---] ;[15]
- push cnt ;[16]
-; [---] ;[17]
- ldi phase, 0 ;[18] [rx loop init]
- ldi cnt, USB_BUFSIZE;[19] [rx loop init]
- rjmp rxbit1 ;[20]
-; [---] ;[21]
-
-;----------------------------------------------------------------------------
-; Receiver loop (numbers in brackets are cycles within byte after instr)
-;----------------------------------------------------------------------------
-/*
-byte oriented operations done during loop:
-bit 0: store data
-bit 1: SE0 check
-bit 2: overflow check
-bit 3: catch up
-bit 4: rjmp to achieve conditional jump range
-bit 5: PLL
-bit 6: catch up
-bit 7: jump, fixup bitstuff
-; 87 [+ 2] cycles
-------------------------------------------------------------------
-*/
-continueWithBit5:
- in x2, USBIN ;[055] <-- bit 5
- eor r0, x2 ;[056]
- or phase, r0 ;[057]
- sbrc phase, USBMINUS ;[058]
- lpm ;[059] optional nop3; modifies r0
- in phase, USBIN ;[060] <-- phase
- eor x1, x2 ;[061]
- bst x1, USBMINUS ;[062]
- bld shift, 5 ;[063]
- andi shift, 0x3f ;[064]
- in x1, USBIN ;[065] <-- bit 6
- breq unstuff5 ;[066] *** unstuff escape
- eor phase, x1 ;[067]
- eor x2, x1 ;[068]
- bst x2, USBMINUS ;[069]
- bld shift, 6 ;[070]
-didUnstuff6: ;[ ]
- in r0, USBIN ;[071] <-- phase
- cpi shift, 0x02 ;[072]
- brlo unstuff6 ;[073] *** unstuff escape
-didUnstuff5: ;[ ]
- nop2 ;[074]
-; [---] ;[075]
- in x2, USBIN ;[076] <-- bit 7
- eor x1, x2 ;[077]
- bst x1, USBMINUS ;[078]
- bld shift, 7 ;[079]
-didUnstuff7: ;[ ]
- eor r0, x2 ;[080]
- or phase, r0 ;[081]
- in r0, USBIN ;[082] <-- phase
- cpi shift, 0x04 ;[083]
- brsh rxLoop ;[084]
-; [---] ;[085]
-unstuff7: ;[ ]
- andi x3, ~0x80 ;[085]
- ori shift, 0x80 ;[086]
- in x2, USBIN ;[087] <-- sample stuffed bit 7
- nop ;[088]
- rjmp didUnstuff7 ;[089]
-; [---] ;[090]
- ;[080]
-
-unstuff5: ;[067]
- eor phase, x1 ;[068]
- andi x3, ~0x20 ;[069]
- ori shift, 0x20 ;[070]
- in r0, USBIN ;[071] <-- phase
- mov x2, x1 ;[072]
- nop ;[073]
- nop2 ;[074]
-; [---] ;[075]
- in x1, USBIN ;[076] <-- bit 6
- eor r0, x1 ;[077]
- or phase, r0 ;[078]
- eor x2, x1 ;[079]
- bst x2, USBMINUS ;[080]
- bld shift, 6 ;[081] no need to check bitstuffing, we just had one
- in r0, USBIN ;[082] <-- phase
- rjmp didUnstuff5 ;[083]
-; [---] ;[084]
- ;[074]
-
-unstuff6: ;[074]
- andi x3, ~0x40 ;[075]
- in x1, USBIN ;[076] <-- bit 6 again
- ori shift, 0x40 ;[077]
- nop2 ;[078]
-; [---] ;[079]
- rjmp didUnstuff6 ;[080]
-; [---] ;[081]
- ;[071]
-
-unstuff0: ;[013]
- eor r0, x2 ;[014]
- or phase, r0 ;[015]
- andi x2, USBMASK ;[016] check for SE0
- in r0, USBIN ;[017] <-- phase
- breq didUnstuff0 ;[018] direct jump to se0 would be too long
- andi x3, ~0x01 ;[019]
- ori shift, 0x01 ;[020]
- mov x1, x2 ;[021] mov existing sample
- in x2, USBIN ;[022] <-- bit 1 again
- rjmp didUnstuff0 ;[023]
-; [---] ;[024]
- ;[014]
-
-unstuff1: ;[024]
- eor r0, x1 ;[025]
- or phase, r0 ;[026]
- andi x3, ~0x02 ;[027]
- in r0, USBIN ;[028] <-- phase
- ori shift, 0x02 ;[029]
- mov x2, x1 ;[030]
- rjmp didUnstuff1 ;[031]
-; [---] ;[032]
- ;[022]
-
-unstuff2: ;[035]
- eor r0, x2 ;[036]
- or phase, r0 ;[037]
- andi x3, ~0x04 ;[038]
- in r0, USBIN ;[039] <-- phase
- ori shift, 0x04 ;[040]
- mov x1, x2 ;[041]
- rjmp didUnstuff2 ;[042]
-; [---] ;[043]
- ;[033]
-
-unstuff3: ;[043]
- in x2, USBIN ;[044] <-- bit 3 again
- eor r0, x2 ;[045]
- or phase, r0 ;[046]
- andi x3, ~0x08 ;[047]
- ori shift, 0x08 ;[048]
- nop ;[049]
- in r0, USBIN ;[050] <-- phase
- rjmp didUnstuff3 ;[051]
-; [---] ;[052]
- ;[042]
-
-unstuff4: ;[053]
- andi x3, ~0x10 ;[054]
- in x1, USBIN ;[055] <-- bit 4 again
- ori shift, 0x10 ;[056]
- rjmp didUnstuff4 ;[057]
-; [---] ;[058]
- ;[048]
-
-rxLoop: ;[085]
- eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
- in x1, USBIN ;[000] <-- bit 0
- st y+, x3 ;[001]
-; [---] ;[002]
- eor r0, x1 ;[003]
- or phase, r0 ;[004]
- eor x2, x1 ;[005]
- in r0, USBIN ;[006] <-- phase
- ser x3 ;[007]
- bst x2, USBMINUS ;[008]
- bld shift, 0 ;[009]
- andi shift, 0xf9 ;[010]
-rxbit1: ;[ ]
- in x2, USBIN ;[011] <-- bit 1
- breq unstuff0 ;[012] *** unstuff escape
- andi x2, USBMASK ;[013] SE0 check for bit 1
-didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
- breq se0 ;[014]
- eor r0, x2 ;[015]
- or phase, r0 ;[016]
- in r0, USBIN ;[017] <-- phase
- eor x1, x2 ;[018]
- bst x1, USBMINUS ;[019]
- bld shift, 1 ;[020]
- andi shift, 0xf3 ;[021]
-didUnstuff1: ;[ ]
- in x1, USBIN ;[022] <-- bit 2
- breq unstuff1 ;[023] *** unstuff escape
- eor r0, x1 ;[024]
- or phase, r0 ;[025]
- subi cnt, 1 ;[026] overflow check
- brcs overflow ;[027]
- in r0, USBIN ;[028] <-- phase
- eor x2, x1 ;[029]
- bst x2, USBMINUS ;[030]
- bld shift, 2 ;[031]
- andi shift, 0xe7 ;[032]
-didUnstuff2: ;[ ]
- in x2, USBIN ;[033] <-- bit 3
- breq unstuff2 ;[034] *** unstuff escape
- eor r0, x2 ;[035]
- or phase, r0 ;[036]
- eor x1, x2 ;[037]
- bst x1, USBMINUS ;[038]
- in r0, USBIN ;[039] <-- phase
- bld shift, 3 ;[040]
- andi shift, 0xcf ;[041]
-didUnstuff3: ;[ ]
- breq unstuff3 ;[042] *** unstuff escape
- nop ;[043]
- in x1, USBIN ;[044] <-- bit 4
- eor x2, x1 ;[045]
- bst x2, USBMINUS ;[046]
- bld shift, 4 ;[047]
-didUnstuff4: ;[ ]
- eor r0, x1 ;[048]
- or phase, r0 ;[049]
- in r0, USBIN ;[050] <-- phase
- andi shift, 0x9f ;[051]
- breq unstuff4 ;[052] *** unstuff escape
- rjmp continueWithBit5;[053]
-; [---] ;[054]
-
-;----------------------------------------------------------------------------
-; Processing of received packet (numbers in brackets are cycles after center of SE0)
-;----------------------------------------------------------------------------
-;This is the only non-error exit point for the software receiver loop
-;we don't check any CRCs here because there is no time left.
-#define token x1
-se0:
- subi cnt, USB_BUFSIZE ;[5]
- neg cnt ;[6]
- cpi cnt, 3 ;[7]
- ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
- out USB_INTR_PENDING, x2;[9] clear pending intr and check flag later. SE0 should be over.
- brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
- sub YL, cnt ;[11]
- sbci YH, 0 ;[12]
- ld token, y ;[13]
- cpi token, USBPID_DATA0 ;[15]
- breq handleData ;[16]
- cpi token, USBPID_DATA1 ;[17]
- breq handleData ;[18]
- ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
- mov x3, x2 ;[21] store for endpoint number
- andi x2, 0x7f ;[22] x2 is now ADDR
- lds shift, usbDeviceAddr;[23]
- cp x2, shift ;[25]
-overflow: ; This is a hack: brcs overflow will never have Z flag set
- brne ignorePacket ;[26] packet for different address
- cpi token, USBPID_IN ;[27]
- breq handleIn ;[28]
- cpi token, USBPID_SETUP ;[29]
- breq handleSetupOrOut ;[30]
- cpi token, USBPID_OUT ;[31]
- breq handleSetupOrOut ;[32]
-; rjmp ignorePacket ;fallthrough, should not happen anyway.
-
-ignorePacket:
- clr shift
- sts usbCurrentTok, shift
-doReturn:
- pop cnt
- pop x4
- pop x3
- pop x2
- pop x1
- pop shift
- pop YH
- pop YL
-sofError:
- pop r0
- out SREG, r0
- pop r0
- reti
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
-handleIn3:
- lds cnt, usbTxLen3 ;[43]
- sbrc cnt, 4 ;[45]
- rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
- sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf3) ;[49]
- ldi YH, hi8(usbTxBuf3) ;[50]
- rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
-#endif
-
-;Setup and Out are followed by a data packet two bit times (16 cycles) after
-;the end of SE0. The sync code allows up to 40 cycles delay from the start of
-;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
-handleSetupOrOut: ;[34]
-#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
- sbrc x3, 7 ;[34] skip if endpoint 0
- ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
-#endif
- sts usbCurrentTok, token;[36]
- pop cnt ;[38]
- pop x4 ;[40]
- pop x3 ;[42]
- pop x2 ;[44]
- pop x1 ;[46]
- pop shift ;[48]
- pop YH ;[50]
- pop YL ;[52]
- in r0, USB_INTR_PENDING;[54]
- sbrc r0, USB_INTR_PENDING_BIT;[55] check whether data is already arriving
- rjmp waitForJ ;[56] save the pops and pushes -- a new interrupt is aready pending
- rjmp sofError ;[57] not an error, but it does the pops and reti we want
-
-
-handleData:
- lds token, usbCurrentTok;[20]
- tst token ;[22]
- breq doReturn ;[23]
- lds x2, usbRxLen ;[24]
- tst x2 ;[26]
- brne sendNakAndReti ;[27]
-; 2006-03-11: The following two lines fix a problem where the device was not
-; recognized if usbPoll() was called less frequently than once every 4 ms.
- cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
- brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
- sts usbRxLen, cnt ;[30] store received data, swap buffers
- sts usbRxToken, token ;[32]
- lds x2, usbInputBufOffset;[34] swap buffers
- ldi cnt, USB_BUFSIZE ;[36]
- sub cnt, x2 ;[37]
- sts usbInputBufOffset, cnt;[38] buffers now swapped
- rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
-
-handleIn:
-;We don't send any data as long as the C code has not processed the current
-;input data and potentially updated the output data. That's more efficient
-;in terms of code size than clearing the tx buffers when a packet is received.
- lds x1, usbRxLen ;[30]
- cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
- brge sendNakAndReti ;[33] unprocessed input packet?
- ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
-#if USB_CFG_HAVE_INTRIN_ENDPOINT
- sbrc x3, 7 ;[35] x3 contains addr + endpoint
- rjmp handleIn1 ;[36]
-#endif
- lds cnt, usbTxLen ;[37]
- sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
- rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
- sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf) ;[43]
- ldi YH, hi8(usbTxBuf) ;[44]
- rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
-
-; Comment about when to set usbTxLen to USBPID_NAK:
-; We should set it back when we receive the ACK from the host. This would
-; be simple to implement: One static variable which stores whether the last
-; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
-; ACK. However, we set it back immediately when we send the package,
-; assuming that no error occurs and the host sends an ACK. We save one byte
-; RAM this way and avoid potential problems with endless retries. The rest of
-; the driver assumes error-free transfers anyway.
-
-#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
-handleIn1: ;[38]
-#if USB_CFG_HAVE_INTRIN_ENDPOINT3
-; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
- ldd x2, y+2 ;[38]
- sbrc x2, 0 ;[40]
- rjmp handleIn3 ;[41]
-#endif
- lds cnt, usbTxLen1 ;[42]
- sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
- rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
- sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
- ldi YL, lo8(usbTxBuf1) ;[48]
- ldi YH, hi8(usbTxBuf1) ;[49]
- rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
-#endif
-
-
-; USB spec says:
-; idle = J
-; J = (D+ = 0), (D- = 1)
-; K = (D+ = 1), (D- = 0)
-; Spec allows 7.5 bit times from EOP to SOP for replies
-
-bitstuff7:
- eor x1, x4 ;[4]
- ldi x2, 0 ;[5]
- nop2 ;[6] C is zero (brcc)
- rjmp didStuff7 ;[8]
-
-bitstuffN:
- eor x1, x4 ;[5]
- ldi x2, 0 ;[6]
- lpm ;[7] 3 cycle NOP, modifies r0
- out USBOUT, x1 ;[10] <-- out
- rjmp didStuffN ;[0]
-
-#define bitStatus x3
-
-sendNakAndReti:
- ldi cnt, USBPID_NAK ;[-19]
- rjmp sendCntAndReti ;[-18]
-sendAckAndReti:
- ldi cnt, USBPID_ACK ;[-17]
-sendCntAndReti:
- mov r0, cnt ;[-16]
- ldi YL, 0 ;[-15] R0 address is 0
- ldi YH, 0 ;[-14]
- ldi cnt, 2 ;[-13]
-; rjmp usbSendAndReti fallthrough
-
-;usbSend:
-;pointer to data in 'Y'
-;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
-;uses: x1...x4, shift, cnt, Y
-;Numbers in brackets are time since first bit of sync pattern is sent
-usbSendAndReti: ; 12 cycles until SOP
- in x2, USBDDR ;[-12]
- ori x2, USBMASK ;[-11]
- sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
- in x1, USBOUT ;[-8] port mirror for tx loop
- out USBDDR, x2 ;[-7] <- acquire bus
-; need not init x2 (bitstuff history) because sync starts with 0
- ldi x4, USBMASK ;[-6] exor mask
- ldi shift, 0x80 ;[-5] sync byte is first byte sent
- ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
-byteloop:
-bitloop:
- sbrs shift, 0 ;[8] [-3]
- eor x1, x4 ;[9] [-2]
- out USBOUT, x1 ;[10] [-1] <-- out
- ror shift ;[0]
- ror x2 ;[1]
-didStuffN:
- cpi x2, 0xfc ;[2]
- brcc bitstuffN ;[3]
- nop ;[4]
- subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
- brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
- sbrs shift, 0 ;[7]
- eor x1, x4 ;[8]
- ror shift ;[9]
-didStuff7:
- out USBOUT, x1 ;[10] <-- out
- ror x2 ;[0]
- cpi x2, 0xfc ;[1]
- brcc bitstuff7 ;[2]
- ld shift, y+ ;[3]
- dec cnt ;[5]
- brne byteloop ;[6]
-;make SE0:
- cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
- lds x2, usbNewDeviceAddr;[8]
- out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
-;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
-;set address only after data packet was sent, not after handshake
- subi YL, 2 ;[0]
- sbci YH, 0 ;[1]
- breq skipAddrAssign ;[2]
- sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
-skipAddrAssign:
-;end of usbDeviceAddress transfer
- ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
- out USB_INTR_PENDING, x2;[5]
- ori x1, USBIDLE ;[6]
- in x2, USBDDR ;[7]
- cbr x2, USBMASK ;[8] set both pins to input
- mov x3, x1 ;[9]
- cbr x3, USBMASK ;[10] configure no pullup on both pins
- ldi x4, 4 ;[11]
-se0Delay:
- dec x4 ;[12] [15] [18] [21]
- brne se0Delay ;[13] [16] [19] [22]
- out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
- out USBDDR, x2 ;[24] <-- release bus now
- out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
- rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm165.inc
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-04-22
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm165.inc 692 2008-11-07 15:07:40Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 16.5 MHz version of the USB driver. It is intended for the
+ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
+This version contains a phase locked loop in the receiver routine to cope with
+slight clock rate deviations of up to +/- 1%.
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
+;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
+;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
+;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 16.5 MHz -> 11 cycles per bit
+; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt
+ push YL ;[-23] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-21]
+ push YL ;[-20]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-15]
+ rjmp foundK ;[-14]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-12]
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push r0 ;[-12]
+; [---] ;[-11]
+ push YH ;[-10]
+; [---] ;[-9]
+ lds YL, usbInputBufOffset;[-8]
+; [---] ;[-7]
+ clr YH ;[-6]
+ subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
+ mov r0, x2 ;[-3] [rx loop init]
+ sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
+ rjmp haveTwoBitsK ;[-1]
+ pop YH ;[0] undo the pushes from before
+ pop r0 ;[2]
+ rjmp waitForK ;[4] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 22 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK: ;[1]
+ push shift ;[1]
+ push x1 ;[3]
+ push x2 ;[5]
+ push x3 ;[7]
+ ldi shift, 0xff ;[9] [rx loop init]
+ ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
+
+ in x1, USBIN ;[11] <-- sample bit 0
+ bst x1, USBMINUS ;[12]
+ bld shift, 0 ;[13]
+ push x4 ;[14] == phase
+; [---] ;[15]
+ push cnt ;[16]
+; [---] ;[17]
+ ldi phase, 0 ;[18] [rx loop init]
+ ldi cnt, USB_BUFSIZE;[19] [rx loop init]
+ rjmp rxbit1 ;[20]
+; [---] ;[21]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+/*
+byte oriented operations done during loop:
+bit 0: store data
+bit 1: SE0 check
+bit 2: overflow check
+bit 3: catch up
+bit 4: rjmp to achieve conditional jump range
+bit 5: PLL
+bit 6: catch up
+bit 7: jump, fixup bitstuff
+; 87 [+ 2] cycles
+------------------------------------------------------------------
+*/
+continueWithBit5:
+ in x2, USBIN ;[055] <-- bit 5
+ eor r0, x2 ;[056]
+ or phase, r0 ;[057]
+ sbrc phase, USBMINUS ;[058]
+ lpm ;[059] optional nop3; modifies r0
+ in phase, USBIN ;[060] <-- phase
+ eor x1, x2 ;[061]
+ bst x1, USBMINUS ;[062]
+ bld shift, 5 ;[063]
+ andi shift, 0x3f ;[064]
+ in x1, USBIN ;[065] <-- bit 6
+ breq unstuff5 ;[066] *** unstuff escape
+ eor phase, x1 ;[067]
+ eor x2, x1 ;[068]
+ bst x2, USBMINUS ;[069]
+ bld shift, 6 ;[070]
+didUnstuff6: ;[ ]
+ in r0, USBIN ;[071] <-- phase
+ cpi shift, 0x02 ;[072]
+ brlo unstuff6 ;[073] *** unstuff escape
+didUnstuff5: ;[ ]
+ nop2 ;[074]
+; [---] ;[075]
+ in x2, USBIN ;[076] <-- bit 7
+ eor x1, x2 ;[077]
+ bst x1, USBMINUS ;[078]
+ bld shift, 7 ;[079]
+didUnstuff7: ;[ ]
+ eor r0, x2 ;[080]
+ or phase, r0 ;[081]
+ in r0, USBIN ;[082] <-- phase
+ cpi shift, 0x04 ;[083]
+ brsh rxLoop ;[084]
+; [---] ;[085]
+unstuff7: ;[ ]
+ andi x3, ~0x80 ;[085]
+ ori shift, 0x80 ;[086]
+ in x2, USBIN ;[087] <-- sample stuffed bit 7
+ nop ;[088]
+ rjmp didUnstuff7 ;[089]
+; [---] ;[090]
+ ;[080]
+
+unstuff5: ;[067]
+ eor phase, x1 ;[068]
+ andi x3, ~0x20 ;[069]
+ ori shift, 0x20 ;[070]
+ in r0, USBIN ;[071] <-- phase
+ mov x2, x1 ;[072]
+ nop ;[073]
+ nop2 ;[074]
+; [---] ;[075]
+ in x1, USBIN ;[076] <-- bit 6
+ eor r0, x1 ;[077]
+ or phase, r0 ;[078]
+ eor x2, x1 ;[079]
+ bst x2, USBMINUS ;[080]
+ bld shift, 6 ;[081] no need to check bitstuffing, we just had one
+ in r0, USBIN ;[082] <-- phase
+ rjmp didUnstuff5 ;[083]
+; [---] ;[084]
+ ;[074]
+
+unstuff6: ;[074]
+ andi x3, ~0x40 ;[075]
+ in x1, USBIN ;[076] <-- bit 6 again
+ ori shift, 0x40 ;[077]
+ nop2 ;[078]
+; [---] ;[079]
+ rjmp didUnstuff6 ;[080]
+; [---] ;[081]
+ ;[071]
+
+unstuff0: ;[013]
+ eor r0, x2 ;[014]
+ or phase, r0 ;[015]
+ andi x2, USBMASK ;[016] check for SE0
+ in r0, USBIN ;[017] <-- phase
+ breq didUnstuff0 ;[018] direct jump to se0 would be too long
+ andi x3, ~0x01 ;[019]
+ ori shift, 0x01 ;[020]
+ mov x1, x2 ;[021] mov existing sample
+ in x2, USBIN ;[022] <-- bit 1 again
+ rjmp didUnstuff0 ;[023]
+; [---] ;[024]
+ ;[014]
+
+unstuff1: ;[024]
+ eor r0, x1 ;[025]
+ or phase, r0 ;[026]
+ andi x3, ~0x02 ;[027]
+ in r0, USBIN ;[028] <-- phase
+ ori shift, 0x02 ;[029]
+ mov x2, x1 ;[030]
+ rjmp didUnstuff1 ;[031]
+; [---] ;[032]
+ ;[022]
+
+unstuff2: ;[035]
+ eor r0, x2 ;[036]
+ or phase, r0 ;[037]
+ andi x3, ~0x04 ;[038]
+ in r0, USBIN ;[039] <-- phase
+ ori shift, 0x04 ;[040]
+ mov x1, x2 ;[041]
+ rjmp didUnstuff2 ;[042]
+; [---] ;[043]
+ ;[033]
+
+unstuff3: ;[043]
+ in x2, USBIN ;[044] <-- bit 3 again
+ eor r0, x2 ;[045]
+ or phase, r0 ;[046]
+ andi x3, ~0x08 ;[047]
+ ori shift, 0x08 ;[048]
+ nop ;[049]
+ in r0, USBIN ;[050] <-- phase
+ rjmp didUnstuff3 ;[051]
+; [---] ;[052]
+ ;[042]
+
+unstuff4: ;[053]
+ andi x3, ~0x10 ;[054]
+ in x1, USBIN ;[055] <-- bit 4 again
+ ori shift, 0x10 ;[056]
+ rjmp didUnstuff4 ;[057]
+; [---] ;[058]
+ ;[048]
+
+rxLoop: ;[085]
+ eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ in x1, USBIN ;[000] <-- bit 0
+ st y+, x3 ;[001]
+; [---] ;[002]
+ eor r0, x1 ;[003]
+ or phase, r0 ;[004]
+ eor x2, x1 ;[005]
+ in r0, USBIN ;[006] <-- phase
+ ser x3 ;[007]
+ bst x2, USBMINUS ;[008]
+ bld shift, 0 ;[009]
+ andi shift, 0xf9 ;[010]
+rxbit1: ;[ ]
+ in x2, USBIN ;[011] <-- bit 1
+ breq unstuff0 ;[012] *** unstuff escape
+ andi x2, USBMASK ;[013] SE0 check for bit 1
+didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
+ breq se0 ;[014]
+ eor r0, x2 ;[015]
+ or phase, r0 ;[016]
+ in r0, USBIN ;[017] <-- phase
+ eor x1, x2 ;[018]
+ bst x1, USBMINUS ;[019]
+ bld shift, 1 ;[020]
+ andi shift, 0xf3 ;[021]
+didUnstuff1: ;[ ]
+ in x1, USBIN ;[022] <-- bit 2
+ breq unstuff1 ;[023] *** unstuff escape
+ eor r0, x1 ;[024]
+ or phase, r0 ;[025]
+ subi cnt, 1 ;[026] overflow check
+ brcs overflow ;[027]
+ in r0, USBIN ;[028] <-- phase
+ eor x2, x1 ;[029]
+ bst x2, USBMINUS ;[030]
+ bld shift, 2 ;[031]
+ andi shift, 0xe7 ;[032]
+didUnstuff2: ;[ ]
+ in x2, USBIN ;[033] <-- bit 3
+ breq unstuff2 ;[034] *** unstuff escape
+ eor r0, x2 ;[035]
+ or phase, r0 ;[036]
+ eor x1, x2 ;[037]
+ bst x1, USBMINUS ;[038]
+ in r0, USBIN ;[039] <-- phase
+ bld shift, 3 ;[040]
+ andi shift, 0xcf ;[041]
+didUnstuff3: ;[ ]
+ breq unstuff3 ;[042] *** unstuff escape
+ nop ;[043]
+ in x1, USBIN ;[044] <-- bit 4
+ eor x2, x1 ;[045]
+ bst x2, USBMINUS ;[046]
+ bld shift, 4 ;[047]
+didUnstuff4: ;[ ]
+ eor r0, x1 ;[048]
+ or phase, r0 ;[049]
+ in r0, USBIN ;[050] <-- phase
+ andi shift, 0x9f ;[051]
+ breq unstuff4 ;[052] *** unstuff escape
+ rjmp continueWithBit5;[053]
+; [---] ;[054]
+
+macro POP_STANDARD ; 16 cycles
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ pop r0
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+
+bitstuff7:
+ eor x1, x4 ;[4]
+ ldi x2, 0 ;[5]
+ nop2 ;[6] C is zero (brcc)
+ rjmp didStuff7 ;[8]
+
+bitstuffN:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6]
+ lpm ;[7] 3 cycle NOP, modifies r0
+ out USBOUT, x1 ;[10] <-- out
+ rjmp didStuffN ;[0]
+
+#define bitStatus x3
+
+sendNakAndReti:
+ ldi cnt, USBPID_NAK ;[-19]
+ rjmp sendCntAndReti ;[-18]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov r0, cnt ;[-16]
+ ldi YL, 0 ;[-15] R0 address is 0
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+ ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
+byteloop:
+bitloop:
+ sbrs shift, 0 ;[8] [-3]
+ eor x1, x4 ;[9] [-2]
+ out USBOUT, x1 ;[10] [-1] <-- out
+ ror shift ;[0]
+ ror x2 ;[1]
+didStuffN:
+ cpi x2, 0xfc ;[2]
+ brcc bitstuffN ;[3]
+ nop ;[4]
+ subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
+ brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
+ sbrs shift, 0 ;[7]
+ eor x1, x4 ;[8]
+ ror shift ;[9]
+didStuff7:
+ out USBOUT, x1 ;[10] <-- out
+ ror x2 ;[0]
+ cpi x2, 0xfc ;[1]
+ brcc bitstuff7 ;[2]
+ ld shift, y+ ;[3]
+ dec cnt ;[5]
+ brne byteloop ;[6]
+;make SE0:
+ cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
+ lds x2, usbNewDeviceAddr;[8]
+ lsl x2 ;[10] we compare with left shifted address
+ out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0
+ sbci YH, 0 ;[1]
+ breq skipAddrAssign ;[2]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[5]
+ ori x1, USBIDLE ;[6]
+ in x2, USBDDR ;[7]
+ cbr x2, USBMASK ;[8] set both pins to input
+ mov x3, x1 ;[9]
+ cbr x3, USBMASK ;[10] configure no pullup on both pins
+ ldi x4, 4 ;[11]
+se0Delay:
+ dec x4 ;[12] [15] [18] [21]
+ brne se0Delay ;[13] [16] [19] [22]
+ out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[24] <-- release bus now
+ out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm20.inc
+ * Project: AVR USB driver
+ * Author: Jeroen Benschop
+ * Based on usbdrvasm16.inc from Christian Starkjohann
+ * Creation Date: 2008-03-05
+ * Tabsize: 4
+ * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm20.inc 692 2008-11-07 15:07:40Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 20 MHz version of the asssembler part of the USB driver. It
+requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+#define leap2 x3
+#ifdef __IAR_SYSTEMS_ASM__
+#define nextInst $+2
+#else
+#define nextInst .+0
+#endif
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+;register use in receive loop:
+; shift assembles the byte currently being received
+; x1 holds the D+ and D- line state
+; x2 holds the previous line state
+; x4 (leap) is used to add a leap cycle once every three bytes received
+; X3 (leap2) is used to add a leap cycle once every three stuff bits received
+; bitcnt is used to determine when a stuff bit is due
+; cnt holds the number of bytes left in the receive buffer
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
+ push YL ;[-28] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-26]
+ push YL ;[-25]
+ push YH ;[-23]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-19]
+ rjmp foundK ;[-18]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-16]
+;{3, 5} after falling D- edge, average delay: 4 cycles
+;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample
+;use 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push bitcnt ;[-16]
+; [---] ;[-15]
+ lds YL, usbInputBufOffset;[-14]
+; [---] ;[-13]
+ clr YH ;[-12]
+ subi YL, lo8(-(usbRxBuf));[-11] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init]
+ push shift ;[-9]
+; [---] ;[-8]
+ ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected
+ nop2 ;[-6]
+; [---] ;[-5]
+ ldi bitcnt, 5 ;[-4] [rx loop init]
+ sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
+ rjmp haveTwoBitsK ;[-2]
+ pop shift ;[-1] undo the push from before
+ pop bitcnt ;[1]
+ rjmp waitForK ;[3] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 27 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK:
+ push x1 ;[0]
+ push x2 ;[2]
+ push x3 ;[4] (leap2)
+ ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit
+ push x4 ;[7] == leap
+ ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received
+ push cnt ;[10]
+ ldi cnt, USB_BUFSIZE ;[12] [rx loop init]
+ ldi x2, 1<<USBPLUS ;[13] current line state is K state. D+=="1", D-=="0"
+bit0:
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ rjmp handleBit ;[2] make bit0 14 cycles long
+
+;----------------------------------------------------------------------------
+; Process bit7. However, bit 6 still may need unstuffing.
+;----------------------------------------------------------------------------
+
+b6checkUnstuff:
+ dec bitcnt ;[9]
+ breq unstuff6 ;[10]
+bit7:
+ subi cnt, 1 ;[11] cannot use dec becaus it does not affect the carry flag
+ brcs overflow ;[12] Too many bytes received. Ignore packet
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ cpse x1, x2 ;[2] when previous line state equals current line state, handle "1"
+ rjmp b7handle0 ;[3] when line state differs, handle "0"
+ sec ;[4]
+ ror shift ;[5] shift "1" into the data
+ st y+, shift ;[6] store the data into the buffer
+ ldi shift, 0x40 ;[7] reset data for receiving the next byte
+ subi leap, 0x55 ;[9] trick to introduce a leap cycle every 3 bytes
+ brcc nextInst ;[10 or 11] it will fail after 85 bytes. However low speed can only receive 11
+ dec bitcnt ;[11 or 12]
+ brne bit0 ;[12 or 13]
+ ldi x1, 1 ;[13 or 14] unstuffing bit 7
+ in bitcnt, USBIN ;[0] sample stuff bit
+ rjmp unstuff ;[1]
+
+b7handle0:
+ mov x2,x1 ;[5] Set x2 to current line state
+ ldi bitcnt, 6 ;[6]
+ lsr shift ;[7] shift "0" into the data
+ st y+, shift ;[8] store data into the buffer
+ ldi shift, 0x40 ;[10] reset data for receiving the next byte
+ subi leap, 0x55 ;[11] trick to introduce a leap cycle every 3 bytes
+ brcs bit0 ;[12] it will fail after 85 bytes. However low speed can only receive 11
+ rjmp bit0 ;[13]
+
+
+;----------------------------------------------------------------------------
+; Handle unstuff
+; x1==0xFF indicate unstuffing bit6
+;----------------------------------------------------------------------------
+
+unstuff6:
+ ldi x1,0xFF ;[12] indicate unstuffing bit 6
+ in bitcnt, USBIN ;[0] sample stuff bit
+ nop ;[1] fix timing
+unstuff: ;b0-5 b6 b7
+ mov x2,bitcnt ;[3] [2] [3] Set x2 to match line state
+ subi leap2, 0x55 ;[4] [3] [4] delay loop
+ brcs nextInst ;[5] [4] [5] add one cycle every three stuff bits
+ sbci leap2,0 ;[6] [5] [6]
+ ldi bitcnt,6 ;[7] [6] [7] reset bit stuff counter
+ andi x2, USBMASK ;[8] [7] [8] only keep D+ and D-
+ cpi x1,0 ;[9] [8] [9]
+ brmi bit7 ;[10] [9] [10] finished unstuffing bit6 When x1<0
+ breq bitloop ;[11] --- [11] finished unstuffing bit0-5 when x1=0
+ nop ;--- --- [12]
+ in x1, USBIN ;--- --- [0] sample line state for bit0
+ andi x1, USBMASK ;--- --- [1] filter only D+ and D- bits
+ rjmp handleBit ;--- --- [2] make bit0 14 cycles long
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+bitloop:
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ breq se0 ;[2] both lines are low so handle se0
+handleBit:
+ cpse x1, x2 ;[3] when previous line state equals current line state, handle "1"
+ rjmp handle0 ;[4] when line state differs, handle "0"
+ sec ;[5]
+ ror shift ;[6] shift "1" into the data
+ brcs b6checkUnstuff ;[7] When after shift C is set, next bit is bit7
+ nop2 ;[8]
+ dec bitcnt ;[10]
+ brne bitloop ;[11]
+ ldi x1,0 ;[12] indicate unstuff for bit other than bit6 or bit7
+ in bitcnt, USBIN ;[0] sample stuff bit
+ rjmp unstuff ;[1]
+
+handle0:
+ mov x2, x1 ;[6] Set x2 to current line state
+ ldi bitcnt, 6 ;[7] reset unstuff counter.
+ lsr shift ;[8] shift "0" into the data
+ brcs bit7 ;[9] When after shift C is set, next bit is bit7
+ nop ;[10]
+ rjmp bitloop ;[11]
+
+;----------------------------------------------------------------------------
+; End of receive loop. Now start handling EOP
+;----------------------------------------------------------------------------
+
+macro POP_STANDARD ; 14 cycles
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop bitcnt
+ endm
+macro POP_RETI ; 7 cycles
+ pop YH
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+
+
+#include "asmcommon.inc"
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+; 7.5 bit times is 100 cycles. This implementation arrives a bit later at se0
+; then specified in the include file but there is plenty of time
+
+bitstuffN:
+ eor x1, x4 ;[8]
+ ldi x2, 0 ;[9]
+ nop2 ;[10]
+ out USBOUT, x1 ;[12] <-- out
+ rjmp didStuffN ;[0]
+
+bitstuff7:
+ eor x1, x4 ;[6]
+ ldi x2, 0 ;[7] Carry is zero due to brcc
+ rol shift ;[8] compensate for ror shift at branch destination
+ nop2 ;[9]
+ rjmp didStuff7 ;[11]
+
+sendNakAndReti:
+ ldi x3, USBPID_NAK ;[-18]
+ rjmp sendX3AndReti ;[-17]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov x3, cnt ;[-16]
+sendX3AndReti:
+ ldi YL, 20 ;[-15] x3==r20 address is 20
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We don't match the transfer rate exactly (don't insert leap cycles every third
+;byte) because the spec demands only 1.5% precision anyway.
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+txByteLoop:
+ ldi bitcnt, 0x49 ;[-4] [10] binary 01001001
+txBitLoop:
+ sbrs shift, 0 ;[-3] [10] [11]
+ eor x1, x4 ;[-2] [11] [12]
+ out USBOUT, x1 ;[-1] [12] [13] <-- out N
+ ror shift ;[0] [13] [14]
+ ror x2 ;[1]
+didStuffN:
+ nop2 ;[2]
+ nop ;[4]
+ cpi x2, 0xfc ;[5]
+ brcc bitstuffN ;[6]
+ lsr bitcnt ;[7]
+ brcc txBitLoop ;[8]
+ brne txBitLoop ;[9]
+
+ sbrs shift, 0 ;[10]
+ eor x1, x4 ;[11]
+didStuff7:
+ out USBOUT, x1 ;[-1] [13] <-- out 7
+ ror shift ;[0] [14]
+ ror x2 ;[1]
+ nop ;[2]
+ cpi x2, 0xfc ;[3]
+ brcc bitstuff7 ;[4]
+ ld shift, y+ ;[5]
+ dec cnt ;[7]
+ brne txByteLoop ;[8]
+;make SE0:
+ cbr x1, USBMASK ;[9] prepare SE0 [spec says EOP may be 25 to 30 cycles]
+ lds x2, usbNewDeviceAddr;[10]
+ lsl x2 ;[12] we compare with left shifted address
+ out USBOUT, x1 ;[13] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+ subi YL, 20 + 2 ;[0] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[1]
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[2]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[5]
+ ori x1, USBIDLE ;[6]
+ in x2, USBDDR ;[7]
+ cbr x2, USBMASK ;[8] set both pins to input
+ mov x3, x1 ;[9]
+ cbr x3, USBMASK ;[10] configure no pullup on both pins
+ ldi x4, 5 ;[11]
+se0Delay:
+ dec x4 ;[12] [15] [18] [21] [24]
+ brne se0Delay ;[13] [16] [19] [22] [25]
+ out USBOUT, x1 ;[26] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[27] <-- release bus now
+ out USBOUT, x3 ;[28] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbportability.h
+ * Project: AVR USB driver
+ * Author: Christian Starkjohann
+ * Creation Date: 2008-06-17
+ * Tabsize: 4
+ * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbportability.h 692 2008-11-07 15:07:40Z cs $
+ */
+
+/*
+General Description:
+This header is intended to contain all (or at least most of) the compiler
+and library dependent stuff. The C code is written for avr-gcc and avr-libc.
+The API of other development environments is converted to gcc's and avr-libc's
+API by means of defines.
+
+This header also contains all system includes since they depend on the
+development environment.
+
+Thanks to Oleg Semyonov for his help with the IAR tools port!
+*/
+
+#ifndef __usbportability_h_INCLUDED__
+#define __usbportability_h_INCLUDED__
+
+/* We check explicitly for IAR and CodeVision. Default is avr-gcc/avr-libc. */
+
+/* ------------------------------------------------------------------------- */
+#if defined __IAR_SYSTEMS_ICC__ || defined __IAR_SYSTEMS_ASM__ /* check for IAR */
+/* ------------------------------------------------------------------------- */
+
+#ifndef ENABLE_BIT_DEFINITIONS
+# define ENABLE_BIT_DEFINITIONS 1 /* Enable bit definitions */
+#endif
+
+/* Include IAR headers */
+#include <ioavr.h>
+#ifndef __IAR_SYSTEMS_ASM__
+# include <inavr.h>
+#endif
+
+#define __attribute__(arg) /* not supported on IAR */
+
+#ifdef __IAR_SYSTEMS_ASM__
+# define __ASSEMBLER__ /* IAR does not define standard macro for asm */
+#endif
+
+#ifdef __HAS_ELPM__
+# define PROGMEM __farflash
+#else
+# define PROGMEM __flash
+#endif
+
+#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr))
+
+/* The following definitions are not needed by the driver, but may be of some
+ * help if you port a gcc based project to IAR.
+ */
+#define cli() __disable_interrupt()
+#define sei() __enable_interrupt()
+#define wdt_reset() __watchdog_reset()
+#define _BV(x) (1 << (x))
+
+/* assembler compatibility macros */
+#define nop2 rjmp $+2 /* jump to next instruction */
+#define XL r26
+#define XH r27
+#define YL r28
+#define YH r29
+#define ZL r30
+#define ZH r31
+#define lo8(x) LOW(x)
+#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */
+
+/* Depending on the device you use, you may get problems with the way usbdrv.h
+ * handles the differences between devices. Since IAR does not use #defines
+ * for MCU registers, we can't check for the existence of a particular
+ * register with an #ifdef. If the autodetection mechanism fails, include
+ * definitions for the required USB_INTR_* macros in your usbconfig.h. See
+ * usbconfig-prototype.h and usbdrv.h for details.
+ */
+
+/* ------------------------------------------------------------------------- */
+#elif __CODEVISIONAVR__ /* check for CodeVision AVR */
+/* ------------------------------------------------------------------------- */
+/* This port is not working (yet) */
+
+/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */
+
+#include <io.h>
+#include <delay.h>
+
+#define __attribute__(arg) /* not supported on IAR */
+
+#define PROGMEM __flash
+#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr))
+
+#ifndef __ASSEMBLER__
+static inline void cli(void)
+{
+ #asm("cli");
+}
+static inline void sei(void)
+{
+ #asm("sei");
+}
+#endif
+#define _delay_ms(t) delay_ms(t)
+#define _BV(x) (1 << (x))
+#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */
+
+#define macro .macro
+#define endm .endmacro
+#define nop2 rjmp .+0 /* jump to next instruction */
+
+/* ------------------------------------------------------------------------- */
+#else /* default development environment is avr-gcc/avr-libc */
+/* ------------------------------------------------------------------------- */
+
+#include <avr/io.h>
+#ifdef __ASSEMBLER__
+# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */
+#else
+# include <avr/pgmspace.h>
+#endif
+
+#define USB_READ_FLASH(addr) pgm_read_byte(addr)
+
+#define macro .macro
+#define endm .endm
+#define nop2 rjmp .+0 /* jump to next instruction */
+
+#endif /* development environment */
+
+/* for conveniecne, ensure that PRG_RDB exists */
+#ifndef PRG_RDB
+# define PRG_RDB(addr) USB_READ_FLASH(addr)
+#endif
+#endif /* __usbportability_h_INCLUDED__ */
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