#define SoftUSART_BitCount GPIOR2\r
\r
\r
-/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r
-ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
+/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */\r
+ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
- BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
+ BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
return;\r
\r
/* Check to see if we are at a rising or falling edge of the clock */\r
- if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)\r
+ if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
{\r
/* If at rising clock edge and we are in send mode, abort */\r
if (IsSending)\r
return;\r
\r
/* Wait for the start bit when receiving */\r
- if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))\r
+ if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
return;\r
\r
/* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
* be discarded leaving the data to be byte-aligned for quick access */\r
- if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)\r
- SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1));\r
+ if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
+ ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
SoftUSART_Data >>= 1;\r
SoftUSART_BitCount--;\r
return;\r
\r
/* Set the data line to the next bit value */\r
- if (SoftUSART_Data & 0x01)\r
- BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
+ if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)\r
+ BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
else\r
- BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK; \r
+ BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; \r
\r
SoftUSART_Data >>= 1;\r
SoftUSART_BitCount--;\r
}\r
}\r
\r
-/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */\r
-ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
+/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r
+ISR(TIMER1_COMPB_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
- BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+ BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
return;\r
\r
/* Check to see if we are at a rising or falling edge of the clock */\r
- if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
+ if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)\r
{\r
/* If at rising clock edge and we are in send mode, abort */\r
if (IsSending)\r
return;\r
\r
/* Wait for the start bit when receiving */\r
- if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
+ if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))\r
return;\r
\r
/* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
* be discarded leaving the data to be byte-aligned for quick access */\r
- if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
- SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1));\r
+ if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)\r
+ ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
SoftUSART_Data >>= 1;\r
SoftUSART_BitCount--;\r
return;\r
\r
/* Set the data line to the next bit value */\r
- if (SoftUSART_Data & 0x01)\r
- BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
+ if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)\r
+ BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
else\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; \r
+ BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK; \r
\r
SoftUSART_Data >>= 1;\r
SoftUSART_BitCount--;\r
}\r
#endif\r
\r
-/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */\r
-void XPROGTarget_EnableTargetTPI(void)\r
+/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */\r
+void XPROGTarget_EnableTargetPDI(void)\r
{\r
- /* Set /RESET line low for at least 90ns to enable TPI functionality */\r
- RESET_LINE_DDR |= RESET_LINE_MASK;\r
- RESET_LINE_PORT &= ~RESET_LINE_MASK;\r
- asm volatile ("NOP"::);\r
- asm volatile ("NOP"::);\r
-\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
- \r
+ \r
+ /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
+ PORTD |= (1 << 3);\r
+ asm volatile ("NOP"::);\r
+ asm volatile ("NOP"::);\r
+ \r
/* Set up the synchronous USART for XMEGA communications - \r
8 data bits, even parity, 2 stop bits */\r
UBRR1 = (F_CPU / 1000000UL);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
\r
- /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
+ /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
XPROGTarget_SendBreak();\r
XPROGTarget_SendBreak();\r
#else\r
/* Set DATA and CLOCK lines to outputs */\r
- BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;\r
- BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;\r
+ BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;\r
+ BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;\r
\r
- /* Set DATA line high for idle state */\r
- BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
+ /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
+ BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
+ asm volatile ("NOP"::);\r
+ asm volatile ("NOP"::);\r
\r
- /* Fire timer capture ISR every 100 cycles to manage the software USART */\r
- OCR1A = 100;\r
- TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << ICIE1);\r
+ /* Fire timer compare channel A ISR every 90 cycles to manage the software USART */\r
+ OCR1A = 90;\r
+ TCCR1B = (1 << WGM12) | (1 << CS10);\r
+ TIMSK1 = (1 << OCIE1A);\r
\r
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
XPROGTarget_SendBreak();\r
#endif\r
}\r
\r
-/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */\r
-void XPROGTarget_EnableTargetPDI(void)\r
+/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */\r
+void XPROGTarget_EnableTargetTPI(void)\r
{\r
+ /* Set /RESET line low for at least 90ns to enable TPI functionality */\r
+ RESET_LINE_DDR |= RESET_LINE_MASK;\r
+ RESET_LINE_PORT &= ~RESET_LINE_MASK;\r
+ asm volatile ("NOP"::);\r
+ asm volatile ("NOP"::);\r
+\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
- \r
- /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
- PORTD |= (1 << 3);\r
- asm volatile ("NOP"::);\r
- asm volatile ("NOP"::);\r
- \r
+ \r
/* Set up the synchronous USART for XMEGA communications - \r
8 data bits, even parity, 2 stop bits */\r
UBRR1 = (F_CPU / 1000000UL);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
\r
- /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
+ /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
XPROGTarget_SendBreak();\r
XPROGTarget_SendBreak();\r
#else\r
/* Set DATA and CLOCK lines to outputs */\r
- BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;\r
+ BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;\r
+ BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;\r
\r
- /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
- BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- asm volatile ("NOP"::);\r
- asm volatile ("NOP"::);\r
+ /* Set DATA line high for idle state */\r
+ BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
\r
- /* Fire timer compare ISR every 100 cycles to manage the software USART */\r
- OCR1A = 100;\r
+ /* Fire timer capture channel B ISR every 90 cycles to manage the software USART */\r
+ OCR1B = 9;\r
TCCR1B = (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << OCIE1A);\r
+ TIMSK1 = (1 << OCIE1B);\r
\r
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
XPROGTarget_SendBreak();\r
#endif\r
}\r
\r
-/** Disables the target's TPI interface, exits programming mode and starts the target's application. */\r
-void XPROGTarget_DisableTargetTPI(void)\r
+/** Disables the target's PDI interface, exits programming mode and starts the target's application. */\r
+void XPROGTarget_DisableTargetPDI(void)\r
{\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
/* Set DATA and CLOCK lines to inputs */\r
- BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
- BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
+ BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
+ BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;\r
\r
/* Tristate DATA and CLOCK lines */\r
- BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
- BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;\r
+ BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
+ BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;\r
#endif\r
-\r
- /* Tristate target /RESET line */\r
- RESET_LINE_DDR &= ~RESET_LINE_MASK;\r
- RESET_LINE_PORT &= ~RESET_LINE_MASK;\r
}\r
\r
-/** Disables the target's PDI interface, exits programming mode and starts the target's application. */\r
-void XPROGTarget_DisableTargetPDI(void)\r
+/** Disables the target's TPI interface, exits programming mode and starts the target's application. */\r
+void XPROGTarget_DisableTargetTPI(void)\r
{\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
/* Set DATA and CLOCK lines to inputs */\r
- BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;\r
+ BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
+ BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
\r
/* Tristate DATA and CLOCK lines */\r
- BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;\r
+ BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
+ BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;\r
#endif\r
+\r
+ /* Tristate target /RESET line */\r
+ RESET_LINE_DDR &= ~RESET_LINE_MASK;\r
+ RESET_LINE_PORT &= ~RESET_LINE_MASK;\r
}\r
\r
/** Sends a byte via the USART.\r
projects / pub / USBasp.git / blobdiff