Fix mistakes in the XPROGTarget.c/.h files for TPI mode software USART clock rate...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index 7908c65..29397a6 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -145,6 +145,8 @@ ISR(TIMER1_COMPB_vect, ISR_BLOCK)
 /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */\r
 void XPROGTarget_EnableTargetPDI(void)\r
 {\r
+       IsSending = false;\r
+\r
 #if defined(XPROG_VIA_HARDWARE_USART)\r
        /* Set Tx and XCK as outputs, Rx as input */\r
        DDRD |=  (1 << 5) | (1 << 3);\r
@@ -160,10 +162,6 @@ void XPROGTarget_EnableTargetPDI(void)
        UBRR1  = (F_CPU / 1000000UL);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
-\r
-       /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
-       XPROGTarget_SendBreak();\r
-       XPROGTarget_SendBreak();\r
 #else\r
        /* Set DATA and CLOCK lines to outputs */\r
        BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;\r
@@ -174,20 +172,22 @@ void XPROGTarget_EnableTargetPDI(void)
        asm volatile ("NOP"::);\r
        asm volatile ("NOP"::);\r
 \r
-       /* Fire timer compare channel A ISR every 90 cycles to manage the software USART */\r
-       OCR1A   = 90;\r
+       /* Fire timer compare channel A ISR to manage the software USART */\r
+       OCR1A   = BITS_BETWEEN_USART_CLOCKS;\r
        TCCR1B  = (1 << WGM12) | (1 << CS10);\r
        TIMSK1  = (1 << OCIE1A);\r
-       \r
-       /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
+#endif\r
+\r
+       /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
        XPROGTarget_SendBreak();\r
        XPROGTarget_SendBreak();\r
-#endif\r
 }\r
 \r
 /** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */\r
 void XPROGTarget_EnableTargetTPI(void)\r
 {\r
+       IsSending = false;\r
+\r
        /* Set /RESET line low for at least 90ns to enable TPI functionality */\r
        RESET_LINE_DDR  |= RESET_LINE_MASK;\r
        RESET_LINE_PORT &= ~RESET_LINE_MASK;\r
@@ -204,10 +204,6 @@ void XPROGTarget_EnableTargetTPI(void)
        UBRR1  = (F_CPU / 1000000UL);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
-\r
-       /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
-       XPROGTarget_SendBreak();\r
-       XPROGTarget_SendBreak();\r
 #else\r
        /* Set DATA and CLOCK lines to outputs */\r
        BITBANG_TPIDATA_DDR  |= BITBANG_TPIDATA_MASK;\r
@@ -216,15 +212,15 @@ void XPROGTarget_EnableTargetTPI(void)
        /* Set DATA line high for idle state */\r
        BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
 \r
-       /* Fire timer capture channel B ISR every 90 cycles to manage the software USART */\r
-       OCR1B   = 9;\r
+       /* Fire timer capture channel B ISR to manage the software USART */\r
+       OCR1B   = BITS_BETWEEN_USART_CLOCKS;\r
        TCCR1B  = (1 << WGM12) | (1 << CS10);\r
        TIMSK1  = (1 << OCIE1B);\r
-       \r
+#endif\r
+\r
        /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
        XPROGTarget_SendBreak();\r
        XPROGTarget_SendBreak();\r
-#endif\r
 }\r
 \r
 /** Disables the target's PDI interface, exits programming mode and starts the target's application. */\r