*\r
* \param[in] Register NVM register whose absolute address is to be sent\r
*/\r
-void NVMTarget_SendNVMRegAddress(uint8_t Register)\r
+void NVMTarget_SendNVMRegAddress(const uint8_t Register)\r
{\r
/* Determine the absolute register address from the NVM base memory address and the NVM register address */\r
uint32_t Address = XPROG_Param_NVMBase | Register;\r
\r
/* Send the calculated 32-bit address to the target, LSB first */\r
- PDITarget_SendByte(Address & 0xFF);\r
- PDITarget_SendByte(Address >> 8);\r
- PDITarget_SendByte(Address >> 16);\r
- PDITarget_SendByte(Address >> 24);\r
+ NVMTarget_SendAddress(Address);\r
}\r
\r
/** Sends the given 32-bit absolute address to the target.\r
*\r
* \param[in] AbsoluteAddress Absolute address to send to the target\r
*/\r
-void NVMTarget_SendAddress(uint32_t AbsoluteAddress)\r
+void NVMTarget_SendAddress(const uint32_t AbsoluteAddress)\r
{\r
/* Send the given 32-bit address to the target, LSB first */\r
PDITarget_SendByte(AbsoluteAddress & 0xFF);\r
bool NVMTarget_WaitWhileNVMControllerBusy(void)\r
{\r
TCNT0 = 0;\r
-\r
+ TIFR0 = (1 << OCF1A);\r
+ \r
+ uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS;\r
+ \r
/* Poll the NVM STATUS register while the NVM controller is busy */\r
- while (TCNT0 < NVM_BUSY_TIMEOUT_MS)\r
+ while (TimeoutMS)\r
{\r
/* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
/* Check to see if the BUSY flag is still set */\r
if (!(PDITarget_ReceiveByte() & (1 << 7)))\r
return true;\r
+\r
+ if (TIFR0 & (1 << OCF1A))\r
+ {\r
+ TIFR0 = (1 << OCF1A);\r
+ TimeoutMS--;\r
+ }\r
}\r
\r
return false;\r
* \param[in] CRCCommand NVM CRC command to issue to the target\r
* \param[out] CRCDest CRC Destination when read from the target\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
-bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)\r
+bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
* \param[out] ReadBuffer Buffer to store read data into\r
* \param[in] ReadSize Number of bytes to read\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
-bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)\r
+bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
return false;\r
\r
- /* Send the READNVM command to the NVM controller for reading of an aribtrary location */\r
+ /* Send the READNVM command to the NVM controller for reading of an arbitrary location */\r
PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
PDITarget_SendByte(NVM_CMD_READNVM);\r
NVMTarget_SendAddress(ReadAddress);\r
\r
/* Send the REPEAT command with the specified number of bytes to read */\r
- PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);\r
- PDITarget_SendByte(ReadSize & 0xFF);\r
- PDITarget_SendByte(ReadSize >> 8);\r
+ PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+ PDITarget_SendByte(ReadSize - 1);\r
\r
/* Send a LD command with indirect access and postincrement to read out the bytes */\r
PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
* \param[in] WriteCommand Command to send to the device to write each memory byte\r
* \param[in] WriteAddress Start address to write to within the target's address space\r
* \param[in] WriteBuffer Buffer to source data from\r
- * \param[in] WriteSize Number of bytes to write\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
-bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)\r
+bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)\r
{\r
- for (uint16_t i = 0; i < WriteSize; i++)\r
- {\r
- /* Wait until the NVM controller is no longer busy */\r
- if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
- return false;\r
+ /* Wait until the NVM controller is no longer busy */\r
+ if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+ return false;\r
\r
- /* Send the memory write command to the target */\r
- PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
- PDITarget_SendByte(WriteCommand);\r
+ /* Send the memory write command to the target */\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+ NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+ PDITarget_SendByte(WriteCommand);\r
\r
- /* Send each new memory byte to the memory to the target */\r
- PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendAddress(WriteAddress++);\r
- PDITarget_SendByte(*(WriteBuffer++));\r
- }\r
+ /* Send new memory byte to the memory to the target */\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+ NVMTarget_SendAddress(WriteAddress);\r
+ PDITarget_SendByte(*(WriteBuffer++));\r
\r
return true;\r
}\r
* \param[in] WriteBuffer Buffer to source data from\r
* \param[in] WriteSize Number of bytes to write\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
-bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,\r
- uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)\r
+bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand,\r
+ const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,\r
+ const uint8_t* WriteBuffer, const uint16_t WriteSize)\r
{\r
if (PageMode & XPRG_PAGEMODE_ERASE)\r
{\r
NVMTarget_SendAddress(WriteAddress);\r
\r
/* Send the REPEAT command with the specified number of bytes to write */\r
- PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);\r
- PDITarget_SendByte(WriteSize & 0xFF);\r
- PDITarget_SendByte(WriteSize >> 8);\r
+ PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+ PDITarget_SendByte(WriteSize - 1);\r
\r
/* Send a ST command with indirect access and postincrement to write the bytes */\r
PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
for (uint16_t i = 0; i < WriteSize; i++)\r
PDITarget_SendByte(*(WriteBuffer++));\r
-\r
- // TEMP\r
- PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
- GPIOR0 = PDITarget_ReceiveByte();\r
- if (!(GPIOR0 & (1 << 0)))\r
- JTAG_DEBUG_POINT();\r
- // END TEMP\r
}\r
\r
if (PageMode & XPRG_PAGEMODE_WRITE)\r
* \param[in] EraseCommand NVM erase command to send to the device\r
* \param[in] Address Address inside the memory space to erase\r
*\r
- * \return Boolean true if the command sequence complete sucessfully\r
+ * \return Boolean true if the command sequence complete successfully\r
*/\r
-bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)\r
+bool NVMTarget_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
PDITarget_SendByte(EraseCommand);\r
\r
- /* Chip erase is handled seperately, since it's procedure is different to other erase types */\r
+ /* Chip erase is handled separately, since it's procedure is different to other erase types */\r
if (EraseCommand == NVM_CMD_CHIPERASE)\r
{\r
/* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
projects / pub / USBasp.git / blobdiff