firmware/tpi_defs.h

   1 /**
   2  * \brief Internal defs for tpi
   3  * \file tpi_defs.h
   4  * \author S³awomir Fra\9c
   5  */
   6 #ifndef __TPI_DEFS_H__
   7 #define __TPI_DEFS_H__
   8
   9 /* TPI instructions */
  10 #define TPI_OP_SLD      0x20
  11 #define TPI_OP_SLD_INC  0x24
  12 #define TPI_OP_SST      0x60
  13 #define TPI_OP_SST_INC  0x64
  14 #define TPI_OP_SSTPR(a) (0x68 | (a))
  15 #define TPI_OP_SIN(a)   (0x10 | (((a)<<1)&0x60) | ((a)&0x0F) )
  16 #define TPI_OP_SOUT(a)  (0x90 | (((a)<<1)&0x60) | ((a)&0x0F) )
  17 #define TPI_OP_SLDCS(a) (0x80 | ((a)&0x0F) )
  18 #define TPI_OP_SSTCS(a) (0xC0 | ((a)&0x0F) )
  19 #define TPI_OP_SKEY     0xE0
  20
  21 /* TPI control/status registers */
  22 #define TPIIR  0xF
  23 #define TPIPCR 0x2
  24 #define TPISR  0x0
  25
  26 // TPIPCR bits
  27 #define TPIPCR_GT_2    0x04
  28 #define TPIPCR_GT_1    0x02
  29 #define TPIPCR_GT_0    0x01
  30 #define TPIPCR_GT_128b 0x00
  31 #define TPIPCR_GT_64b  0x01
  32 #define TPIPCR_GT_32b  0x02
  33 #define TPIPCR_GT_16b  0x03
  34 #define TPIPCR_GT_8b   0x04
  35 #define TPIPCR_GT_4b   0x05
  36 #define TPIPCR_GT_2b   0x06
  37 #define TPIPCR_GT_0b   0x07
  38
  39 // TPISR bits
  40 #define TPISR_NVMEN    0x02
  41
  42 /* NVM registers */
  43 #define NVMCSR         0x32
  44 #define NVMCMD         0x33
  45
  46 // NVMCSR bits
  47 #define NVMCSR_BSY     0x80
  48
  49 // NVMCMD values
  50 #define NVMCMD_NOP           0x00
  51 #define NVMCMD_CHIP_ERASE    0x10
  52 #define NVMCMD_SECTION_ERASE 0x14
  53 #define NVMCMD_WORD_WRITE    0x1D
  54
  55
  56
  57
  58
  59 #endif /*__TPI_DEFS_H__*/