Projects/XPLAINBridge/Lib/SoftUART.c

   1 /*
   2                          LUFA Library
   3          Copyright (C) Dean Camera, 2010.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6           www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2010  David Prentice (david.prentice [at] farming [dot] uk)
  11   Copyright 2010  Peter Danneger
  12   Copyright 2010  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  13
  14   Permission to use, copy, modify, distribute, and sell this
  15   software and its documentation for any purpose is hereby granted
  16   without fee, provided that the above copyright notice appear in
  17   all copies and that both that the copyright notice and this
  18   permission notice and warranty disclaimer appear in supporting
  19   documentation, and that the name of the author not be used in
  20   advertising or publicity pertaining to distribution of the
  21   software without specific, written prior permission.
  22
  23   The author disclaim all warranties with regard to this
  24   software, including all implied warranties of merchantability
  25   and fitness.  In no event shall the author be liable for any
  26   special, indirect or consequential damages or any damages
  27   whatsoever resulting from loss of use, data or profits, whether
  28   in an action of contract, negligence or other tortious action,
  29   arising out of or in connection with the use or performance of
  30   this software.
  31 */
  32
  33 #include "SoftUART.h"
  34
  35 volatile uint8_t srx_done, stx_count;
  36 volatile uint8_t srx_data, srx_mask, srx_tmp, stx_data;
  37
  38 uint8_t SoftUART_IsReady(void)
  39 {
  40         return !(stx_count);
  41 }
  42
  43 uint8_t SoftUART_TxByte(uint8_t Byte)
  44 {
  45         while (stx_count);
  46
  47         stx_data  = ~Byte;
  48         stx_count = 10;
  49
  50         return Byte;
  51 }
  52
  53 uint8_t SoftUART_IsReceived(void)
  54 {
  55         return srx_done;
  56 }
  57
  58 uint8_t SoftUART_RxByte(void)
  59 {
  60         while (!(srx_done));
  61
  62         srx_done = 0;
  63
  64         return srx_data;
  65 }
  66
  67 void SoftUART_Init(void)
  68 {
  69         OCR2B  = TCNT2 + 1;                                             // force first compare
  70         TCCR2A = (1 << COM2B1) | (1 << COM2B0); // T1 mode 0
  71         TCCR2B = (1 << FOC2B)  | (1 << CS21);   // CLK/8, T1 mode 0
  72         TIMSK2 = (1 << OCIE2B);                                 // enable tx and wait for start
  73         EICRA  = (1 << ISC01);                                  // -ve edge
  74         EIMSK  = (1 << INT0);                                   // enable INT0 interrupt
  75
  76         stx_count = 0;                                                  // nothing to send
  77         srx_done = 0;                                                   // nothing received
  78         STXPORT |= 1 << STX;                                    // TX output
  79         STXDDR  |= 1 << STX;                                    // TX output
  80         SRXPORT |= (1 << SRX);                                  // pullup on INT0
  81 }
  82
  83 /* ISR to detect the start of a bit being sent from the transmitter. */
  84 ISR(INT0_vect)
  85 {
  86         OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start
  87
  88         srx_tmp = 0;                                                    // clear bit storage
  89         srx_mask = 1;                                                   // bit mask
  90
  91         TIFR2 = (1 << OCF2A);                                   // clear pending interrupt
  92
  93         if (!(SRXPIN & (1 << SRX)))                             // still low
  94         {
  95                 TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
  96                 EIMSK &= ~(1 << INT0);
  97         }
  98 }
  99
 100 /* ISR to manage the reception of bits to the transmitter. */
 101 ISR(TIMER2_COMPA_vect)
 102 {
 103         if (srx_mask)
 104         {
 105                 if (SRXPIN & (1 << SRX))
 106                   srx_tmp |= srx_mask;
 107
 108                 srx_mask <<= 1;
 109
 110                 OCR2A += BIT_TIME / 8;                          // next bit slice
 111         }
 112         else
 113         {
 114                 srx_done  = 1;                                          // mark rx data valid
 115                 srx_data  = srx_tmp;                            // store rx data
 116                 TIMSK2    = (1 << OCIE2B);                      // enable tx and wait for start
 117                 EIMSK    |= (1 << INT0);                        // enable START irq
 118                 EIFR      = (1 << INTF0);                       // clear any pending
 119         }
 120 }
 121
 122 /* ISR to manage the transmission of bits to the receiver. */
 123 ISR(TIMER2_COMPB_vect)
 124 {
 125         OCR2B += BIT_TIME / 8;                                  // next bit slice
 126
 127         if (stx_count)
 128         {
 129                 if (--stx_count != 9)                           // no start bit
 130                 {
 131                         if (!(stx_data & 1))                    // test inverted data
 132                           TCCR2A = (1 << COM2B1) | (1 << COM2B0);
 133                         else
 134                           TCCR2A = (1 << COM2B1);
 135
 136                         stx_data >>= 1;                                 // shift zero in from left
 137                 }
 138                 else
 139                 {
 140                         TCCR2A = (1 << COM2B1);                 // START bit
 141                 }
 142         }
 143 }