Slightly speed up software USART in the AVRISP project - faster parity computation...
[pub/USBasp.git] / Projects / AVRISP / Lib / PDITarget.c
1 /*
2 LUFA Library
3 Copyright (C) Dean Camera, 2009.
4
5 dean [at] fourwalledcubicle [dot] com
6 www.fourwalledcubicle.com
7 */
8
9 /*
10 Copyright 2009 Dean Camera (dean [at] fourwalledcubicle [dot] com)
11
12 Permission to use, copy, modify, and distribute this software
13 and its documentation for any purpose and without fee is hereby
14 granted, provided that the above copyright notice appear in all
15 copies and that both that the copyright notice and this
16 permission notice and warranty disclaimer appear in supporting
17 documentation, and that the name of the author not be used in
18 advertising or publicity pertaining to distribution of the
19 software without specific, written prior permission.
20
21 The author disclaim all warranties with regard to this
22 software, including all implied warranties of merchantability
23 and fitness. In no event shall the author be liable for any
24 special, indirect or consequential damages or any damages
25 whatsoever resulting from loss of use, data or profits, whether
26 in an action of contract, negligence or other tortious action,
27 arising out of or in connection with the use or performance of
28 this software.
29 */
30
31 /** \file
32 *
33 * Target-related functions for the PDI Protocol decoder.
34 */
35
36 #define INCLUDE_FROM_PDITARGET_C
37 #include "PDITarget.h"
38
39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
40
41 /** Flag to indicate if the USART is currently in Tx or Rx mode. */
42 volatile bool IsSending;
43
44 #if !defined(PDI_VIA_HARDWARE_USART)
45 /** Software USART raw frame bits for transmission/reception. */
46 volatile uint16_t SoftUSART_Data;
47
48 /** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */
49 #define SoftUSART_BitCount GPIOR2
50
51
52 /** ISR to manage the software USART when bit-banged USART mode is selected. */
53 ISR(TIMER1_COMPA_vect, ISR_BLOCK)
54 {
55 /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
56 BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;
57
58 /* If not sending or receiving, just exit */
59 if (!(SoftUSART_BitCount))
60 return;
61
62 /* Check to see if we are at a rising or falling edge of the clock */
63 if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)
64 {
65 /* If at rising clock edge and we are in send mode, abort */
66 if (IsSending)
67 return;
68
69 /* Wait for the start bit when receiving */
70 if ((SoftUSART_BitCount == BITS_IN_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
71 return;
72
73 /* Shift in the bit one less than the frame size in position, so that the start bit will eventually
74 * be discarded leaving the data to be byte-aligned for quick access */
75 if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
76 SoftUSART_Data |= (1 << (BITS_IN_FRAME - 1));
77
78 SoftUSART_Data >>= 1;
79 SoftUSART_BitCount--;
80 }
81 else
82 {
83 /* If at falling clock edge and we are in receive mode, abort */
84 if (!IsSending)
85 return;
86
87 /* Set the data line to the next bit value */
88 if (SoftUSART_Data & 0x01)
89 BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
90 else
91 BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
92
93 SoftUSART_Data >>= 1;
94 SoftUSART_BitCount--;
95 }
96 }
97 #endif
98
99 /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
100 void PDITarget_EnableTargetPDI(void)
101 {
102 #if defined(PDI_VIA_HARDWARE_USART)
103 /* Set Tx and XCK as outputs, Rx as input */
104 DDRD |= (1 << 5) | (1 << 3);
105 DDRD &= ~(1 << 2);
106
107 /* Set DATA line high for at least 90ns to disable /RESET functionality */
108 PORTD |= (1 << 3);
109 asm volatile ("NOP"::);
110 asm volatile ("NOP"::);
111
112 /* Set up the synchronous USART for XMEGA communications -
113 8 data bits, even parity, 2 stop bits */
114 UBRR1 = (F_CPU / 1000000UL);
115 UCSR1B = (1 << TXEN1);
116 UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
117
118 /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
119 PDITarget_SendBreak();
120 PDITarget_SendBreak();
121 #else
122 /* Set DATA and CLOCK lines to outputs */
123 BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
124 BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
125
126 /* Set DATA line high for at least 90ns to disable /RESET functionality */
127 BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
128 asm volatile ("NOP"::);
129 asm volatile ("NOP"::);
130
131 /* Fire timer compare ISR every 100 cycles to manage the software USART */
132 OCR1A = 80;
133 TCCR1B = (1 << WGM12) | (1 << CS10);
134 TIMSK1 = (1 << OCIE1A);
135
136 PDITarget_SendBreak();
137 PDITarget_SendBreak();
138 #endif
139 }
140
141 /** Disables the target's PDI interface, exits programming mode and starts the target's application. */
142 void PDITarget_DisableTargetPDI(void)
143 {
144 #if defined(PDI_VIA_HARDWARE_USART)
145 /* Turn off receiver and transmitter of the USART, clear settings */
146 UCSR1A |= (1 << TXC1) | (1 << RXC1);
147 UCSR1B = 0;
148 UCSR1C = 0;
149
150 /* Set all USART lines as input, tristate */
151 DDRD &= ~((1 << 5) | (1 << 3));
152 PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
153 #else
154 /* Set DATA and CLOCK lines to inputs */
155 BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
156 BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
157
158 /* Tristate DATA and CLOCK lines */
159 BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
160 BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
161
162 TCCR0B = 0;
163 #endif
164 }
165
166 /** Sends a byte via the USART.
167 *
168 * \param[in] Byte Byte to send through the USART
169 */
170 void PDITarget_SendByte(uint8_t Byte)
171 {
172 #if defined(PDI_VIA_HARDWARE_USART)
173 /* Switch to Tx mode if currently in Rx mode */
174 if (!(IsSending))
175 {
176 PORTD |= (1 << 3);
177 DDRD |= (1 << 3);
178
179 UCSR1B |= (1 << TXEN1);
180 UCSR1B &= ~(1 << RXEN1);
181
182 IsSending = true;
183 }
184
185 /* Wait until there is space in the hardware Tx buffer before writing */
186 while (!(UCSR1A & (1 << UDRE1)));
187 UCSR1A |= (1 << TXC1);
188 UDR1 = Byte;
189 #else
190 /* Switch to Tx mode if currently in Rx mode */
191 if (!(IsSending))
192 {
193 BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
194 BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
195
196 IsSending = true;
197 }
198
199 bool EvenParityBit = false;
200 uint8_t ParityData = Byte;
201
202 /* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */
203 while (ParityData)
204 {
205 EvenParityBit ^= true;
206 ParityData &= (ParityData - 1);
207 }
208
209 /* Calculate the new USART frame data here while while we wait for a previous byte (if any) to finish sending */
210 uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | ((uint16_t)EvenParityBit << 9) | ((uint16_t)Byte << 1) | (0 << 0));
211
212 while (SoftUSART_BitCount);
213
214 /* Data shifted out LSB first, START DATA PARITY STOP STOP */
215 SoftUSART_Data = NewUSARTData;
216 SoftUSART_BitCount = BITS_IN_FRAME;
217 #endif
218 }
219
220 /** Receives a byte via the software USART, blocking until data is received.
221 *
222 * \return Received byte from the USART
223 */
224 uint8_t PDITarget_ReceiveByte(void)
225 {
226 #if defined(PDI_VIA_HARDWARE_USART)
227 /* Switch to Rx mode if currently in Tx mode */
228 if (IsSending)
229 {
230 while (!(UCSR1A & (1 << TXC1)));
231 UCSR1A |= (1 << TXC1);
232
233 UCSR1B &= ~(1 << TXEN1);
234 UCSR1B |= (1 << RXEN1);
235
236 DDRD &= ~(1 << 3);
237 PORTD &= ~(1 << 3);
238
239 IsSending = false;
240 }
241
242 /* Wait until a byte has been received before reading */
243 while (!(UCSR1A & (1 << RXC1)));
244 return UDR1;
245 #else
246 /* Switch to Rx mode if currently in Tx mode */
247 if (IsSending)
248 {
249 while (SoftUSART_BitCount);
250
251 BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
252 BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
253
254 IsSending = false;
255 }
256
257 /* Wait until a byte has been received before reading */
258 SoftUSART_BitCount = BITS_IN_FRAME;
259 while (SoftUSART_BitCount);
260
261 /* Throw away the start, parity and stop bits to leave only the data */
262 return (uint8_t)SoftUSART_Data;
263 #endif
264 }
265
266 /** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
267 void PDITarget_SendBreak(void)
268 {
269 #if defined(PDI_VIA_HARDWARE_USART)
270 /* Switch to Tx mode if currently in Rx mode */
271 if (!(IsSending))
272 {
273 PORTD |= (1 << 3);
274 DDRD |= (1 << 3);
275
276 UCSR1B &= ~(1 << RXEN1);
277 UCSR1B |= (1 << TXEN1);
278
279 IsSending = true;
280 }
281
282 /* Need to do nothing for a full frame to send a BREAK */
283 for (uint8_t i = 0; i <= BITS_IN_FRAME; i++)
284 {
285 /* Wait for a full cycle of the clock */
286 while (PIND & (1 << 5));
287 while (!(PIND & (1 << 5)));
288 }
289 #else
290 /* Switch to Tx mode if currently in Rx mode */
291 if (!(IsSending))
292 {
293 BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
294 BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
295
296 IsSending = true;
297 }
298
299 while (SoftUSART_BitCount);
300
301 /* Need to do nothing for a full frame to send a BREAK */
302 SoftUSART_Data = 0x0FFF;
303 SoftUSART_BitCount = BITS_IN_FRAME;
304 #endif
305 }
306
307 /** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC
308 * calculation.
309 *
310 * \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
311 */
312 bool PDITarget_WaitWhileNVMBusBusy(void)
313 {
314 TCNT0 = 0;
315
316 /* Poll the STATUS register to check to see if NVM access has been enabled */
317 while (TCNT0 < PDI_NVM_TIMEOUT_MS)
318 {
319 /* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
320 PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
321 if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
322 return true;
323 }
324
325 return false;
326 }
327
328 #endif