Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Sends the given NVM register address to the target.
  42  *
  43  *  \param[in] Register  NVM register whose absolute address is to be sent
  44  */
  45 void NVMTarget_SendNVMRegAddress(const uint8_t Register)
  46 {
  47         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  48         uint32_t Address = XPROG_Param_NVMBase | Register;
  49
  50         /* Send the calculated 32-bit address to the target, LSB first */
  51         NVMTarget_SendAddress(Address);
  52 }
  53
  54 /** Sends the given 32-bit absolute address to the target.
  55  *
  56  *  \param[in] AbsoluteAddress  Absolute address to send to the target
  57  */
  58 void NVMTarget_SendAddress(const uint32_t AbsoluteAddress)
  59 {
  60         /* Send the given 32-bit address to the target, LSB first */
  61         PDITarget_SendByte(AbsoluteAddress &  0xFF);
  62         PDITarget_SendByte(AbsoluteAddress >> 8);
  63         PDITarget_SendByte(AbsoluteAddress >> 16);
  64         PDITarget_SendByte(AbsoluteAddress >> 24);
  65 }
  66
  67 /** Waits while the target's NVM controller is busy performing an operation, exiting if the
  68  *  timeout period expires.
  69  *
  70  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
  71  */
  72 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  73 {
  74         TCNT0 = 0;
  75         TIFR0 = (1 << OCF1A);
  76
  77         uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS;
  78
  79         /* Poll the NVM STATUS register while the NVM controller is busy */
  80         while (TimeoutMS)
  81         {
  82                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  83                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  84                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  85
  86                 /* Check to see if the BUSY flag is still set */
  87                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  88                   return true;
  89
  90                 if (TIFR0 & (1 << OCF1A))
  91                 {
  92                         TIFR0 = (1 << OCF1A);
  93                         TimeoutMS--;
  94                 }
  95         }
  96
  97         return false;
  98 }
  99
 100 /** Retrieves the CRC value of the given memory space.
 101  *
 102  *  \param[in]  CRCCommand  NVM CRC command to issue to the target
 103  *  \param[out] CRCDest     CRC Destination when read from the target
 104  *
 105  *  \return Boolean true if the command sequence complete successfully
 106  */
 107 bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)
 108 {
 109         /* Wait until the NVM controller is no longer busy */
 110         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 111           return false;
 112
 113         /* Set the NVM command to the correct CRC read command */
 114         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 115         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 116         PDITarget_SendByte(CRCCommand);
 117
 118         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
 119         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 120         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 121         PDITarget_SendByte(1 << 0);
 122
 123         /* Wait until the NVM bus is ready again */
 124         if (!(PDITarget_WaitWhileNVMBusBusy()))
 125           return false;
 126
 127         /* Wait until the NVM controller is no longer busy */
 128         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 129           return false;
 130
 131         *CRCDest = 0;
 132
 133         /* Read the first generated CRC byte value */
 134         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 135         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 136         *CRCDest  = PDITarget_ReceiveByte();
 137
 138         /* Read the second generated CRC byte value */
 139         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 140         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 141         *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 142
 143         /* Read the third generated CRC byte value */
 144         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 145         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 146         *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 147
 148         return true;
 149 }
 150
 151 /** Reads memory from the target's memory spaces.
 152  *
 153  *  \param[in]  ReadAddress  Start address to read from within the target's address space
 154  *  \param[out] ReadBuffer   Buffer to store read data into
 155  *  \param[in]  ReadSize     Number of bytes to read
 156  *
 157  *  \return Boolean true if the command sequence complete successfully
 158  */
 159 bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)
 160 {
 161         /* Wait until the NVM controller is no longer busy */
 162         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 163           return false;
 164
 165         /* Send the READNVM command to the NVM controller for reading of an arbitrary location */
 166         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 167         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 168         PDITarget_SendByte(NVM_CMD_READNVM);
 169
 170         /* Load the PDI pointer register with the start address we want to read from */
 171         PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 172         NVMTarget_SendAddress(ReadAddress);
 173
 174         /* Send the REPEAT command with the specified number of bytes to read */
 175         PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 176         PDITarget_SendByte(ReadSize - 1);
 177
 178         /* Send a LD command with indirect access and postincrement to read out the bytes */
 179         PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 180         for (uint16_t i = 0; i < ReadSize; i++)
 181           *(ReadBuffer++) = PDITarget_ReceiveByte();
 182
 183         return true;
 184 }
 185
 186 /** Writes byte addressed memory to the target's memory spaces.
 187  *
 188  *  \param[in]  WriteCommand  Command to send to the device to write each memory byte
 189  *  \param[in]  WriteAddress  Start address to write to within the target's address space
 190  *  \param[in]  WriteBuffer   Buffer to source data from
 191  *
 192  *  \return Boolean true if the command sequence complete successfully
 193  */
 194 bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)
 195 {
 196         /* Wait until the NVM controller is no longer busy */
 197         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 198           return false;
 199
 200         /* Send the memory write command to the target */
 201         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 202         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 203         PDITarget_SendByte(WriteCommand);
 204
 205         /* Send new memory byte to the memory to the target */
 206         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 207         NVMTarget_SendAddress(WriteAddress);
 208         PDITarget_SendByte(*(WriteBuffer++));
 209
 210         return true;
 211 }
 212
 213 /** Writes page addressed memory to the target's memory spaces.
 214  *
 215  *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer
 216  *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer
 217  *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory
 218  *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page
 219  *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space
 220  *  \param[in]  WriteBuffer       Buffer to source data from
 221  *  \param[in]  WriteSize         Number of bytes to write
 222  *
 223  *  \return Boolean true if the command sequence complete successfully
 224  */
 225 bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand,
 226                                const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,
 227                                const uint8_t* WriteBuffer, const uint16_t WriteSize)
 228 {
 229         if (PageMode & XPRG_PAGEMODE_ERASE)
 230         {
 231                 /* Wait until the NVM controller is no longer busy */
 232                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 233                   return false;
 234
 235                 /* Send the memory buffer erase command to the target */
 236                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 237                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 238                 PDITarget_SendByte(EraseBuffCommand);
 239
 240                 /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
 241                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 242                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 243                 PDITarget_SendByte(1 << 0);
 244         }
 245
 246         if (WriteSize)
 247         {
 248                 /* Wait until the NVM controller is no longer busy */
 249                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 250                   return false;
 251
 252                 /* Send the memory buffer write command to the target */
 253                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 254                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 255                 PDITarget_SendByte(WriteBuffCommand);
 256
 257                 /* Load the PDI pointer register with the start address we want to write to */
 258                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 259                 NVMTarget_SendAddress(WriteAddress);
 260
 261                 /* Send the REPEAT command with the specified number of bytes to write */
 262                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 263                 PDITarget_SendByte(WriteSize - 1);
 264
 265                 /* Send a ST command with indirect access and postincrement to write the bytes */
 266                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 267                 for (uint16_t i = 0; i < WriteSize; i++)
 268                   PDITarget_SendByte(*(WriteBuffer++));
 269         }
 270
 271         if (PageMode & XPRG_PAGEMODE_WRITE)
 272         {
 273                 /* Wait until the NVM controller is no longer busy */
 274                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 275                   return false;
 276
 277                 /* Send the memory write command to the target */
 278                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 279                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 280                 PDITarget_SendByte(WritePageCommand);
 281
 282                 /* Send the address of the first page location to write the memory page */
 283                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 284                 NVMTarget_SendAddress(WriteAddress);
 285                 PDITarget_SendByte(0x00);
 286         }
 287
 288         return true;
 289 }
 290
 291 /** Erases a specific memory space of the target.
 292  *
 293  *  \param[in] EraseCommand  NVM erase command to send to the device
 294  *  \param[in] Address  Address inside the memory space to erase
 295  *
 296  *  \return Boolean true if the command sequence complete successfully
 297  */
 298 bool NVMTarget_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)
 299 {
 300         /* Wait until the NVM controller is no longer busy */
 301         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 302           return false;
 303
 304         /* Send the memory erase command to the target */
 305         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 306         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 307         PDITarget_SendByte(EraseCommand);
 308
 309         /* Chip erase is handled separately, since it's procedure is different to other erase types */
 310         if (EraseCommand == NVM_CMD_CHIPERASE)
 311         {
 312                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 313                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 314                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 315                 PDITarget_SendByte(1 << 0);
 316         }
 317         else
 318         {
 319                 /* Other erase modes just need us to address a byte within the target memory space */
 320                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 321                 NVMTarget_SendAddress(Address);
 322                 PDITarget_SendByte(0x00);
 323         }
 324
 325         /* Wait until the NVM bus is ready again */
 326         if (!(PDITarget_WaitWhileNVMBusBusy()))
 327           return false;
 328
 329         return true;
 330 }
 331
 332 #endif