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Add new Bulk Vendor device demo application.
[pub/USBasp.git] / LUFA / Platform / XMEGA / ClockManagement.h
1 /*
2 LUFA Library
3 Copyright (C) Dean Camera, 2013.
4
5 dean [at] fourwalledcubicle [dot] com
6 www.lufa-lib.org
7 */
8
9 /*
10 Copyright 2013 Dean Camera (dean [at] fourwalledcubicle [dot] com)
11
12 Permission to use, copy, modify, distribute, and sell this
13 software and its documentation for any purpose is hereby granted
14 without fee, provided that the above copyright notice appear in
15 all copies and that both that the copyright notice and this
16 permission notice and warranty disclaimer appear in supporting
17 documentation, and that the name of the author not be used in
18 advertising or publicity pertaining to distribution of the
19 software without specific, written prior permission.
20
21 The author disclaims all warranties with regard to this
22 software, including all implied warranties of merchantability
23 and fitness. In no event shall the author be liable for any
24 special, indirect or consequential damages or any damages
25 whatsoever resulting from loss of use, data or profits, whether
26 in an action of contract, negligence or other tortious action,
27 arising out of or in connection with the use or performance of
28 this software.
29 */
30
31 /** \file
32 * \brief Module Clock Driver for the AVR USB XMEGA microcontrollers.
33 *
34 * Clock management driver for the AVR USB XMEGA microcontrollers. This driver allows for the configuration
35 * of the various clocks within the device to clock the various peripherals.
36 */
37
38 /** \ingroup Group_PlatformDrivers_XMEGA
39 * \defgroup Group_PlatformDrivers_XMEGAClocks Clock Management Driver - LUFA/Platform/XMEGA/ClockManagement.h
40 * \brief Module Clock Driver for the AVR USB XMEGA microcontrollers.
41 *
42 * \section Sec_PlatformDrivers_XMEGAClocks_Dependencies Module Source Dependencies
43 * The following files must be built with any user project that uses this module:
44 * - None
45 *
46 * \section Sec_PlatformDrivers_XMEGAClocks_ModDescription Module Description
47 * Clock management driver for the AVR USB XMEGA microcontrollers. This driver allows for the configuration
48 * of the various clocks within the device to clock the various peripherals.
49 *
50 * Usage Example:
51 * \code
52 * #include <LUFA/Platform/XMEGA/ClockManagement.h>
53 *
54 * void main(void)
55 * {
56 * // Start the PLL to multiply the 2MHz RC oscillator to F_CPU and switch the CPU core to run from it
57 * XMEGACLK_StartPLL(CLOCK_SRC_INT_RC2MHZ, 2000000, F_CPU);
58 * XMEGACLK_SetCPUClockSource(CLOCK_SRC_PLL);
59 *
60 * // Start the 32MHz internal RC oscillator and start the DFLL to increase it to F_USB using the USB SOF as a reference
61 * XMEGACLK_StartInternalOscillator(CLOCK_SRC_INT_RC32MHZ);
62 * XMEGACLK_StartDFLL(CLOCK_SRC_INT_RC32MHZ, DFLL_REF_INT_USBSOF, F_USB);
63 * }
64 * \endcode
65 *
66 * @{
67 */
68
69 #ifndef _XMEGA_CLOCK_MANAGEMENT_H_
70 #define _XMEGA_CLOCK_MANAGEMENT_H_
71
72 /* Includes: */
73 #include "../../Common/Common.h"
74
75 /* Enable C linkage for C++ Compilers: */
76 #if defined(__cplusplus)
77 extern "C" {
78 #endif
79
80 /* Public Interface - May be used in end-application: */
81 /* Macros: */
82 /** Enum for the possible external oscillator frequency ranges. */
83 enum XMEGA_Extern_OSC_ClockFrequency_t
84 {
85 EXOSC_FREQ_2MHZ_MAX = OSC_FRQRANGE_04TO2_gc, /**< External crystal oscillator equal to or slower than 2MHz. */
86 EXOSC_FREQ_9MHZ_MAX = OSC_FRQRANGE_2TO9_gc, /**< External crystal oscillator equal to or slower than 9MHz. */
87 EXOSC_FREQ_12MHZ_MAX = OSC_FRQRANGE_9TO12_gc, /**< External crystal oscillator equal to or slower than 12MHz. */
88 EXOSC_FREQ_16MHZ_MAX = OSC_FRQRANGE_12TO16_gc, /**< External crystal oscillator equal to or slower than 16MHz. */
89 };
90
91 /** Enum for the possible external oscillator startup times. */
92 enum XMEGA_Extern_OSC_ClockStartup_t
93 {
94 EXOSC_START_6CLK = OSC_XOSCSEL_EXTCLK_gc, /**< Wait 6 clock cycles before startup (external clock). */
95 EXOSC_START_32KCLK = OSC_XOSCSEL_32KHz_gc, /**< Wait 32K clock cycles before startup (32.768KHz crystal). */
96 EXOSC_START_256CLK = OSC_XOSCSEL_XTAL_256CLK_gc, /**< Wait 256 clock cycles before startup. */
97 EXOSC_START_1KCLK = OSC_XOSCSEL_XTAL_1KCLK_gc, /**< Wait 1K clock cycles before startup. */
98 EXOSC_START_16KCLK = OSC_XOSCSEL_XTAL_16KCLK_gc, /**< Wait 16K clock cycles before startup. */
99 };
100
101 /** Enum for the possible module clock sources. */
102 enum XMEGA_System_ClockSource_t
103 {
104 CLOCK_SRC_INT_RC2MHZ = 0, /**< Clock sourced from the Internal 2MHz RC Oscillator clock. */
105 CLOCK_SRC_INT_RC32MHZ = 1, /**< Clock sourced from the Internal 32MHz RC Oscillator clock. */
106 CLOCK_SRC_INT_RC32KHZ = 2, /**< Clock sourced from the Internal 32KHz RC Oscillator clock. */
107 CLOCK_SRC_XOSC = 3, /**< Clock sourced from the External Oscillator clock. */
108 CLOCK_SRC_PLL = 4, /**< Clock sourced from the Internal PLL clock. */
109 };
110
111 /** Enum for the possible DFLL clock reference sources. */
112 enum XMEGA_System_DFLLReference_t
113 {
114 DFLL_REF_INT_RC32KHZ = 0, /**< Reference clock sourced from the Internal 32KHz RC Oscillator clock. */
115 DFLL_REF_EXT_RC32KHZ = 1, /**< Reference clock sourced from the External 32KHz RC Oscillator clock connected to TOSC pins. */
116 DFLL_REF_INT_USBSOF = 2, /**< Reference clock sourced from the USB Start Of Frame packets. */
117 };
118
119 /* Inline Functions: */
120 /** Write a value to a location protected by the XMEGA CCP protection mechanism. This function uses inline assembly to ensure that
121 * the protected address is written to within four clock cycles of the CCP key being written.
122 *
123 * \param[in] Address Address to write to, a memory address protected by the CCP mechanism
124 * \param[in] Value Value to write to the protected location
125 */
126 static inline void XMEGACLK_CCP_Write(volatile void* Address, const uint8_t Value) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;
127 static inline void XMEGACLK_CCP_Write(volatile void* Address, const uint8_t Value)
128 {
129 __asm__ __volatile__ (
130 "out %0, __zero_reg__" "\n\t" /* Zero RAMPZ using fixed zero value register */
131 "movw r30, %1" "\n\t" /* Copy address to Z register pair */
132 "out %2, %3" "\n\t" /* Write key to CCP register */
133 "st Z, %4" "\n\t" /* Indirectly write value to address */
134 : /* No output operands */
135 : /* Input operands: */ "m" (RAMPZ), "e" (Address), "m" (CCP), "r" (CCP_IOREG_gc), "r" (Value)
136 : /* Clobbered registers: */ "r30", "r31"
137 );
138 }
139
140 /** Starts the external oscillator of the XMEGA microcontroller, with the given options. This routine blocks until
141 * the oscillator is ready for use.
142 *
143 * \param[in] FreqRange Frequency range of the external oscillator, a value from \ref XMEGA_Extern_OSC_ClockFrequency_t.
144 * \param[in] Startup Startup time of the external oscillator, a value from \ref XMEGA_Extern_OSC_ClockStartup_t.
145 *
146 * \return Boolean \c true if the external oscillator was successfully started, \c false if invalid parameters specified.
147 */
148 static inline bool XMEGACLK_StartExternalOscillator(const uint8_t FreqRange,
149 const uint8_t Startup) ATTR_ALWAYS_INLINE;
150 static inline bool XMEGACLK_StartExternalOscillator(const uint8_t FreqRange,
151 const uint8_t Startup)
152 {
153 OSC.XOSCCTRL = (FreqRange | ((Startup == EXOSC_START_32KCLK) ? OSC_X32KLPM_bm : 0) | Startup);
154 OSC.CTRL |= OSC_XOSCEN_bm;
155
156 while (!(OSC.STATUS & OSC_XOSCRDY_bm));
157 return true;
158 }
159
160 /** Stops the external oscillator of the XMEGA microcontroller. */
161 static inline void XMEGACLK_StopExternalOscillator(void) ATTR_ALWAYS_INLINE;
162 static inline void XMEGACLK_StopExternalOscillator(void)
163 {
164 OSC.CTRL &= ~OSC_XOSCEN_bm;
165 }
166
167 /** Starts the given internal oscillator of the XMEGA microcontroller, with the given options. This routine blocks until
168 * the oscillator is ready for use.
169 *
170 * \param[in] Source Internal oscillator to start, a value from \ref XMEGA_System_ClockSource_t.
171 *
172 * \return Boolean \c true if the internal oscillator was successfully started, \c false if invalid parameters specified.
173 */
174 static inline uint8_t XMEGACLK_StartInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE;
175 static inline uint8_t XMEGACLK_StartInternalOscillator(const uint8_t Source)
176 {
177 switch (Source)
178 {
179 case CLOCK_SRC_INT_RC2MHZ:
180 OSC.CTRL |= OSC_RC2MEN_bm;
181 while (!(OSC.STATUS & OSC_RC2MRDY_bm));
182 return true;
183 case CLOCK_SRC_INT_RC32MHZ:
184 OSC.CTRL |= OSC_RC32MEN_bm;
185 while (!(OSC.STATUS & OSC_RC32MRDY_bm));
186 return true;
187 case CLOCK_SRC_INT_RC32KHZ:
188 OSC.CTRL |= OSC_RC32KEN_bm;
189 while (!(OSC.STATUS & OSC_RC32KRDY_bm));
190 return true;
191 default:
192 return false;
193 }
194 }
195
196 /** Stops the given internal oscillator of the XMEGA microcontroller.
197 *
198 * \param[in] Source Internal oscillator to stop, a value from \ref XMEGA_System_ClockSource_t.
199 *
200 * \return Boolean \c true if the internal oscillator was successfully stopped, \c false if invalid parameters specified.
201 */
202 static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE;
203 static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source)
204 {
205 switch (Source)
206 {
207 case CLOCK_SRC_INT_RC2MHZ:
208 OSC.CTRL &= ~OSC_RC2MEN_bm;
209 return true;
210 case CLOCK_SRC_INT_RC32MHZ:
211 OSC.CTRL &= ~OSC_RC32MEN_bm;
212 return true;
213 case CLOCK_SRC_INT_RC32KHZ:
214 OSC.CTRL &= ~OSC_RC32KEN_bm;
215 return true;
216 default:
217 return false;
218 }
219 }
220
221 /** Starts the PLL of the XMEGA microcontroller, with the given options. This routine blocks until the PLL is ready for use.
222 *
223 * \attention The output frequency must be equal to or greater than the source frequency.
224 *
225 * \param[in] Source Clock source for the PLL, a value from \ref XMEGA_System_ClockSource_t.
226 * \param[in] SourceFreq Frequency of the PLL's clock source, in Hz.
227 * \param[in] Frequency Target frequency of the PLL's output.
228 *
229 * \return Boolean \c true if the PLL was successfully started, \c false if invalid parameters specified.
230 */
231 static inline bool XMEGACLK_StartPLL(const uint8_t Source,
232 const uint32_t SourceFreq,
233 const uint32_t Frequency) ATTR_ALWAYS_INLINE;
234 static inline bool XMEGACLK_StartPLL(const uint8_t Source,
235 const uint32_t SourceFreq,
236 const uint32_t Frequency)
237 {
238 uint8_t MulFactor = (Frequency / SourceFreq);
239
240 if (SourceFreq > Frequency)
241 return false;
242
243 if (MulFactor > 31)
244 return false;
245
246 switch (Source)
247 {
248 case CLOCK_SRC_INT_RC2MHZ:
249 OSC.PLLCTRL = (OSC_PLLSRC_RC2M_gc | MulFactor);
250 break;
251 case CLOCK_SRC_INT_RC32MHZ:
252 OSC.PLLCTRL = (OSC_PLLSRC_RC32M_gc | MulFactor);
253 break;
254 case CLOCK_SRC_XOSC:
255 OSC.PLLCTRL = (OSC_PLLSRC_XOSC_gc | MulFactor);
256 break;
257 default:
258 return false;
259 }
260
261 OSC.CTRL |= OSC_PLLEN_bm;
262
263 while (!(OSC.STATUS & OSC_PLLRDY_bm));
264 return true;
265 }
266
267 /** Stops the PLL of the XMEGA microcontroller. */
268 static inline void XMEGACLK_StopPLL(void) ATTR_ALWAYS_INLINE;
269 static inline void XMEGACLK_StopPLL(void)
270 {
271 OSC.CTRL &= ~OSC_PLLEN_bm;
272 }
273
274 /** Starts the DFLL of the XMEGA microcontroller, with the given options.
275 *
276 * \param[in] Source RC Clock source for the DFLL, a value from \ref XMEGA_System_ClockSource_t.
277 * \param[in] Reference Reference clock source for the DFLL, an value from \ref XMEGA_System_DFLLReference_t.
278 * \param[in] Frequency Target frequency of the DFLL's output.
279 *
280 * \return Boolean \c true if the DFLL was successfully started, \c false if invalid parameters specified.
281 */
282 static inline bool XMEGACLK_StartDFLL(const uint8_t Source,
283 const uint8_t Reference,
284 const uint32_t Frequency) ATTR_ALWAYS_INLINE;
285 static inline bool XMEGACLK_StartDFLL(const uint8_t Source,
286 const uint8_t Reference,
287 const uint32_t Frequency)
288 {
289 uint16_t DFLLCompare = (Frequency / 1000);
290
291 switch (Source)
292 {
293 case CLOCK_SRC_INT_RC2MHZ:
294 OSC.DFLLCTRL |= (Reference << OSC_RC2MCREF_bp);
295 DFLLRC2M.COMP1 = (DFLLCompare & 0xFF);
296 DFLLRC2M.COMP2 = (DFLLCompare >> 8);
297 DFLLRC2M.CTRL = DFLL_ENABLE_bm;
298 break;
299 case CLOCK_SRC_INT_RC32MHZ:
300 OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp);
301 DFLLRC32M.COMP1 = (DFLLCompare & 0xFF);
302 DFLLRC32M.COMP2 = (DFLLCompare >> 8);
303
304 if (Reference == DFLL_REF_INT_USBSOF)
305 {
306 NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc;
307 DFLLRC32M.CALA = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSCA));
308 DFLLRC32M.CALB = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC));
309 NVM.CMD = 0;
310 }
311
312 DFLLRC32M.CTRL = DFLL_ENABLE_bm;
313 break;
314 default:
315 return false;
316 }
317
318 return true;
319 }
320
321 /** Stops the given DFLL of the XMEGA microcontroller.
322 *
323 * \param[in] Source RC Clock source for the DFLL to be stopped, a value from \ref XMEGA_System_ClockSource_t.
324 *
325 * \return Boolean \c true if the DFLL was successfully stopped, \c false if invalid parameters specified.
326 */
327 static inline bool XMEGACLK_StopDFLL(const uint8_t Source) ATTR_ALWAYS_INLINE;
328 static inline bool XMEGACLK_StopDFLL(const uint8_t Source)
329 {
330 switch (Source)
331 {
332 case CLOCK_SRC_INT_RC2MHZ:
333 DFLLRC2M.CTRL = 0;
334 break;
335 case CLOCK_SRC_INT_RC32MHZ:
336 DFLLRC32M.CTRL = 0;
337 break;
338 default:
339 return false;
340 }
341
342 return true;
343 }
344
345 /** Sets the clock source for the main microcontroller core. The given clock source should be configured
346 * and ready for use before this function is called.
347 *
348 * \param[in] Source Clock source for the CPU core, a value from \ref XMEGA_System_ClockSource_t.
349 *
350 * \return Boolean \c true if the CPU core clock was successfully altered, \c false if invalid parameters specified.
351 */
352 static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source) ATTR_ALWAYS_INLINE;
353 static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source)
354 {
355 uint8_t ClockSourceMask = 0;
356
357 switch (Source)
358 {
359 case CLOCK_SRC_INT_RC2MHZ:
360 ClockSourceMask = CLK_SCLKSEL_RC2M_gc;
361 break;
362 case CLOCK_SRC_INT_RC32MHZ:
363 ClockSourceMask = CLK_SCLKSEL_RC32M_gc;
364 break;
365 case CLOCK_SRC_INT_RC32KHZ:
366 ClockSourceMask = CLK_SCLKSEL_RC32K_gc;
367 break;
368 case CLOCK_SRC_XOSC:
369 ClockSourceMask = CLK_SCLKSEL_XOSC_gc;
370 break;
371 case CLOCK_SRC_PLL:
372 ClockSourceMask = CLK_SCLKSEL_PLL_gc;
373 break;
374 default:
375 return false;
376 }
377
378 uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();
379 GlobalInterruptDisable();
380
381 XMEGACLK_CCP_Write(&CLK.CTRL, ClockSourceMask);
382
383 SetGlobalInterruptMask(CurrentGlobalInt);
384
385 Delay_MS(1);
386 return (CLK.CTRL == ClockSourceMask);
387 }
388
389 /* Disable C linkage for C++ Compilers: */
390 #if defined(__cplusplus)
391 }
392 #endif
393
394 #endif
395
396 /** @} */
397
USB isp AVR programmer