Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Sends the given NVM register address to the target.
  42  *
  43  *  \param[in] Register  NVM register whose absolute address is to be sent
  44  */
  45 void NVMTarget_SendNVMRegAddress(const uint8_t Register)
  46 {
  47         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  48         uint32_t Address = XPROG_Param_NVMBase | Register;
  49
  50         /* Send the calculated 32-bit address to the target, LSB first */
  51         NVMTarget_SendAddress(Address);
  52 }
  53
  54 /** Sends the given 32-bit absolute address to the target.
  55  *
  56  *  \param[in] AbsoluteAddress  Absolute address to send to the target
  57  */
  58 void NVMTarget_SendAddress(const uint32_t AbsoluteAddress)
  59 {
  60         /* Send the given 32-bit address to the target, LSB first */
  61         PDITarget_SendByte(AbsoluteAddress &  0xFF);
  62         PDITarget_SendByte(AbsoluteAddress >> 8);
  63         PDITarget_SendByte(AbsoluteAddress >> 16);
  64         PDITarget_SendByte(AbsoluteAddress >> 24);
  65 }
  66
  67 /** Waits while the target's NVM controller is busy performing an operation, exiting if the
  68  *  timeout period expires.
  69  *
  70  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
  71  */
  72 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  73 {
  74         TCNT0 = 0;
  75
  76         /* Poll the NVM STATUS register while the NVM controller is busy */
  77         while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
  78         {
  79                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  80                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  81                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  82
  83                 /* Check to see if the BUSY flag is still set */
  84                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  85                   return true;
  86         }
  87
  88         return false;
  89 }
  90
  91 /** Retrieves the CRC value of the given memory space.
  92  *
  93  *  \param[in]  CRCCommand  NVM CRC command to issue to the target
  94  *  \param[out] CRCDest     CRC Destination when read from the target
  95  *
  96  *  \return Boolean true if the command sequence complete successfully
  97  */
  98 bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)
  99 {
 100         /* Wait until the NVM controller is no longer busy */
 101         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 102           return false;
 103
 104         /* Set the NVM command to the correct CRC read command */
 105         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 106         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 107         PDITarget_SendByte(CRCCommand);
 108
 109         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
 110         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 111         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 112         PDITarget_SendByte(1 << 0);
 113
 114         /* Wait until the NVM bus is ready again */
 115         if (!(PDITarget_WaitWhileNVMBusBusy()))
 116           return false;
 117
 118         /* Wait until the NVM controller is no longer busy */
 119         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 120           return false;
 121
 122         *CRCDest = 0;
 123
 124         /* Read the first generated CRC byte value */
 125         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 126         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 127         *CRCDest  = PDITarget_ReceiveByte();
 128
 129         /* Read the second generated CRC byte value */
 130         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 131         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 132         *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 133
 134         /* Read the third generated CRC byte value */
 135         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 136         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 137         *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 138
 139         return true;
 140 }
 141
 142 /** Reads memory from the target's memory spaces.
 143  *
 144  *  \param[in]  ReadAddress  Start address to read from within the target's address space
 145  *  \param[out] ReadBuffer   Buffer to store read data into
 146  *  \param[in]  ReadSize     Number of bytes to read
 147  *
 148  *  \return Boolean true if the command sequence complete successfully
 149  */
 150 bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)
 151 {
 152         /* Wait until the NVM controller is no longer busy */
 153         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 154           return false;
 155
 156         /* Send the READNVM command to the NVM controller for reading of an arbitrary location */
 157         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 158         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 159         PDITarget_SendByte(NVM_CMD_READNVM);
 160
 161         /* Load the PDI pointer register with the start address we want to read from */
 162         PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 163         NVMTarget_SendAddress(ReadAddress);
 164
 165         /* Send the REPEAT command with the specified number of bytes to read */
 166         PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 167         PDITarget_SendByte(ReadSize - 1);
 168
 169         /* Send a LD command with indirect access and postincrement to read out the bytes */
 170         PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 171         for (uint16_t i = 0; i < ReadSize; i++)
 172           *(ReadBuffer++) = PDITarget_ReceiveByte();
 173
 174         return true;
 175 }
 176
 177 /** Writes byte addressed memory to the target's memory spaces.
 178  *
 179  *  \param[in]  WriteCommand  Command to send to the device to write each memory byte
 180  *  \param[in]  WriteAddress  Start address to write to within the target's address space
 181  *  \param[in]  WriteBuffer   Buffer to source data from
 182  *
 183  *  \return Boolean true if the command sequence complete successfully
 184  */
 185 bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)
 186 {
 187         /* Wait until the NVM controller is no longer busy */
 188         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 189           return false;
 190
 191         /* Send the memory write command to the target */
 192         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 193         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 194         PDITarget_SendByte(WriteCommand);
 195
 196         /* Send new memory byte to the memory to the target */
 197         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 198         NVMTarget_SendAddress(WriteAddress);
 199         PDITarget_SendByte(*(WriteBuffer++));
 200
 201         return true;
 202 }
 203
 204 /** Writes page addressed memory to the target's memory spaces.
 205  *
 206  *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer
 207  *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer
 208  *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory
 209  *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page
 210  *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space
 211  *  \param[in]  WriteBuffer       Buffer to source data from
 212  *  \param[in]  WriteSize         Number of bytes to write
 213  *
 214  *  \return Boolean true if the command sequence complete successfully
 215  */
 216 bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand,
 217                                const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,
 218                                const uint8_t* WriteBuffer, const uint16_t WriteSize)
 219 {
 220         if (PageMode & XPRG_PAGEMODE_ERASE)
 221         {
 222                 /* Wait until the NVM controller is no longer busy */
 223                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 224                   return false;
 225
 226                 /* Send the memory buffer erase command to the target */
 227                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 228                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 229                 PDITarget_SendByte(EraseBuffCommand);
 230
 231                 /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
 232                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 233                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 234                 PDITarget_SendByte(1 << 0);
 235         }
 236
 237         if (WriteSize)
 238         {
 239                 /* Wait until the NVM controller is no longer busy */
 240                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 241                   return false;
 242
 243                 /* Send the memory buffer write command to the target */
 244                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 245                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 246                 PDITarget_SendByte(WriteBuffCommand);
 247
 248                 /* Load the PDI pointer register with the start address we want to write to */
 249                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 250                 NVMTarget_SendAddress(WriteAddress);
 251
 252                 /* Send the REPEAT command with the specified number of bytes to write */
 253                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 254                 PDITarget_SendByte(WriteSize - 1);
 255
 256                 /* Send a ST command with indirect access and postincrement to write the bytes */
 257                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 258                 for (uint16_t i = 0; i < WriteSize; i++)
 259                   PDITarget_SendByte(*(WriteBuffer++));
 260         }
 261
 262         if (PageMode & XPRG_PAGEMODE_WRITE)
 263         {
 264                 /* Wait until the NVM controller is no longer busy */
 265                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 266                   return false;
 267
 268                 /* Send the memory write command to the target */
 269                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 270                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 271                 PDITarget_SendByte(WritePageCommand);
 272
 273                 /* Send the address of the first page location to write the memory page */
 274                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 275                 NVMTarget_SendAddress(WriteAddress);
 276                 PDITarget_SendByte(0x00);
 277         }
 278
 279         return true;
 280 }
 281
 282 /** Erases a specific memory space of the target.
 283  *
 284  *  \param[in] EraseCommand  NVM erase command to send to the device
 285  *  \param[in] Address  Address inside the memory space to erase
 286  *
 287  *  \return Boolean true if the command sequence complete successfully
 288  */
 289 bool NVMTarget_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)
 290 {
 291         /* Wait until the NVM controller is no longer busy */
 292         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 293           return false;
 294
 295         /* Send the memory erase command to the target */
 296         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 297         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 298         PDITarget_SendByte(EraseCommand);
 299
 300         /* Chip erase is handled separately, since it's procedure is different to other erase types */
 301         if (EraseCommand == NVM_CMD_CHIPERASE)
 302         {
 303                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 304                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 305                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 306                 PDITarget_SendByte(1 << 0);
 307         }
 308         else
 309         {
 310                 /* Other erase modes just need us to address a byte within the target memory space */
 311                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 312                 NVMTarget_SendAddress(Address);
 313                 PDITarget_SendByte(0x00);
 314         }
 315
 316         /* Wait until the NVM bus is ready again */
 317         if (!(PDITarget_WaitWhileNVMBusBusy()))
 318           return false;
 319
 320         return true;
 321 }
 322
 323 #endif