Projects/XPLAINBridge/Lib/SoftUART.c

   1 /*
   2                          LUFA Library
   3          Copyright (C) Dean Camera, 2010.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6           www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2010  David Prentice (david.prentice [at] farming [dot] uk)
  11   Copyright 2010  Peter Danneger
  12   Copyright 2010  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  13
  14   Permission to use, copy, modify, distribute, and sell this
  15   software and its documentation for any purpose is hereby granted
  16   without fee, provided that the above copyright notice appear in
  17   all copies and that both that the copyright notice and this
  18   permission notice and warranty disclaimer appear in supporting
  19   documentation, and that the name of the author not be used in
  20   advertising or publicity pertaining to distribution of the
  21   software without specific, written prior permission.
  22
  23   The author disclaim all warranties with regard to this
  24   software, including all implied warranties of merchantability
  25   and fitness.  In no event shall the author be liable for any
  26   special, indirect or consequential damages or any damages
  27   whatsoever resulting from loss of use, data or profits, whether
  28   in an action of contract, negligence or other tortious action,
  29   arising out of or in connection with the use or performance of
  30   this software.
  31 */
  32
  33 #include "SoftUART.h"
  34
  35 volatile bool    srx_done;
  36 volatile uint8_t stx_count;
  37 static   uint8_t srx_data, srx_mask, srx_tmp, stx_data;
  38
  39 void SoftUART_TxByte(uint8_t Byte)
  40 {
  41         while (stx_count);
  42
  43         stx_data  = ~Byte;
  44         stx_count = 10;
  45 }
  46
  47 uint8_t SoftUART_RxByte(void)
  48 {
  49         while (!(srx_done));
  50         srx_done = false;
  51
  52         return srx_data;
  53 }
  54
  55 void SoftUART_Init(void)
  56 {
  57         OCR2B  = TCNT2 + 1;                                             // force first compare
  58         TCCR2A = (1 << COM2B1) | (1 << COM2B0); // T1 mode 0
  59         TCCR2B = (1 << FOC2B)  | (1 << CS21);   // CLK/8, T1 mode 0
  60         TIMSK2 = (1 << OCIE2B);                                 // enable tx and wait for start
  61         EICRA  = (1 << ISC01);                                  // -ve edge
  62         EIMSK  = (1 << INT0);                                   // enable INT0 interrupt
  63
  64         stx_count = 0;                                                  // nothing to send
  65         srx_done  = false;                                              // nothing received
  66         STXPORT |= (1 << STX);                                  // TX output
  67         STXDDR  |= (1 << STX);                                  // TX output
  68         SRXPORT |= (1 << SRX);                                  // pullup on INT0
  69 }
  70
  71 /* ISR to detect the start of a bit being sent from the transmitter. */
  72 ISR(INT0_vect)
  73 {
  74         OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start
  75
  76         srx_tmp  = 0;                                                   // clear bit storage
  77         srx_mask = 1;                                                   // bit mask
  78
  79         TIFR2 = (1 << OCF2A);                                   // clear pending interrupt
  80
  81         if (!(SRXPIN & (1 << SRX)))                             // still low
  82         {
  83                 TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
  84                 EIMSK &= ~(1 << INT0);
  85         }
  86 }
  87
  88 /* ISR to manage the reception of bits to the transmitter. */
  89 ISR(TIMER2_COMPA_vect)
  90 {
  91         if (srx_mask)
  92         {
  93                 if (SRXPIN & (1 << SRX))
  94                   srx_tmp |= srx_mask;
  95
  96                 srx_mask <<= 1;
  97
  98                 OCR2A += BIT_TIME / 8;                          // next bit slice
  99         }
 100         else
 101         {
 102                 srx_done  = true;                                       // mark rx data valid
 103                 srx_data  = srx_tmp;                            // store rx data
 104                 TIMSK2    = (1 << OCIE2B);                      // enable tx and wait for start
 105                 EIMSK    |= (1 << INT0);                        // enable START irq
 106                 EIFR      = (1 << INTF0);                       // clear any pending
 107         }
 108 }
 109
 110 /* ISR to manage the transmission of bits to the receiver. */
 111 ISR(TIMER2_COMPB_vect)
 112 {
 113         OCR2B += BIT_TIME / 8;                                  // next bit slice
 114
 115         if (stx_count)
 116         {
 117                 if (--stx_count != 9)                           // no start bit
 118                 {
 119                         if (!(stx_data & 1))                    // test inverted data
 120                           TCCR2A = (1 << COM2B1) | (1 << COM2B0);
 121                         else
 122                           TCCR2A = (1 << COM2B1);
 123
 124                         stx_data >>= 1;                                 // shift zero in from left
 125                 }
 126                 else
 127                 {
 128                         TCCR2A = (1 << COM2B1);                 // START bit
 129                 }
 130         }
 131 }