Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Sends the given NVM register address to the target.
  42  *
  43  *  \param[in] Register  NVM register whose absolute address is to be sent
  44  */
  45 void NVMTarget_SendNVMRegAddress(uint8_t Register)
  46 {
  47         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  48         uint32_t Address = XPROG_Param_NVMBase | Register;
  49
  50         /* Send the calculated 32-bit address to the target, LSB first */
  51         PDITarget_SendByte(Address &  0xFF);
  52         PDITarget_SendByte(Address >> 8);
  53         PDITarget_SendByte(Address >> 16);
  54         PDITarget_SendByte(Address >> 24);
  55 }
  56
  57 /** Sends the given 32-bit absolute address to the target.
  58  *
  59  *  \param[in] AbsoluteAddress  Absolute address to send to the target
  60  */
  61 void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
  62 {
  63         /* Send the given 32-bit address to the target, LSB first */
  64         PDITarget_SendByte(AbsoluteAddress &  0xFF);
  65         PDITarget_SendByte(AbsoluteAddress >> 8);
  66         PDITarget_SendByte(AbsoluteAddress >> 16);
  67         PDITarget_SendByte(AbsoluteAddress >> 24);
  68 }
  69
  70 /** Waits while the target's NVM controller is busy performing an operation, exiting if the
  71  *  timeout period expires.
  72  *
  73  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
  74  */
  75 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  76 {
  77         TCNT0 = 0;
  78
  79         /* Poll the NVM STATUS register while the NVM controller is busy */
  80         while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
  81         {
  82                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  83                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  84                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  85
  86                 /* Check to see if the BUSY flag is still set */
  87                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  88                   return true;
  89         }
  90
  91         return false;
  92 }
  93
  94 /** Retrieves the CRC value of the given memory space.
  95  *
  96  *  \param[in]  CRCCommand  NVM CRC command to issue to the target
  97  *  \param[out] CRCDest     CRC Destination when read from the target
  98  *
  99  *  \return Boolean true if the command sequence complete successfully
 100  */
 101 bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)
 102 {
 103         /* Wait until the NVM controller is no longer busy */
 104         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 105           return false;
 106
 107         /* Set the NVM command to the correct CRC read command */
 108         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 109         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 110         PDITarget_SendByte(CRCCommand);
 111
 112         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
 113         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 114         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 115         PDITarget_SendByte(1 << 0);
 116
 117         /* Wait until the NVM bus is ready again */
 118         if (!(PDITarget_WaitWhileNVMBusBusy()))
 119           return false;
 120
 121         /* Wait until the NVM controller is no longer busy */
 122         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 123           return false;
 124
 125         *CRCDest = 0;
 126
 127         /* Read the first generated CRC byte value */
 128         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 129         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 130         *CRCDest  = PDITarget_ReceiveByte();
 131
 132         /* Read the second generated CRC byte value */
 133         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 134         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 135         *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 136
 137         /* Read the third generated CRC byte value */
 138         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 139         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 140         *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 141
 142         return true;
 143 }
 144
 145 /** Reads memory from the target's memory spaces.
 146  *
 147  *  \param[in]  ReadAddress  Start address to read from within the target's address space
 148  *  \param[out] ReadBuffer   Buffer to store read data into
 149  *  \param[in]  ReadSize     Number of bytes to read
 150  *
 151  *  \return Boolean true if the command sequence complete successfully
 152  */
 153 bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
 154 {
 155         /* Wait until the NVM controller is no longer busy */
 156         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 157           return false;
 158
 159         /* Send the READNVM command to the NVM controller for reading of an arbitrary location */
 160         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 161         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 162         PDITarget_SendByte(NVM_CMD_READNVM);
 163
 164         /* Load the PDI pointer register with the start address we want to read from */
 165         PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 166         NVMTarget_SendAddress(ReadAddress);
 167
 168         /* Send the REPEAT command with the specified number of bytes to read */
 169         PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 170         PDITarget_SendByte(ReadSize - 1);
 171
 172         /* Send a LD command with indirect access and postincrement to read out the bytes */
 173         PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 174         for (uint16_t i = 0; i < ReadSize; i++)
 175           *(ReadBuffer++) = PDITarget_ReceiveByte();
 176
 177         return true;
 178 }
 179
 180 /** Writes byte addressed memory to the target's memory spaces.
 181  *
 182  *  \param[in]  WriteCommand  Command to send to the device to write each memory byte
 183  *  \param[in]  WriteAddress  Start address to write to within the target's address space
 184  *  \param[in]  WriteBuffer   Buffer to source data from
 185  *
 186  *  \return Boolean true if the command sequence complete successfully
 187  */
 188 bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer)
 189 {
 190         /* Wait until the NVM controller is no longer busy */
 191         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 192           return false;
 193
 194         /* Send the memory write command to the target */
 195         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 196         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 197         PDITarget_SendByte(WriteCommand);
 198
 199         /* Send new memory byte to the memory to the target */
 200         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 201         NVMTarget_SendAddress(WriteAddress++);
 202         PDITarget_SendByte(*(WriteBuffer++));
 203
 204         return true;
 205 }
 206
 207 /** Writes page addressed memory to the target's memory spaces.
 208  *
 209  *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer
 210  *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer
 211  *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory
 212  *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page
 213  *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space
 214  *  \param[in]  WriteBuffer       Buffer to source data from
 215  *  \param[in]  WriteSize         Number of bytes to write
 216  *
 217  *  \return Boolean true if the command sequence complete successfully
 218  */
 219 bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,
 220                                uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
 221 {
 222         if (PageMode & XPRG_PAGEMODE_ERASE)
 223         {
 224                 /* Wait until the NVM controller is no longer busy */
 225                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 226                   return false;
 227
 228                 /* Send the memory buffer erase command to the target */
 229                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 230                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 231                 PDITarget_SendByte(EraseBuffCommand);
 232
 233                 /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
 234                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 235                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 236                 PDITarget_SendByte(1 << 0);
 237         }
 238
 239         if (WriteSize)
 240         {
 241                 /* Wait until the NVM controller is no longer busy */
 242                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 243                   return false;
 244
 245                 /* Send the memory buffer write command to the target */
 246                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 247                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 248                 PDITarget_SendByte(WriteBuffCommand);
 249
 250                 /* Load the PDI pointer register with the start address we want to write to */
 251                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 252                 NVMTarget_SendAddress(WriteAddress);
 253
 254                 /* Send the REPEAT command with the specified number of bytes to write */
 255                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 256                 PDITarget_SendByte(WriteSize - 1);
 257
 258                 /* Send a ST command with indirect access and postincrement to write the bytes */
 259                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 260                 for (uint16_t i = 0; i < WriteSize; i++)
 261                   PDITarget_SendByte(*(WriteBuffer++));
 262         }
 263
 264         if (PageMode & XPRG_PAGEMODE_WRITE)
 265         {
 266                 /* Wait until the NVM controller is no longer busy */
 267                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 268                   return false;
 269
 270                 /* Send the memory write command to the target */
 271                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 272                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 273                 PDITarget_SendByte(WritePageCommand);
 274
 275                 /* Send the address of the first page location to write the memory page */
 276                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 277                 NVMTarget_SendAddress(WriteAddress);
 278                 PDITarget_SendByte(0x00);
 279         }
 280
 281         return true;
 282 }
 283
 284 /** Erases a specific memory space of the target.
 285  *
 286  *  \param[in] EraseCommand  NVM erase command to send to the device
 287  *  \param[in] Address  Address inside the memory space to erase
 288  *
 289  *  \return Boolean true if the command sequence complete successfully
 290  */
 291 bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
 292 {
 293         /* Wait until the NVM controller is no longer busy */
 294         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 295           return false;
 296
 297         /* Send the memory erase command to the target */
 298         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 299         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 300         PDITarget_SendByte(EraseCommand);
 301
 302         /* Chip erase is handled separately, since it's procedure is different to other erase types */
 303         if (EraseCommand == NVM_CMD_CHIPERASE)
 304         {
 305                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 306                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 307                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 308                 PDITarget_SendByte(1 << 0);
 309         }
 310         else
 311         {
 312                 /* Other erase modes just need us to address a byte within the target memory space */
 313                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 314                 NVMTarget_SendAddress(Address);
 315                 PDITarget_SendByte(0x00);
 316         }
 317
 318         /* Wait until the NVM bus is ready again */
 319         if (!(PDITarget_WaitWhileNVMBusBusy()))
 320           return false;
 321
 322         return true;
 323 }
 324
 325 #endif