Projects/AVRISP/Lib/TPI/TPITarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the TPI Protocol decoder.
  34  */
  35
  36 #define  INCLUDE_FROM_TPITARGET_C
  37 #include "TPITarget.h"
  38
  39 #if defined(ENABLE_TPI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Flag to indicate if the USART is currently in Tx or Rx mode. */
  42 volatile bool               IsSending;
  43
  44 #if !defined(TPI_VIA_HARDWARE_USART)
  45 /** Software USART raw frame bits for transmission/reception. */
  46 volatile uint16_t           SoftUSART_Data;
  47
  48 /** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */
  49 #define SoftUSART_BitCount  GPIOR2
  50
  51
  52 /** ISR to manage the software USART when bit-banged USART mode is selected. */
  53 ISR(TIMER1_CAPT_vect, ISR_BLOCK)
  54 {
  55         /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
  56         BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;
  57
  58         /* If not sending or receiving, just exit */
  59         if (!(SoftUSART_BitCount))
  60           return;
  61
  62         /* Check to see if we are at a rising or falling edge of the clock */
  63         if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
  64         {
  65                 /* If at rising clock edge and we are in send mode, abort */
  66                 if (IsSending)
  67                   return;
  68
  69                 /* Wait for the start bit when receiving */
  70                 if ((SoftUSART_BitCount == BITS_IN_TPI_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
  71                   return;
  72
  73                 /* Shift in the bit one less than the frame size in position, so that the start bit will eventually
  74                  * be discarded leaving the data to be byte-aligned for quick access */
  75                 if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
  76                   SoftUSART_Data |= (1 << (BITS_IN_TPI_FRAME - 1));
  77
  78                 SoftUSART_Data >>= 1;
  79                 SoftUSART_BitCount--;
  80         }
  81         else
  82         {
  83                 /* If at falling clock edge and we are in receive mode, abort */
  84                 if (!IsSending)
  85                   return;
  86
  87                 /* Set the data line to the next bit value */
  88                 if (SoftUSART_Data & 0x01)
  89                   BITBANG_TPIDATA_PORT |=  BITBANG_TPIDATA_MASK;
  90                 else
  91                   BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
  92
  93                 SoftUSART_Data >>= 1;
  94                 SoftUSART_BitCount--;
  95         }
  96 }
  97 #endif
  98
  99 /** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
 100 void TPITarget_EnableTargetTPI(void)
 101 {
 102         /* Set /RESET line low for at least 90ns to enable TPI functionality */
 103         RESET_LINE_DDR  |= RESET_LINE_MASK;
 104         RESET_LINE_PORT &= ~RESET_LINE_MASK;
 105         asm volatile ("NOP"::);
 106         asm volatile ("NOP"::);
 107
 108 #if defined(TPI_VIA_HARDWARE_USART)
 109         /* Set Tx and XCK as outputs, Rx as input */
 110         DDRD |=  (1 << 5) | (1 << 3);
 111         DDRD &= ~(1 << 2);
 112
 113         /* Set up the synchronous USART for XMEGA communications -
 114            8 data bits, even parity, 2 stop bits */
 115         UBRR1  = (F_CPU / 1000000UL);
 116         UCSR1B = (1 << TXEN1);
 117         UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
 118
 119         /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
 120         TPITarget_SendBreak();
 121         TPITarget_SendBreak();
 122 #else
 123         /* Set DATA and CLOCK lines to outputs */
 124         BITBANG_TPIDATA_DDR  |= BITBANG_TPIDATA_MASK;
 125         BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
 126
 127         /* Set DATA line high for idle state */
 128         BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
 129
 130         /* Fire timer capture ISR every 100 cycles to manage the software USART */
 131         OCR1A   = 80;
 132         TCCR1B  = (1 << WGM13) | (1 << WGM12) | (1 << CS10);
 133         TIMSK1  = (1 << ICIE1);
 134
 135         /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
 136         TPITarget_SendBreak();
 137         TPITarget_SendBreak();
 138 #endif
 139 }
 140
 141 /** Disables the target's TPI interface, exits programming mode and starts the target's application. */
 142 void TPITarget_DisableTargetTPI(void)
 143 {
 144 #if defined(TPI_VIA_HARDWARE_USART)
 145         /* Turn off receiver and transmitter of the USART, clear settings */
 146         UCSR1A |= (1 << TXC1) | (1 << RXC1);
 147         UCSR1B  = 0;
 148         UCSR1C  = 0;
 149
 150         /* Set all USART lines as input, tristate */
 151         DDRD  &= ~((1 << 5) | (1 << 3));
 152         PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
 153 #else
 154         /* Set DATA and CLOCK lines to inputs */
 155         BITBANG_TPIDATA_DDR   &= ~BITBANG_TPIDATA_MASK;
 156         BITBANG_TPICLOCK_DDR  &= ~BITBANG_TPICLOCK_MASK;
 157
 158         /* Tristate DATA and CLOCK lines */
 159         BITBANG_TPIDATA_PORT  &= ~BITBANG_TPIDATA_MASK;
 160         BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;
 161 #endif
 162
 163         /* Tristate target /RESET line */
 164         RESET_LINE_DDR  &= ~RESET_LINE_MASK;
 165         RESET_LINE_PORT &= ~RESET_LINE_MASK;
 166 }
 167
 168 /** Sends a byte via the USART.
 169  *
 170  *  \param[in] Byte  Byte to send through the USART
 171  */
 172 void TPITarget_SendByte(const uint8_t Byte)
 173 {
 174 #if defined(TPI_VIA_HARDWARE_USART)
 175         /* Switch to Tx mode if currently in Rx mode */
 176         if (!(IsSending))
 177         {
 178                 PORTD  |=  (1 << 3);
 179                 DDRD   |=  (1 << 3);
 180
 181                 UCSR1B |=  (1 << TXEN1);
 182                 UCSR1B &= ~(1 << RXEN1);
 183
 184                 IsSending = true;
 185         }
 186
 187         /* Wait until there is space in the hardware Tx buffer before writing */
 188         while (!(UCSR1A & (1 << UDRE1)));
 189         UCSR1A |= (1 << TXC1);
 190         UDR1    = Byte;
 191 #else
 192         /* Switch to Tx mode if currently in Rx mode */
 193         if (!(IsSending))
 194         {
 195                 BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
 196                 BITBANG_TPIDATA_DDR  |= BITBANG_TPIDATA_MASK;
 197
 198                 IsSending = true;
 199         }
 200
 201         /* Calculate the new USART frame data here while while we wait for a previous byte (if any) to finish sending */
 202         uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));
 203
 204         /* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */
 205         uint8_t ParityData    = Byte;
 206         while (ParityData)
 207         {
 208                 NewUSARTData ^= (1 << 9);
 209                 ParityData   &= (ParityData - 1);
 210         }
 211
 212         /* Wait until transmitter is idle before writing new data */
 213         while (SoftUSART_BitCount);
 214
 215         /* Data shifted out LSB first, START DATA PARITY STOP STOP */
 216         SoftUSART_Data     = NewUSARTData;
 217         SoftUSART_BitCount = BITS_IN_TPI_FRAME;
 218 #endif
 219 }
 220
 221 /** Receives a byte via the software USART, blocking until data is received.
 222  *
 223  *  \return Received byte from the USART
 224  */
 225 uint8_t TPITarget_ReceiveByte(void)
 226 {
 227 #if defined(TPI_VIA_HARDWARE_USART)
 228         /* Switch to Rx mode if currently in Tx mode */
 229         if (IsSending)
 230         {
 231                 while (!(UCSR1A & (1 << TXC1)));
 232                 UCSR1A |=  (1 << TXC1);
 233
 234                 UCSR1B &= ~(1 << TXEN1);
 235                 UCSR1B |=  (1 << RXEN1);
 236
 237                 DDRD   &= ~(1 << 3);
 238                 PORTD  &= ~(1 << 3);
 239
 240                 IsSending = false;
 241         }
 242
 243         /* Wait until a byte has been received before reading */
 244         while (!(UCSR1A & (1 << RXC1)));
 245         return UDR1;
 246 #else
 247         /* Switch to Rx mode if currently in Tx mode */
 248         if (IsSending)
 249         {
 250                 while (SoftUSART_BitCount);
 251
 252                 BITBANG_TPIDATA_DDR  &= ~BITBANG_TPIDATA_MASK;
 253                 BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
 254
 255                 IsSending = false;
 256         }
 257
 258         /* Wait until a byte has been received before reading */
 259         SoftUSART_BitCount = BITS_IN_TPI_FRAME;
 260         while (SoftUSART_BitCount);
 261
 262         /* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */
 263         return (uint8_t)SoftUSART_Data;
 264 #endif
 265 }
 266
 267 /** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
 268 void TPITarget_SendBreak(void)
 269 {
 270 #if defined(TPI_VIA_HARDWARE_USART)
 271         /* Switch to Tx mode if currently in Rx mode */
 272         if (!(IsSending))
 273         {
 274                 PORTD  |=  (1 << 3);
 275                 DDRD   |=  (1 << 3);
 276
 277                 UCSR1B &= ~(1 << RXEN1);
 278                 UCSR1B |=  (1 << TXEN1);
 279
 280                 IsSending = true;
 281         }
 282
 283         /* Need to do nothing for a full frame to send a BREAK */
 284         for (uint8_t i = 0; i < BITS_IN_TPI_FRAME; i++)
 285         {
 286                 /* Wait for a full cycle of the clock */
 287                 while (PIND & (1 << 5));
 288                 while (!(PIND & (1 << 5)));
 289         }
 290 #else
 291         /* Switch to Tx mode if currently in Rx mode */
 292         if (!(IsSending))
 293         {
 294                 BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
 295                 BITBANG_TPIDATA_DDR  |= BITBANG_TPIDATA_MASK;
 296
 297                 IsSending = true;
 298         }
 299
 300         while (SoftUSART_BitCount);
 301
 302         /* Need to do nothing for a full frame to send a BREAK */
 303         SoftUSART_Data     = 0x0FFF;
 304         SoftUSART_BitCount = BITS_IN_TPI_FRAME;
 305 #endif
 306 }
 307
 308 /** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC
 309  *  calculation.
 310  *
 311  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
 312  */
 313 bool TPITarget_WaitWhileNVMBusBusy(void)
 314 {
 315         TCNT0 = 0;
 316         TIFR0 = (1 << OCF1A);
 317
 318         uint8_t TimeoutMS = TPI_NVM_TIMEOUT_MS;
 319
 320         /* Poll the STATUS register to check to see if NVM access has been enabled */
 321         while (TimeoutMS)
 322         {
 323                 /* Send the LDCS command to read the TPI STATUS register to see the NVM bus is active */
 324                 TPITarget_SendByte(TPI_CMD_SLDCS | TPI_STATUS_REG);
 325                 if (TPITarget_ReceiveByte() & TPI_STATUS_NVM)
 326                   return true;
 327
 328                 if (TIFR0 & (1 << OCF1A))
 329                 {
 330                         TIFR0 = (1 << OCF1A);
 331                         TimeoutMS--;
 332                 }
 333         }
 334
 335         return false;
 336 }
 337
 338 #endif