Projects/AVRISP/Lib/PDI/PDITarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the PDI Protocol decoder.
  34  */
  35
  36 #define  INCLUDE_FROM_PDITARGET_C
  37 #include "PDITarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Flag to indicate if the USART is currently in Tx or Rx mode. */
  42 volatile bool               IsSending;
  43
  44 #if !defined(PDI_VIA_HARDWARE_USART)
  45 /** Software USART raw frame bits for transmission/reception. */
  46 volatile uint16_t           SoftUSART_Data;
  47
  48 /** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */
  49 #define SoftUSART_BitCount  GPIOR2
  50
  51
  52 /** ISR to manage the software USART when bit-banged USART mode is selected. */
  53 ISR(TIMER1_COMPA_vect, ISR_BLOCK)
  54 {
  55         /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
  56         BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;
  57
  58         /* If not sending or receiving, just exit */
  59         if (!(SoftUSART_BitCount))
  60           return;
  61
  62         /* Check to see if we are at a rising or falling edge of the clock */
  63         if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)
  64         {
  65                 /* If at rising clock edge and we are in send mode, abort */
  66                 if (IsSending)
  67                   return;
  68
  69                 /* Wait for the start bit when receiving */
  70                 if ((SoftUSART_BitCount == BITS_IN_PDI_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
  71                   return;
  72
  73                 /* Shift in the bit one less than the frame size in position, so that the start bit will eventually
  74                  * be discarded leaving the data to be byte-aligned for quick access */
  75                 if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
  76                   SoftUSART_Data |= (1 << (BITS_IN_PDI_FRAME - 1));
  77
  78                 SoftUSART_Data >>= 1;
  79                 SoftUSART_BitCount--;
  80         }
  81         else
  82         {
  83                 /* If at falling clock edge and we are in receive mode, abort */
  84                 if (!IsSending)
  85                   return;
  86
  87                 /* Set the data line to the next bit value */
  88                 if (SoftUSART_Data & 0x01)
  89                   BITBANG_PDIDATA_PORT |=  BITBANG_PDIDATA_MASK;
  90                 else
  91                   BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
  92
  93                 SoftUSART_Data >>= 1;
  94                 SoftUSART_BitCount--;
  95         }
  96 }
  97 #endif
  98
  99 /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
 100 void PDITarget_EnableTargetPDI(void)
 101 {
 102 #if defined(PDI_VIA_HARDWARE_USART)
 103         /* Set Tx and XCK as outputs, Rx as input */
 104         DDRD |=  (1 << 5) | (1 << 3);
 105         DDRD &= ~(1 << 2);
 106
 107         /* Set DATA line high for at least 90ns to disable /RESET functionality */
 108         PORTD |= (1 << 3);
 109         asm volatile ("NOP"::);
 110         asm volatile ("NOP"::);
 111
 112         /* Set up the synchronous USART for XMEGA communications -
 113            8 data bits, even parity, 2 stop bits */
 114         UBRR1  = (F_CPU / 1000000UL);
 115         UCSR1B = (1 << TXEN1);
 116         UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
 117
 118         /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
 119         PDITarget_SendBreak();
 120         PDITarget_SendBreak();
 121 #else
 122         /* Set DATA and CLOCK lines to outputs */
 123         BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
 124         BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
 125
 126         /* Set DATA line high for at least 90ns to disable /RESET functionality */
 127         BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
 128         asm volatile ("NOP"::);
 129         asm volatile ("NOP"::);
 130
 131         /* Fire timer compare ISR every 100 cycles to manage the software USART */
 132         OCR1A   = 80;
 133         TCCR1B  = (1 << WGM12) | (1 << CS10);
 134         TIMSK1  = (1 << OCIE1A);
 135
 136         /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
 137         PDITarget_SendBreak();
 138         PDITarget_SendBreak();
 139 #endif
 140 }
 141
 142 /** Disables the target's PDI interface, exits programming mode and starts the target's application. */
 143 void PDITarget_DisableTargetPDI(void)
 144 {
 145 #if defined(PDI_VIA_HARDWARE_USART)
 146         /* Turn off receiver and transmitter of the USART, clear settings */
 147         UCSR1A |= (1 << TXC1) | (1 << RXC1);
 148         UCSR1B  = 0;
 149         UCSR1C  = 0;
 150
 151         /* Set all USART lines as input, tristate */
 152         DDRD  &= ~((1 << 5) | (1 << 3));
 153         PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
 154 #else
 155         /* Set DATA and CLOCK lines to inputs */
 156         BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;
 157         BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;
 158
 159         /* Tristate DATA and CLOCK lines */
 160         BITBANG_PDIDATA_PORT  &= ~BITBANG_PDIDATA_MASK;
 161         BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
 162 #endif
 163 }
 164
 165 /** Sends a byte via the USART.
 166  *
 167  *  \param[in] Byte  Byte to send through the USART
 168  */
 169 void PDITarget_SendByte(const uint8_t Byte)
 170 {
 171 #if defined(PDI_VIA_HARDWARE_USART)
 172         /* Switch to Tx mode if currently in Rx mode */
 173         if (!(IsSending))
 174         {
 175                 PORTD  |=  (1 << 3);
 176                 DDRD   |=  (1 << 3);
 177
 178                 UCSR1B |=  (1 << TXEN1);
 179                 UCSR1B &= ~(1 << RXEN1);
 180
 181                 IsSending = true;
 182         }
 183
 184         /* Wait until there is space in the hardware Tx buffer before writing */
 185         while (!(UCSR1A & (1 << UDRE1)));
 186         UCSR1A |= (1 << TXC1);
 187         UDR1    = Byte;
 188 #else
 189         /* Switch to Tx mode if currently in Rx mode */
 190         if (!(IsSending))
 191         {
 192                 BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
 193                 BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
 194
 195                 IsSending = true;
 196         }
 197
 198         /* Calculate the new USART frame data here while while we wait for a previous byte (if any) to finish sending */
 199         uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));
 200
 201         /* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */
 202         uint8_t ParityData    = Byte;
 203         while (ParityData)
 204         {
 205                 NewUSARTData ^= (1 << 9);
 206                 ParityData   &= (ParityData - 1);
 207         }
 208
 209         /* Wait until transmitter is idle before writing new data */
 210         while (SoftUSART_BitCount);
 211
 212         /* Data shifted out LSB first, START DATA PARITY STOP STOP */
 213         SoftUSART_Data     = NewUSARTData;
 214         SoftUSART_BitCount = BITS_IN_PDI_FRAME;
 215 #endif
 216 }
 217
 218 /** Receives a byte via the software USART, blocking until data is received.
 219  *
 220  *  \return Received byte from the USART
 221  */
 222 uint8_t PDITarget_ReceiveByte(void)
 223 {
 224 #if defined(PDI_VIA_HARDWARE_USART)
 225         /* Switch to Rx mode if currently in Tx mode */
 226         if (IsSending)
 227         {
 228                 while (!(UCSR1A & (1 << TXC1)));
 229                 UCSR1A |=  (1 << TXC1);
 230
 231                 UCSR1B &= ~(1 << TXEN1);
 232                 UCSR1B |=  (1 << RXEN1);
 233
 234                 DDRD   &= ~(1 << 3);
 235                 PORTD  &= ~(1 << 3);
 236
 237                 IsSending = false;
 238         }
 239
 240         /* Wait until a byte has been received before reading */
 241         while (!(UCSR1A & (1 << RXC1)));
 242         return UDR1;
 243 #else
 244         /* Switch to Rx mode if currently in Tx mode */
 245         if (IsSending)
 246         {
 247                 while (SoftUSART_BitCount);
 248
 249                 BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
 250                 BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
 251
 252                 IsSending = false;
 253         }
 254
 255         /* Wait until a byte has been received before reading */
 256         SoftUSART_BitCount = BITS_IN_PDI_FRAME;
 257         while (SoftUSART_BitCount);
 258
 259         /* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */
 260         return (uint8_t)SoftUSART_Data;
 261 #endif
 262 }
 263
 264 /** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
 265 void PDITarget_SendBreak(void)
 266 {
 267 #if defined(PDI_VIA_HARDWARE_USART)
 268         /* Switch to Tx mode if currently in Rx mode */
 269         if (!(IsSending))
 270         {
 271                 PORTD  |=  (1 << 3);
 272                 DDRD   |=  (1 << 3);
 273
 274                 UCSR1B &= ~(1 << RXEN1);
 275                 UCSR1B |=  (1 << TXEN1);
 276
 277                 IsSending = true;
 278         }
 279
 280         /* Need to do nothing for a full frame to send a BREAK */
 281         for (uint8_t i = 0; i < BITS_IN_PDI_FRAME; i++)
 282         {
 283                 /* Wait for a full cycle of the clock */
 284                 while (PIND & (1 << 5));
 285                 while (!(PIND & (1 << 5)));
 286         }
 287 #else
 288         /* Switch to Tx mode if currently in Rx mode */
 289         if (!(IsSending))
 290         {
 291                 BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
 292                 BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
 293
 294                 IsSending = true;
 295         }
 296
 297         while (SoftUSART_BitCount);
 298
 299         /* Need to do nothing for a full frame to send a BREAK */
 300         SoftUSART_Data     = 0x0FFF;
 301         SoftUSART_BitCount = BITS_IN_PDI_FRAME;
 302 #endif
 303 }
 304
 305 /** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC
 306  *  calculation.
 307  *
 308  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
 309  */
 310 bool PDITarget_WaitWhileNVMBusBusy(void)
 311 {
 312         TCNT0 = 0;
 313         TIFR0 = (1 << OCF1A);
 314
 315         uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS;
 316
 317         /* Poll the STATUS register to check to see if NVM access has been enabled */
 318         while (TimeoutMS)
 319         {
 320                 /* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
 321                 PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
 322                 if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
 323                   return true;
 324
 325                 if (TIFR0 & (1 << OCF1A))
 326                 {
 327                         TIFR0 = (1 << OCF1A);
 328                         TimeoutMS--;
 329                 }
 330         }
 331
 332         return false;
 333 }
 334
 335 #endif