Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Sends the given NVM register address to the target.
  42  *
  43  *  \param[in] Register  NVM register whose absolute address is to be sent
  44  */
  45 void NVMTarget_SendNVMRegAddress(uint8_t Register)
  46 {
  47         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  48         uint32_t Address = XPROG_Param_NVMBase | Register;
  49
  50         /* Send the calculated 32-bit address to the target, LSB first */
  51         NVMTarget_SendAddress(Address);
  52 }
  53
  54 /** Waits while the target's NVM controller is busy performing an operation, exiting if the
  55  *  timeout period expires.
  56  *
  57  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
  58  */
  59 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  60 {
  61         TCNT0 = 0;
  62
  63         /* Poll the NVM STATUS register while the NVM controller is busy */
  64         while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
  65         {
  66                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  67                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  68                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  69
  70                 /* Check to see if the BUSY flag is still set */
  71                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  72                   return true;
  73         }
  74
  75         return false;
  76 }
  77
  78 /** Retrieves the CRC value of the given memory space.
  79  *
  80  *  \param[in]  CRCCommand  NVM CRC command to issue to the target
  81  *  \param[out] CRCDest     CRC Destination when read from the target
  82  *
  83  *  \return Boolean true if the command sequence complete successfully
  84  */
  85 bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)
  86 {
  87         /* Wait until the NVM controller is no longer busy */
  88         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
  89           return false;
  90
  91         /* Set the NVM command to the correct CRC read command */
  92         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
  93         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
  94         PDITarget_SendByte(CRCCommand);
  95
  96         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
  97         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
  98         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
  99         PDITarget_SendByte(1 << 0);
 100
 101         /* Wait until the NVM bus is ready again */
 102         if (!(PDITarget_WaitWhileNVMBusBusy()))
 103           return false;
 104
 105         /* Wait until the NVM controller is no longer busy */
 106         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 107           return false;
 108
 109         *CRCDest = 0;
 110
 111         /* Read the first generated CRC byte value */
 112         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 113         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 114         *CRCDest  = PDITarget_ReceiveByte();
 115
 116         /* Read the second generated CRC byte value */
 117         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 118         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 119         *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 120
 121         /* Read the third generated CRC byte value */
 122         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 123         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 124         *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 125
 126         return true;
 127 }
 128
 129 /** Reads memory from the target's memory spaces.
 130  *
 131  *  \param[in]  ReadAddress  Start address to read from within the target's address space
 132  *  \param[out] ReadBuffer   Buffer to store read data into
 133  *  \param[in]  ReadSize     Number of bytes to read
 134  *
 135  *  \return Boolean true if the command sequence complete successfully
 136  */
 137 bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
 138 {
 139         /* Wait until the NVM controller is no longer busy */
 140         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 141           return false;
 142
 143         /* Send the READNVM command to the NVM controller for reading of an arbitrary location */
 144         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 145         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 146         PDITarget_SendByte(NVM_CMD_READNVM);
 147
 148         /* Load the PDI pointer register with the start address we want to read from */
 149         PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 150         NVMTarget_SendAddress(ReadAddress);
 151
 152         /* Send the REPEAT command with the specified number of bytes to read */
 153         PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 154         PDITarget_SendByte(ReadSize - 1);
 155
 156         /* Send a LD command with indirect access and postincrement to read out the bytes */
 157         PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 158         for (uint16_t i = 0; i < ReadSize; i++)
 159           *(ReadBuffer++) = PDITarget_ReceiveByte();
 160
 161         return true;
 162 }
 163
 164 /** Writes byte addressed memory to the target's memory spaces.
 165  *
 166  *  \param[in]  WriteCommand  Command to send to the device to write each memory byte
 167  *  \param[in]  WriteAddress  Start address to write to within the target's address space
 168  *  \param[in]  WriteBuffer   Buffer to source data from
 169  *
 170  *  \return Boolean true if the command sequence complete successfully
 171  */
 172 bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer)
 173 {
 174         /* Wait until the NVM controller is no longer busy */
 175         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 176           return false;
 177
 178         /* Send the memory write command to the target */
 179         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 180         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 181         PDITarget_SendByte(WriteCommand);
 182
 183         /* Send new memory byte to the memory to the target */
 184         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 185         NVMTarget_SendAddress(WriteAddress++);
 186         PDITarget_SendByte(*(WriteBuffer++));
 187
 188         return true;
 189 }
 190
 191 /** Writes page addressed memory to the target's memory spaces.
 192  *
 193  *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer
 194  *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer
 195  *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory
 196  *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page
 197  *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space
 198  *  \param[in]  WriteBuffer       Buffer to source data from
 199  *  \param[in]  WriteSize         Number of bytes to write
 200  *
 201  *  \return Boolean true if the command sequence complete successfully
 202  */
 203 bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,
 204                                uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
 205 {
 206         if (PageMode & XPRG_PAGEMODE_ERASE)
 207         {
 208                 /* Wait until the NVM controller is no longer busy */
 209                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 210                   return false;
 211
 212                 /* Send the memory buffer erase command to the target */
 213                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 214                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 215                 PDITarget_SendByte(EraseBuffCommand);
 216
 217                 /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
 218                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 219                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 220                 PDITarget_SendByte(1 << 0);
 221         }
 222
 223         if (WriteSize)
 224         {
 225                 /* Wait until the NVM controller is no longer busy */
 226                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 227                   return false;
 228
 229                 /* Send the memory buffer write command to the target */
 230                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 231                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 232                 PDITarget_SendByte(WriteBuffCommand);
 233
 234                 /* Load the PDI pointer register with the start address we want to write to */
 235                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 236                 NVMTarget_SendAddress(WriteAddress);
 237
 238                 /* Send the REPEAT command with the specified number of bytes to write */
 239                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
 240                 PDITarget_SendByte(WriteSize - 1);
 241
 242                 /* Send a ST command with indirect access and postincrement to write the bytes */
 243                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 244                 for (uint16_t i = 0; i < WriteSize; i++)
 245                   PDITarget_SendByte(*(WriteBuffer++));
 246         }
 247
 248         if (PageMode & XPRG_PAGEMODE_WRITE)
 249         {
 250                 /* Wait until the NVM controller is no longer busy */
 251                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 252                   return false;
 253
 254                 /* Send the memory write command to the target */
 255                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 256                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 257                 PDITarget_SendByte(WritePageCommand);
 258
 259                 /* Send the address of the first page location to write the memory page */
 260                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 261                 NVMTarget_SendAddress(WriteAddress);
 262                 PDITarget_SendByte(0x00);
 263         }
 264
 265         return true;
 266 }
 267
 268 /** Erases a specific memory space of the target.
 269  *
 270  *  \param[in] EraseCommand  NVM erase command to send to the device
 271  *  \param[in] Address  Address inside the memory space to erase
 272  *
 273  *  \return Boolean true if the command sequence complete successfully
 274  */
 275 bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
 276 {
 277         /* Wait until the NVM controller is no longer busy */
 278         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 279           return false;
 280
 281         /* Send the memory erase command to the target */
 282         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 283         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 284         PDITarget_SendByte(EraseCommand);
 285
 286         /* Chip erase is handled separately, since it's procedure is different to other erase types */
 287         if (EraseCommand == NVM_CMD_CHIPERASE)
 288         {
 289                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 290                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 291                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 292                 PDITarget_SendByte(1 << 0);
 293         }
 294         else
 295         {
 296                 /* Other erase modes just need us to address a byte within the target memory space */
 297                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 298                 NVMTarget_SendAddress(Address);
 299                 PDITarget_SendByte(0x00);
 300         }
 301
 302         /* Wait until the NVM bus is ready again */
 303         if (!(PDITarget_WaitWhileNVMBusBusy()))
 304           return false;
 305
 306         return true;
 307 }
 308
 309 #endif