Add option to the USB XMEGAs to set the USB bus interrupt priority level.

[pub/lufa.git] / LUFA / Drivers / USB / Core / XMEGA / USBController_XMEGA.h

diff --git a/LUFA/Drivers/USB/Core/XMEGA/USBController_XMEGA.h b/LUFA/Drivers/USB/Core/XMEGA/USBController_XMEGA.h
index 45cfe59..f6c4a7a 100644 (file)
--- a/LUFA/Drivers/USB/Core/XMEGA/USBController_XMEGA.h
+++ b/LUFA/Drivers/USB/Core/XMEGA/USBController_XMEGA.h
@@ -84,7 +84,25 @@
                #endif\r
 \r
        /* Public Interface - May be used in end-application: */\r
-               /* Macros: */                   \r
+               /* Macros: */\r
+                       /** \name USB Controller Option Masks */\r
+                       //@{\r
+                       /** Sets the USB bus interrupt priority level to be low priority. The USB bus interrupt is used for Start of Frame events, bus suspend\r
+                        *  and resume events, bus reset events and other events related to the management of the USB bus.\r
+                        */\r
+                       #define USB_OPT_BUSEVENT_PRILOW           ((0 << 1) | (0 << 1))\r
+\r
+                       /** Sets the USB bus interrupt priority level to be medium priority. The USB bus interrupt is used for Start of Frame events, bus suspend\r
+                        *  and resume events, bus reset events and other events related to the management of the USB bus.\r
+                        */\r
+                       #define USB_OPT_BUSEVENT_PRIMED           ((0 << 1) | (1 << 1))\r
+\r
+                       /** Sets the USB bus interrupt priority level to be high priority. The USB bus interrupt is used for Start of Frame events, bus suspend\r
+                        *  and resume events, bus reset events and other events related to the management of the USB bus.\r
+                        */\r
+                       #define USB_OPT_BUSEVENT_PRIHIGH          ((1 << 1) | (0 << 1))\r
+                       //@}\r
+\r
                        /** \name Endpoint/Pipe Type Masks */\r
                        //@{\r
                        /** Mask for a CONTROL type endpoint or pipe.\r