* in slower transfers as only one USB device (the AVR or the host) can access the endpoint's\r
* bank at the one time.\r
*/\r
- #define ENDPOINT_BANK_SINGLE AVR32_USBB_UECFG0_EPBK0_SINGLE\r
+ #define ENDPOINT_BANK_SINGLE AVR32_USBB_UECFG0_EPBK_SINGLE\r
\r
/** Mask for the bank mode selection for the \ref Endpoint_ConfigureEndpoint() macro. This indicates\r
* that the endpoint should have two banks, which requires more USB FIFO memory but results\r
* in faster transfers as one USB device (the AVR or the host) can access one bank while the other\r
* accesses the second bank.\r
*/\r
- #define ENDPOINT_BANK_DOUBLE AVR32_USBB_UECFG0_EPBK0_DOUBLE\r
+ #define ENDPOINT_BANK_DOUBLE AVR32_USBB_UECFG0_EPBK_DOUBLE\r
\r
/** Mask for the bank mode selection for the \ref Endpoint_ConfigureEndpoint() macro. This indicates\r
* that the endpoint should have three banks, which requires more USB FIFO memory but results\r
* in faster transfers as one USB device (the AVR or the host) can access one bank while the other\r
* accesses the remaining banks.\r
*/\r
- #define ENDPOINT_BANK_TRIPLE AVR32_USBB_UECFG0_TRIPLE\r
+ #define ENDPOINT_BANK_TRIPLE AVR32_USBB_UECFG0_EPBK_TRIPLE\r
//@}\r
\r
/** Endpoint address for the default control endpoint, which always resides in address 0. This is\r