Seperate out XMEGA and TINY NVM routines into seperate files.

[pub/lufa.git] / Projects / AVRISP / Lib / XMEGANVM.c

diff --git a/Projects/AVRISP/Lib/XMEGANVM.c b/Projects/AVRISP/Lib/XMEGANVM.c
index adf213b..ed8719c 100644 (file)
--- a/Projects/AVRISP/Lib/XMEGANVM.c
+++ b/Projects/AVRISP/Lib/XMEGANVM.c
@@ -30,11 +30,11 @@
 \r
 /** \file\r
  *\r
 \r
 /** \file\r
  *\r

- *  Target-related functions for the target's NVM module.\r
+ *  Target-related functions for the XMEGA target's NVM module.\r

  */\r
 \r
  */\r
 \r

-#define  INCLUDE_FROM_NVMTARGET_C\r
-#include "NVMTarget.h"\r
+#define  INCLUDE_FROM_XMEGA_NVM_C\r
+#include "XMEGANVM.h"\r

 \r
 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)\r
 \r
 \r
 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)\r
 \r


@@ -42,20 +42,20 @@
  *\r
  *  \param[in] Register  NVM register whose absolute address is to be sent\r
  */\r
  *\r
  *  \param[in] Register  NVM register whose absolute address is to be sent\r
  */\r

-void NVMTarget_SendNVMRegAddress(const uint8_t Register)\r
+void XMEGANVM_SendNVMRegAddress(const uint8_t Register)\r

 {\r
        /* Determine the absolute register address from the NVM base memory address and the NVM register address */\r
        uint32_t Address = XPROG_Param_NVMBase | Register;\r
 \r
        /* Send the calculated 32-bit address to the target, LSB first */\r
 {\r
        /* Determine the absolute register address from the NVM base memory address and the NVM register address */\r
        uint32_t Address = XPROG_Param_NVMBase | Register;\r
 \r
        /* Send the calculated 32-bit address to the target, LSB first */\r

-       NVMTarget_SendAddress(Address);\r
+       XMEGANVM_SendAddress(Address);\r

 }\r
 \r
 /** Sends the given 32-bit absolute address to the target.\r
  *\r
  *  \param[in] AbsoluteAddress  Absolute address to send to the target\r
  */\r
 }\r
 \r
 /** Sends the given 32-bit absolute address to the target.\r
  *\r
  *  \param[in] AbsoluteAddress  Absolute address to send to the target\r
  */\r

-void NVMTarget_SendAddress(const uint32_t AbsoluteAddress)\r
+void XMEGANVM_SendAddress(const uint32_t AbsoluteAddress)\r

 {\r
        /* Send the given 32-bit address to the target, LSB first */\r
        PDITarget_SendByte(AbsoluteAddress &  0xFF);\r
 {\r
        /* Send the given 32-bit address to the target, LSB first */\r
        PDITarget_SendByte(AbsoluteAddress &  0xFF);\r


@@ -69,19 +69,19 @@ void NVMTarget_SendAddress(const uint32_t AbsoluteAddress)
  *\r
  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise\r
  */\r
  *\r
  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise\r
  */\r

-bool NVMTarget_WaitWhileNVMControllerBusy(void)\r
+bool XMEGANVM_WaitWhileNVMControllerBusy(void)\r

 {\r
        TCNT0 = 0;\r
        TIFR0 = (1 << OCF1A);\r
                        \r
 {\r
        TCNT0 = 0;\r
        TIFR0 = (1 << OCF1A);\r
                        \r

-       uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS;\r
+       uint8_t TimeoutMS = XMEGA_NVM_BUSY_TIMEOUT_MS;\r

        \r
        /* Poll the NVM STATUS register while the NVM controller is busy */\r
        while (TimeoutMS)\r
        {\r
                /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
                PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        \r
        /* Poll the NVM STATUS register while the NVM controller is busy */\r
        while (TimeoutMS)\r
        {\r
                /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
                PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
+               XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_STATUS);\r

                \r
                /* Check to see if the BUSY flag is still set */\r
                if (!(PDITarget_ReceiveByte() & (1 << 7)))\r
                \r
                /* Check to see if the BUSY flag is still set */\r
                if (!(PDITarget_ReceiveByte() & (1 << 7)))\r


@@ -104,20 +104,20 @@ bool NVMTarget_WaitWhileNVMControllerBusy(void)
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r

-bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)\r
+bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)\r

 {\r
        /* Wait until the NVM controller is no longer busy */\r
 {\r
        /* Wait until the NVM controller is no longer busy */\r

-       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

          return false;\r
          \r
        /* Set the NVM command to the correct CRC read command */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
          return false;\r
          \r
        /* Set the NVM command to the correct CRC read command */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r

        PDITarget_SendByte(CRCCommand);\r
 \r
        /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        PDITarget_SendByte(CRCCommand);\r
 \r
        /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);\r

        PDITarget_SendByte(1 << 0);\r
 \r
        /* Wait until the NVM bus is ready again */\r
        PDITarget_SendByte(1 << 0);\r
 \r
        /* Wait until the NVM bus is ready again */\r


@@ -125,24 +125,24 @@ bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)
          return false;\r
 \r
        /* Wait until the NVM controller is no longer busy */\r
          return false;\r
 \r
        /* Wait until the NVM controller is no longer busy */\r

-       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

          return false;\r
        \r
        *CRCDest = 0;\r
        \r
        /* Read the first generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
          return false;\r
        \r
        *CRCDest = 0;\r
        \r
        /* Read the first generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT0);\r

        *CRCDest  = PDITarget_ReceiveByte();\r
 \r
        /* Read the second generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        *CRCDest  = PDITarget_ReceiveByte();\r
 \r
        /* Read the second generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT1);\r

        *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
 \r
        /* Read the third generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
 \r
        /* Read the third generated CRC byte value */\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT2);\r

        *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
        \r
        return true;\r
        *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
        \r
        return true;\r


@@ -156,20 +156,20 @@ bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r

-bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)\r
+bool XMEGANVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)\r

 {\r
        /* Wait until the NVM controller is no longer busy */\r
 {\r
        /* Wait until the NVM controller is no longer busy */\r

-       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

          return false;\r
        \r
        /* Send the READNVM command to the NVM controller for reading of an arbitrary location */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
          return false;\r
        \r
        /* Send the READNVM command to the NVM controller for reading of an arbitrary location */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
-       PDITarget_SendByte(NVM_CMD_READNVM);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
+       PDITarget_SendByte(XMEGA_NVM_CMD_READNVM);\r

 \r
        /* Load the PDI pointer register with the start address we want to read from */\r
        PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
 \r
        /* Load the PDI pointer register with the start address we want to read from */\r
        PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r

-       NVMTarget_SendAddress(ReadAddress);\r
+       XMEGANVM_SendAddress(ReadAddress);\r

 \r
        /* Send the REPEAT command with the specified number of bytes to read */\r
        PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
 \r
        /* Send the REPEAT command with the specified number of bytes to read */\r
        PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r


@@ -191,20 +191,20 @@ bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r

-bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)\r
+bool XMEGANVM_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)\r

 {\r
        /* Wait until the NVM controller is no longer busy */\r
 {\r
        /* Wait until the NVM controller is no longer busy */\r

-       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

          return false;\r
 \r
        /* Send the memory write command to the target */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
          return false;\r
 \r
        /* Send the memory write command to the target */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r

        PDITarget_SendByte(WriteCommand);\r
        \r
        /* Send new memory byte to the memory to the target */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        PDITarget_SendByte(WriteCommand);\r
        \r
        /* Send new memory byte to the memory to the target */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendAddress(WriteAddress);\r
+       XMEGANVM_SendAddress(WriteAddress);\r

        PDITarget_SendByte(*(WriteBuffer++));\r
        \r
        return true;\r
        PDITarget_SendByte(*(WriteBuffer++));\r
        \r
        return true;\r


@@ -222,41 +222,41 @@ bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteA
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r

-bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand,\r
+bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand,\r

                                const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,\r
                                const uint8_t* WriteBuffer, const uint16_t WriteSize)\r
 {\r
        if (PageMode & XPRG_PAGEMODE_ERASE)\r
        {\r
                /* Wait until the NVM controller is no longer busy */\r
                                const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,\r
                                const uint8_t* WriteBuffer, const uint16_t WriteSize)\r
 {\r
        if (PageMode & XPRG_PAGEMODE_ERASE)\r
        {\r
                /* Wait until the NVM controller is no longer busy */\r

-               if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+               if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

                  return false;\r
 \r
                /* Send the memory buffer erase command to the target */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                  return false;\r
 \r
                /* Send the memory buffer erase command to the target */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+               XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r

                PDITarget_SendByte(EraseBuffCommand);\r
 \r
                /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                PDITarget_SendByte(EraseBuffCommand);\r
 \r
                /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
+               XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);\r

                PDITarget_SendByte(1 << 0);\r
        }\r
 \r
        if (WriteSize)\r
        {\r
                /* Wait until the NVM controller is no longer busy */\r
                PDITarget_SendByte(1 << 0);\r
        }\r
 \r
        if (WriteSize)\r
        {\r
                /* Wait until the NVM controller is no longer busy */\r

-               if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+               if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

                  return false;\r
 \r
                /* Send the memory buffer write command to the target */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                  return false;\r
 \r
                /* Send the memory buffer write command to the target */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+               XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r

                PDITarget_SendByte(WriteBuffCommand);\r
 \r
                /* Load the PDI pointer register with the start address we want to write to */\r
                PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
                PDITarget_SendByte(WriteBuffCommand);\r
 \r
                /* Load the PDI pointer register with the start address we want to write to */\r
                PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r

-               NVMTarget_SendAddress(WriteAddress);\r
+               XMEGANVM_SendAddress(WriteAddress);\r

 \r
                /* Send the REPEAT command with the specified number of bytes to write */\r
                PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
 \r
                /* Send the REPEAT command with the specified number of bytes to write */\r
                PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r


@@ -271,17 +271,17 @@ bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t Era
        if (PageMode & XPRG_PAGEMODE_WRITE)\r
        {\r
                /* Wait until the NVM controller is no longer busy */\r
        if (PageMode & XPRG_PAGEMODE_WRITE)\r
        {\r
                /* Wait until the NVM controller is no longer busy */\r

-               if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+               if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

                  return false;\r
 \r
                /* Send the memory write command to the target */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                  return false;\r
 \r
                /* Send the memory write command to the target */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+               XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r

                PDITarget_SendByte(WritePageCommand);\r
                \r
                /* Send the address of the first page location to write the memory page */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                PDITarget_SendByte(WritePageCommand);\r
                \r
                /* Send the address of the first page location to write the memory page */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendAddress(WriteAddress);\r
+               XMEGANVM_SendAddress(WriteAddress);\r

                PDITarget_SendByte(0x00);\r
        }\r
 \r
                PDITarget_SendByte(0x00);\r
        }\r
 \r


@@ -295,30 +295,30 @@ bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t Era
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r
  *\r
  *  \return Boolean true if the command sequence complete successfully\r
  */\r

-bool NVMTarget_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)\r
+bool XMEGANVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)\r

 {\r
        /* Wait until the NVM controller is no longer busy */\r
 {\r
        /* Wait until the NVM controller is no longer busy */\r

-       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMControllerBusy()))\r

          return false;\r
          \r
        /* Send the memory erase command to the target */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
          return false;\r
          \r
        /* Send the memory erase command to the target */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+       XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r

        PDITarget_SendByte(EraseCommand);\r
        \r
        /* Chip erase is handled separately, since it's procedure is different to other erase types */\r
        PDITarget_SendByte(EraseCommand);\r
        \r
        /* Chip erase is handled separately, since it's procedure is different to other erase types */\r

-       if (EraseCommand == NVM_CMD_CHIPERASE)\r
+       if (EraseCommand == XMEGA_NVM_CMD_CHIPERASE)\r

        {\r
                /* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        {\r
                /* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
+               XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);\r

                PDITarget_SendByte(1 << 0);             \r
        }\r
        else\r
        {\r
                /* Other erase modes just need us to address a byte within the target memory space */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                PDITarget_SendByte(1 << 0);             \r
        }\r
        else\r
        {\r
                /* Other erase modes just need us to address a byte within the target memory space */\r
                PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r

-               NVMTarget_SendAddress(Address); \r
+               XMEGANVM_SendAddress(Address);  \r

                PDITarget_SendByte(0x00);\r
        }\r
        \r
                PDITarget_SendByte(0x00);\r
        }\r
        \r