*\r
* Note that this design currently has several limitations:\r
* - Minimum target clock speed of 500KHz due to hardware SPI used\r
- * - No VTARGET detection and notification\r
* - No reversed/shorted target connector detection and notification\r
*\r
+ * On AVR models with an ADC converter, ACC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be\r
+ * set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models\r
+ * without an ADC converter, VTARGET will report at a fixed 5V level.\r
+ *\r
* \section SSec_Options Project Options\r
*\r
* The following defines can be found in this demo, which can control the demo behaviour when defined, or changed in value.\r
* <td>Makefile CDEFS</td>\r
* <td>Mask for the programmer's target RESET line on the chosen port.</td>\r
* </tr>\r
+ * <tr>\r
+ * <td>VTARGET_ADC_CHANNEL</td>\r
+ * <td>Makefile CDEFS</td>\r
+ * <td>ADC channel number (on supported AVRs) to use for VTARGET level detection.</td> \r
+ * </tr>\r
* </table>\r
*/\r