Removed John Steggall's software UART code from the XPLAIN Bridge project due to...

[pub/lufa.git] / Projects / AVRISP / AVRISP.txt

diff --git a/Projects/AVRISP/AVRISP.txt b/Projects/AVRISP/AVRISP.txt
index 0ccf72a..670c168 100644 (file)
--- a/Projects/AVRISP/AVRISP.txt
+++ b/Projects/AVRISP/AVRISP.txt
@@ -108,8 +108,43 @@
  *  Connections to the device are simple for SPI programming:\r
  *\r
  *  <table>\r
- *   <td><b>PDI Programming is not yet fully implemented.</b></td>\r
+ *   <tr>\r
+ *    <td><b>Programmer Pin:</b></td>\r
+ *    <td><b>Target Device Pin:</b></td>\r
+ *    <td><b>ISP 6 Pin Layout:</b></td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>MISO</td>\r
+ *    <td>DATA</td>\r
+ *    <td>1</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>ADCx <b><sup>1</sup></b></td>\r
+ *    <td>VTARGET</td>\r
+ *    <td>2</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>N/A</td>\r
+ *    <td>N/A</td>\r
+ *    <td>3</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>N/A</td>\r
+ *    <td>N/A</td>\r
+ *    <td>4</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>PORTx.y <b><sup>2</sup></b></td>\r
+ *    <td>CLOCK</td>\r
+ *    <td>5</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>GND</td>\r
+ *    <td>GND</td>\r
+ *    <td>6</td>\r
+ *   </tr>\r
  *  </table>\r
+ *\r
  *  \section SSec_Options Project Options\r
  *\r
  *  The following defines can be found in this demo, which can control the demo behaviour when defined, or changed in value.\r
@@ -135,7 +170,7 @@
  *    <td>Makefile CDEFS</td>\r
  *    <td>Mask for the programmer's target RESET line on the chosen port. <b>Must not be the AVR's /SS pin</b>, as the\r
  *        target pins are tri-stated when not in use, and low signals on the /SS pin will force SPI slave mode when the\r
- *        pin is configured as an input.</td>\r
+ *        pin is configured as an input. When in PDI programming mode, this is the target clock pin.</td>\r
  *   </tr>\r
  *   <tr>\r
  *    <td>VTARGET_ADC_CHANNEL</td>\r