From: Dean Camera <dean@fourwalledcubicle.com>
Date: Wed, 12 Oct 2011 02:27:22 +0000 (+0000)
Subject: When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL... 
X-Git-Tag: LUFA-120219~60
X-Git-Url: http://git.linex4red.de/pub/USBasp.git/commitdiff_plain/c15eaa5dae5b8913d9401f0ad508494a6b66744a?hp=c15eaa5dae5b8913d9401f0ad508494a6b66744a

When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale).
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