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(parent: 1a4a262) | patch
When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL...
authorDean Camera <dean@fourwalledcubicle.com>
Wed, 12 Oct 2011 02:27:22 +0000 (02:27 +0000)
committerDean Camera <dean@fourwalledcubicle.com>
Wed, 12 Oct 2011 02:27:22 +0000 (02:27 +0000)
commitc15eaa5dae5b8913d9401f0ad508494a6b66744a
tree63bdae6e1f3735ee05d662a6fb2efd51b59d5561tree | snapshot (tar.gz tar.bz2 zip)
parent1a4a26271e32fba6e2430b7869ec4a8b4242e6e2commit | diff
When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale).
LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c diff | blob | blame | history
LUFA/ManPages/ChangeLog.txt diff | blob | blame | history
USB isp AVR programmer