X-Git-Url: http://git.linex4red.de/pub/USBasp.git/blobdiff_plain/ea922c98d187eb74c31535afa3334ead5bd50526..a9abe1fdea5ccf67aaccab6fdde300d6fcf2d15a:/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c index 70e49f7c6..ede236280 100644 --- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c +++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c @@ -1,13 +1,13 @@ /* LUFA Library - Copyright (C) Dean Camera, 2011. + Copyright (C) Dean Camera, 2012. dean [at] fourwalledcubicle [dot] com www.lufa-lib.org */ /* - Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com) + Copyright 2012 Dean Camera (dean [at] fourwalledcubicle [dot] com) Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted @@ -46,22 +46,18 @@ void XPROGTarget_EnableTargetPDI(void) { IsSending = false; - #if (ARCH == ARCH_AVR8) - /* Set Tx and XCK as outputs, Rx as input */ - DDRD |= (1 << 5) | (1 << 3); - DDRD &= ~(1 << 2); + /* Set Tx and XCK as outputs, Rx as input */ + DDRD |= (1 << 5) | (1 << 3); + DDRD &= ~(1 << 2); - /* Set DATA line high for at least 90ns to disable /RESET functionality */ - PORTD |= (1 << 3); - Delay_MS(1); + /* Set DATA line high for at least 90ns to disable /RESET functionality */ + PORTD |= (1 << 3); + _delay_us(1); - /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */ - UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1); - UCSR1B = (1 << TXEN1); - UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1); - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */ + UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1); + UCSR1B = (1 << TXEN1); + UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1); /* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */ XPROGTarget_SendIdle(); @@ -73,23 +69,19 @@ void XPROGTarget_EnableTargetTPI(void) { IsSending = false; - #if (ARCH == ARCH_AVR8) - /* Set /RESET line low for at least 400ns to enable TPI functionality */ - AUX_LINE_DDR |= AUX_LINE_MASK; - AUX_LINE_PORT &= ~AUX_LINE_MASK; - Delay_MS(1); + /* Set /RESET line low for at least 400ns to enable TPI functionality */ + AUX_LINE_DDR |= AUX_LINE_MASK; + AUX_LINE_PORT &= ~AUX_LINE_MASK; + _delay_us(1); - /* Set Tx and XCK as outputs, Rx as input */ - DDRD |= (1 << 5) | (1 << 3); - DDRD &= ~(1 << 2); + /* Set Tx and XCK as outputs, Rx as input */ + DDRD |= (1 << 5) | (1 << 3); + DDRD &= ~(1 << 2); - /* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */ - UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1); - UCSR1B = (1 << TXEN1); - UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1); - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + /* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */ + UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1); + UCSR1B = (1 << TXEN1); + UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1); /* Send two IDLEs of 12 bits each to enable TPI interface (need at least 16 idle bits) */ XPROGTarget_SendIdle(); @@ -100,44 +92,38 @@ void XPROGTarget_EnableTargetTPI(void) void XPROGTarget_DisableTargetPDI(void) { /* Switch to Rx mode to ensure that all pending transmissions are complete */ - XPROGTarget_SetRxMode(); - - #if (ARCH == ARCH_AVR8) - /* Turn off receiver and transmitter of the USART, clear settings */ - UCSR1A = ((1 << TXC1) | (1 << RXC1)); - UCSR1B = 0; - UCSR1C = 0; - - /* Tristate all pins */ - DDRD &= ~((1 << 5) | (1 << 3)); - PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2)); - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + if (IsSending) + XPROGTarget_SetRxMode(); + + /* Turn off receiver and transmitter of the USART, clear settings */ + UCSR1A = ((1 << TXC1) | (1 << RXC1)); + UCSR1B = 0; + UCSR1C = 0; + + /* Tristate all pins */ + DDRD &= ~((1 << 5) | (1 << 3)); + PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2)); } /** Disables the target's TPI interface, exits programming mode and starts the target's application. */ void XPROGTarget_DisableTargetTPI(void) { /* Switch to Rx mode to ensure that all pending transmissions are complete */ - XPROGTarget_SetRxMode(); - - #if (ARCH == ARCH_AVR8) - /* Turn off receiver and transmitter of the USART, clear settings */ - UCSR1A |= (1 << TXC1) | (1 << RXC1); - UCSR1B = 0; - UCSR1C = 0; - - /* Set all USART lines as inputs, tristate */ - DDRD &= ~((1 << 5) | (1 << 3)); - PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2)); - - /* Tristate target /RESET line */ - AUX_LINE_DDR &= ~AUX_LINE_MASK; - AUX_LINE_PORT &= ~AUX_LINE_MASK; - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + if (IsSending) + XPROGTarget_SetRxMode(); + + /* Turn off receiver and transmitter of the USART, clear settings */ + UCSR1A |= (1 << TXC1) | (1 << RXC1); + UCSR1B = 0; + UCSR1C = 0; + + /* Set all USART lines as inputs, tristate */ + DDRD &= ~((1 << 5) | (1 << 3)); + PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2)); + + /* Tristate target /RESET line */ + AUX_LINE_DDR &= ~AUX_LINE_MASK; + AUX_LINE_PORT &= ~AUX_LINE_MASK; } /** Sends a byte via the USART. @@ -150,17 +136,13 @@ void XPROGTarget_SendByte(const uint8_t Byte) if (!(IsSending)) XPROGTarget_SetTxMode(); - #if (ARCH == ARCH_AVR8) - /* Wait until there is space in the hardware Tx buffer before writing */ - while (!(UCSR1A & (1 << UDRE1))); - UCSR1A |= (1 << TXC1); - UDR1 = Byte; - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + /* Wait until there is space in the hardware Tx buffer before writing */ + while (!(UCSR1A & (1 << UDRE1))); + UCSR1A |= (1 << TXC1); + UDR1 = Byte; } -/** Receives a byte via the software USART, blocking until data is received. +/** Receives a byte via the hardware USART, blocking until data is received or timeout expired. * * \return Received byte from the USART */ @@ -170,15 +152,13 @@ uint8_t XPROGTarget_ReceiveByte(void) if (IsSending) XPROGTarget_SetRxMode(); - #if (ARCH == ARCH_AVR8) - /* Wait until a byte has been received before reading */ - while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired)); + /* Wait until a byte has been received before reading */ + while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired)); + + /* Byte of data received - reset the timeout */ + wdt_reset(); - return UDR1; - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - return 0; - #endif + return UDR1; } /** Sends an IDLE via the USART to the attached target, consisting of a full frame of idle bits. */ @@ -187,53 +167,43 @@ void XPROGTarget_SendIdle(void) /* Switch to Tx mode if currently in Rx mode */ if (!(IsSending)) XPROGTarget_SetTxMode(); - - #if (ARCH == ARCH_AVR8) - /* Need to do nothing for a full frame to send an IDLE */ - for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++) - { - /* Wait for a full cycle of the clock */ - while (PIND & (1 << 5)); - while (!(PIND & (1 << 5))); - } - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif -} -static void XPROGTarget_SetTxMode(void) -{ - #if (ARCH == ARCH_AVR8) + /* Need to do nothing for a full frame to send an IDLE */ + for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++) + { /* Wait for a full cycle of the clock */ while (PIND & (1 << 5)); while (!(PIND & (1 << 5))); + while (PIND & (1 << 5)); + } +} - PORTD |= (1 << 3); - DDRD |= (1 << 3); +static void XPROGTarget_SetTxMode(void) +{ + /* Wait for a full cycle of the clock */ + while (PIND & (1 << 5)); + while (!(PIND & (1 << 5))); + while (PIND & (1 << 5)); + + PORTD |= (1 << 3); + DDRD |= (1 << 3); - UCSR1B &= ~(1 << RXEN1); - UCSR1B |= (1 << TXEN1); - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + UCSR1B &= ~(1 << RXEN1); + UCSR1B |= (1 << TXEN1); IsSending = true; } static void XPROGTarget_SetRxMode(void) { - #if (ARCH == ARCH_AVR8) - while (!(UCSR1A & (1 << TXC1))); - UCSR1A |= (1 << TXC1); - - UCSR1B &= ~(1 << TXEN1); - UCSR1B |= (1 << RXEN1); - - DDRD &= ~(1 << 3); - PORTD &= ~(1 << 3); - #elif (ARCH == ARCH_UC3) - // TODO: FIXME - #endif + while (!(UCSR1A & (1 << TXC1))); + UCSR1A |= (1 << TXC1); + + UCSR1B &= ~(1 << TXEN1); + UCSR1B |= (1 << RXEN1); + + DDRD &= ~(1 << 3); + PORTD &= ~(1 << 3); IsSending = false; }