X-Git-Url: http://git.linex4red.de/pub/USBasp.git/blobdiff_plain/c73997429271e8566080ac8fdf21e5944c3b4c8e..7cac5e22d7fae140b3ae4167a706d0dc07b9cf3b:/LUFA/Platform/XMEGA/ClockManagement.h diff --git a/LUFA/Platform/XMEGA/ClockManagement.h b/LUFA/Platform/XMEGA/ClockManagement.h index 07ba0e73c..db2bb64a4 100644 --- a/LUFA/Platform/XMEGA/ClockManagement.h +++ b/LUFA/Platform/XMEGA/ClockManagement.h @@ -1,13 +1,13 @@ /* LUFA Library - Copyright (C) Dean Camera, 2011. + Copyright (C) Dean Camera, 2012. dean [at] fourwalledcubicle [dot] com www.lufa-lib.org */ /* - Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com) + Copyright 2012 Dean Camera (dean [at] fourwalledcubicle [dot] com) Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted @@ -35,8 +35,8 @@ * of the various clocks within the device to clock the various peripherals. */ -/** \ingroup Group_PlatformDrivers - * \defgroup Group_PlatformDrivers_XMEGAClocks AVR USB XMEGA Clock Management Driver - LUFA/Platform/XMEGA/ClockManagement.h +/** \ingroup Group_PlatformDrivers_XMEGA + * \defgroup Group_PlatformDrivers_XMEGAClocks Clock Management Driver - LUFA/Platform/XMEGA/ClockManagement.h * \brief Module Clock Driver for the AVR USB XMEGA microcontrollers. * * \section Sec_Dependencies Module Source Dependencies @@ -50,13 +50,13 @@ * Usage Example: * \code * #include - * + * * void main(void) * { * // Start the PLL to multiply the 2MHz RC oscillator to 32MHz and switch the CPU core to run from it * XMEGACLK_StartPLL(CLOCK_SRC_INT_RC2MHZ, 2000000, 32000000); * XMEGACLK_SetCPUClockSource(CLOCK_SRC_PLL, F_CPU); - * + * * // Start the 32MHz internal RC oscillator and start the DFLL to increase it to 48MHz using the USB SOF as a reference * XMEGACLK_StartInternalOscillator(CLOCK_SRC_INT_RC32MHZ); * XMEGACLK_StartDFLL(CLOCK_SRC_INT_RC32MHZ, DFLL_REF_INT_USBSOF, 48000000); @@ -85,7 +85,7 @@ EXOSC_FREQ_2MHZ_MAX = OSC_FRQRANGE_04TO2_gc, /**< External crystal oscillator equal to or slower than 2MHz. */ EXOSC_FREQ_9MHZ_MAX = OSC_FRQRANGE_2TO9_gc, /**< External crystal oscillator equal to or slower than 9MHz. */ EXOSC_FREQ_12MHZ_MAX = OSC_FRQRANGE_9TO12_gc, /**< External crystal oscillator equal to or slower than 12MHz. */ - EXOSC_FREQ_16MHZ_MAX = OSC_FRQRANGE_12TO16_gc, /**< External crystal oscillator equal to or slower than 16MHz. */ + EXOSC_FREQ_16MHZ_MAX = OSC_FRQRANGE_12TO16_gc, /**< External crystal oscillator equal to or slower than 16MHz. */ }; /** Enum for the possible external oscillator statup times. */ @@ -97,7 +97,7 @@ EXOSC_START_1KCLK = OSC_XOSCSEL_XTAL_1KCLK_gc, /**< Wait 1K clock cycles before startup. */ EXOSC_START_16KCLK = OSC_XOSCSEL_XTAL_16KCLK_gc, /**< Wait 16K clock cycles before startup. */ }; - + /** Enum for the possible module clock sources. */ enum XMEGA_System_ClockSource_t { @@ -132,8 +132,8 @@ { OSC.XOSCCTRL = (FreqRange | ((Startup == EXOSC_START_32KCLK) ? OSC_X32KLPM_bm : 0) | Startup); OSC.CTRL |= OSC_XOSCEN_bm; - - while (!(OSC.STATUS & OSC_XOSCRDY_bm)); + + while (!(OSC.STATUS & OSC_XOSCRDY_bm)); return true; } @@ -162,14 +162,14 @@ return true; case CLOCK_SRC_INT_RC32MHZ: OSC.CTRL |= OSC_RC32MEN_bm; - while (!(OSC.STATUS & OSC_RC32MRDY_bm)); + while (!(OSC.STATUS & OSC_RC32MRDY_bm)); return true; case CLOCK_SRC_INT_RC32KHZ: OSC.CTRL |= OSC_RC32KEN_bm; - while (!(OSC.STATUS & OSC_RC32KRDY_bm)); + while (!(OSC.STATUS & OSC_RC32KRDY_bm)); return true; } - + return false; } @@ -178,7 +178,7 @@ * \param[in] Source Internal oscillator to stop, a value from \ref XMEGA_System_ClockSource_t. * * \return Boolean \c true if the internal oscillator was successfully stopped, \c false if invalid parameters specified. - */ + */ static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE; static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source) { @@ -194,13 +194,13 @@ OSC.CTRL &= ~OSC_RC32KEN_bm; return true; } - + return false; } /** Starts the PLL of the XMEGA microcontroller, with the given options. This routine blocks until the PLL is ready for use. * - * \note The output frequency must be equal to or greater than the source frequency. + * \attention The output frequency must be equal to or greater than the source frequency. * * \param[in] Source Clock source for the PLL, a value from \ref XMEGA_System_ClockSource_t. * \param[in] SourceFreq Frequency of the PLL's clock source, in Hz. @@ -216,10 +216,10 @@ const uint32_t Frequency) { uint8_t MulFactor = (Frequency / SourceFreq); - + if (SourceFreq > Frequency) - return false; - + return false; + switch (Source) { case CLOCK_SRC_INT_RC2MHZ: @@ -236,7 +236,7 @@ } OSC.CTRL |= OSC_PLLEN_bm; - + while (!(OSC.STATUS & OSC_PLLRDY_bm)); return true; } @@ -247,7 +247,7 @@ { OSC.CTRL &= ~OSC_PLLEN_bm; } - + /** Starts the DFLL of the XMEGA microcontroller, with the given options. * * \param[in] Source RC Clock source for the DFLL, a value from \ref XMEGA_System_ClockSource_t. @@ -263,37 +263,35 @@ const uint8_t Reference, const uint32_t Frequency) { - uint16_t DFLLCompare = (Frequency / 1024); - uint16_t DFFLCal = 0; + uint16_t DFLLCompare = (Frequency / 1000); - if (Reference == DFLL_REF_INT_USBSOF) - { - NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc; - DFFLCal = ((0x00 << 8) | pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC))); - } - switch (Source) { case CLOCK_SRC_INT_RC2MHZ: OSC.DFLLCTRL |= (Reference << OSC_RC2MCREF_bp); DFLLRC2M.COMP1 = (DFLLCompare & 0xFF); DFLLRC2M.COMP2 = (DFLLCompare >> 8); - DFLLRC2M.CALA = (DFFLCal & 0xFF); - DFLLRC2M.CALB = (DFFLCal >> 8); DFLLRC2M.CTRL = DFLL_ENABLE_bm; break; case CLOCK_SRC_INT_RC32MHZ: OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp); DFLLRC32M.COMP1 = (DFLLCompare & 0xFF); DFLLRC32M.COMP2 = (DFLLCompare >> 8); - DFLLRC32M.CALA = (DFFLCal & 0xFF); - DFLLRC32M.CALB = (DFFLCal >> 8); + + if (Reference == DFLL_REF_INT_USBSOF) + { + NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc; + DFLLRC32M.CALA = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSCA)); + DFLLRC32M.CALB = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC)); + NVM.CMD = 0; + } + DFLLRC32M.CTRL = DFLL_ENABLE_bm; break; default: return false; } - + return true; } @@ -317,7 +315,7 @@ default: return false; } - + return true; } @@ -325,17 +323,14 @@ * and ready for use before this function is called. * * \param[in] Source Clock source for the CPU core, a value from \ref XMEGA_System_ClockSource_t. - * \param[in] SourceFreq Frequency of the CPU core's clock source, in Hz. * * \return Boolean \c true if the CPU core clock was sucessfully altered, \c false if invalid parameters specified. */ - static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source, - const uint32_t SourceFreq) ATTR_ALWAYS_INLINE; - static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source, - const uint32_t SourceFreq) + static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source) ATTR_ALWAYS_INLINE; + static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source) { uint8_t ClockSourceMask = 0; - + switch (Source) { case CLOCK_SRC_INT_RC2MHZ: @@ -356,16 +351,16 @@ default: return false; } - + uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask(); GlobalInterruptDisable(); CCP = CCP_IOREG_gc; - CLK.CTRL = ClockSourceMask; - + CLK_CTRL = ClockSourceMask; + SetGlobalInterruptMask(CurrentGlobalInt); - - Delay_MS(1); + + Delay_MS(1); return (CLK.CTRL == ClockSourceMask); } @@ -377,3 +372,4 @@ #endif /** @} */ +