X-Git-Url: http://git.linex4red.de/pub/USBasp.git/blobdiff_plain/8ea051de637f09f0fd2895f5a18ee9f337b9b1f1..24f730fce3f2022762011d795c3feada5ef874b3:/Projects/AVRISP/Lib/NVMTarget.c?ds=sidebyside diff --git a/Projects/AVRISP/Lib/NVMTarget.c b/Projects/AVRISP/Lib/NVMTarget.c index d84ae6b85..adf213bb4 100644 --- a/Projects/AVRISP/Lib/NVMTarget.c +++ b/Projects/AVRISP/Lib/NVMTarget.c @@ -42,23 +42,20 @@ * * \param[in] Register NVM register whose absolute address is to be sent */ -void NVMTarget_SendNVMRegAddress(uint8_t Register) +void NVMTarget_SendNVMRegAddress(const uint8_t Register) { /* Determine the absolute register address from the NVM base memory address and the NVM register address */ uint32_t Address = XPROG_Param_NVMBase | Register; /* Send the calculated 32-bit address to the target, LSB first */ - PDITarget_SendByte(Address & 0xFF); - PDITarget_SendByte(Address >> 8); - PDITarget_SendByte(Address >> 16); - PDITarget_SendByte(Address >> 24); + NVMTarget_SendAddress(Address); } /** Sends the given 32-bit absolute address to the target. * * \param[in] AbsoluteAddress Absolute address to send to the target */ -void NVMTarget_SendAddress(uint32_t AbsoluteAddress) +void NVMTarget_SendAddress(const uint32_t AbsoluteAddress) { /* Send the given 32-bit address to the target, LSB first */ PDITarget_SendByte(AbsoluteAddress & 0xFF); @@ -75,9 +72,12 @@ void NVMTarget_SendAddress(uint32_t AbsoluteAddress) bool NVMTarget_WaitWhileNVMControllerBusy(void) { TCNT0 = 0; - + TIFR0 = (1 << OCF1A); + + uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS; + /* Poll the NVM STATUS register while the NVM controller is busy */ - while (TCNT0 < NVM_BUSY_TIMEOUT_MS) + while (TimeoutMS) { /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */ PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2)); @@ -86,6 +86,12 @@ bool NVMTarget_WaitWhileNVMControllerBusy(void) /* Check to see if the BUSY flag is still set */ if (!(PDITarget_ReceiveByte() & (1 << 7))) return true; + + if (TIFR0 & (1 << OCF1A)) + { + TIFR0 = (1 << OCF1A); + TimeoutMS--; + } } return false; @@ -96,9 +102,9 @@ bool NVMTarget_WaitWhileNVMControllerBusy(void) * \param[in] CRCCommand NVM CRC command to issue to the target * \param[out] CRCDest CRC Destination when read from the target * - * \return Boolean true if the command sequence complete sucessfully + * \return Boolean true if the command sequence complete successfully */ -bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest) +bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest) { /* Wait until the NVM controller is no longer busy */ if (!(NVMTarget_WaitWhileNVMControllerBusy())) @@ -148,70 +154,137 @@ bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest) * \param[out] ReadBuffer Buffer to store read data into * \param[in] ReadSize Number of bytes to read * - * \return Boolean true if the command sequence complete sucessfully + * \return Boolean true if the command sequence complete successfully */ -bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize) +bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize) { /* Wait until the NVM controller is no longer busy */ if (!(NVMTarget_WaitWhileNVMControllerBusy())) return false; - /* Send the READNVM command to the NVM controller for reading of an aribtrary location */ + /* Send the READNVM command to the NVM controller for reading of an arbitrary location */ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); NVMTarget_SendNVMRegAddress(NVM_REG_CMD); PDITarget_SendByte(NVM_CMD_READNVM); - /* Send the address of the first location to read from - this also primes the internal address - * counters so that we can use the REPEAT command later to save on overhead for multiple bytes */ - PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2)); + /* Load the PDI pointer register with the start address we want to read from */ + PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES); NVMTarget_SendAddress(ReadAddress); - *ReadBuffer = PDITarget_ReceiveByte(); - /* Check to see if we are reading more than a single byte */ - if (ReadSize > 1) - { - /* Send the REPEAT command with the specified number of bytes remaining to read */ - PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES); - PDITarget_SendByte(ReadSize & 0xFF); - PDITarget_SendByte(ReadSize >> 8); + /* Send the REPEAT command with the specified number of bytes to read */ + PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE); + PDITarget_SendByte(ReadSize - 1); - /* Send a LD command with indirect access and postincrement to read out the remaining bytes */ - PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE); - for (uint16_t i = 0; i < ReadSize; i++) - *(ReadBuffer++) = PDITarget_ReceiveByte(); - } + /* Send a LD command with indirect access and postincrement to read out the bytes */ + PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE); + for (uint16_t i = 0; i < ReadSize; i++) + *(ReadBuffer++) = PDITarget_ReceiveByte(); return true; } /** Writes byte addressed memory to the target's memory spaces. * - * \param[in] WriteCommand Command to send to the device to write each memory page - * \param[in] WriteAddress Start address to write to within the target's address space + * \param[in] WriteCommand Command to send to the device to write each memory byte + * \param[in] WriteAddress Start address to write to within the target's address space + * \param[in] WriteBuffer Buffer to source data from + * + * \return Boolean true if the command sequence complete successfully + */ +bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer) +{ + /* Wait until the NVM controller is no longer busy */ + if (!(NVMTarget_WaitWhileNVMControllerBusy())) + return false; + + /* Send the memory write command to the target */ + PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); + NVMTarget_SendNVMRegAddress(NVM_REG_CMD); + PDITarget_SendByte(WriteCommand); + + /* Send new memory byte to the memory to the target */ + PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); + NVMTarget_SendAddress(WriteAddress); + PDITarget_SendByte(*(WriteBuffer++)); + + return true; +} + +/** Writes page addressed memory to the target's memory spaces. + * + * \param[in] WriteBuffCommand Command to send to the device to write a byte to the memory page buffer + * \param[in] EraseBuffCommand Command to send to the device to erase the memory page buffer + * \param[in] WritePageCommand Command to send to the device to write the page buffer to the destination memory + * \param[in] PageMode Bitfield indicating what operations need to be executed on the specified page + * \param[in] WriteAddress Start address to write the page data to within the target's address space * \param[in] WriteBuffer Buffer to source data from * \param[in] WriteSize Number of bytes to write * - * \return Boolean true if the command sequence complete sucessfully + * \return Boolean true if the command sequence complete successfully */ -bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize) +bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand, + const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress, + const uint8_t* WriteBuffer, const uint16_t WriteSize) { - for (uint8_t i = 0; i < WriteSize; i++) + if (PageMode & XPRG_PAGEMODE_ERASE) { /* Wait until the NVM controller is no longer busy */ if (!(NVMTarget_WaitWhileNVMControllerBusy())) return false; - /* Send the memory write command to the target */ + /* Send the memory buffer erase command to the target */ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); NVMTarget_SendNVMRegAddress(NVM_REG_CMD); - PDITarget_SendByte(WriteCommand); - - /* Send each new memory byte to the memory to the target */ + PDITarget_SendByte(EraseBuffCommand); + + /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); - NVMTarget_SendAddress(WriteAddress++); - PDITarget_SendByte(*(WriteBuffer++)); + NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA); + PDITarget_SendByte(1 << 0); + } + + if (WriteSize) + { + /* Wait until the NVM controller is no longer busy */ + if (!(NVMTarget_WaitWhileNVMControllerBusy())) + return false; + + /* Send the memory buffer write command to the target */ + PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); + NVMTarget_SendNVMRegAddress(NVM_REG_CMD); + PDITarget_SendByte(WriteBuffCommand); + + /* Load the PDI pointer register with the start address we want to write to */ + PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES); + NVMTarget_SendAddress(WriteAddress); + + /* Send the REPEAT command with the specified number of bytes to write */ + PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE); + PDITarget_SendByte(WriteSize - 1); + + /* Send a ST command with indirect access and postincrement to write the bytes */ + PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE); + for (uint16_t i = 0; i < WriteSize; i++) + PDITarget_SendByte(*(WriteBuffer++)); } + if (PageMode & XPRG_PAGEMODE_WRITE) + { + /* Wait until the NVM controller is no longer busy */ + if (!(NVMTarget_WaitWhileNVMControllerBusy())) + return false; + + /* Send the memory write command to the target */ + PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); + NVMTarget_SendNVMRegAddress(NVM_REG_CMD); + PDITarget_SendByte(WritePageCommand); + + /* Send the address of the first page location to write the memory page */ + PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2)); + NVMTarget_SendAddress(WriteAddress); + PDITarget_SendByte(0x00); + } + return true; } @@ -220,9 +293,9 @@ bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint * \param[in] EraseCommand NVM erase command to send to the device * \param[in] Address Address inside the memory space to erase * - * \return Boolean true if the command sequence complete sucessfully + * \return Boolean true if the command sequence complete successfully */ -bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address) +bool NVMTarget_EraseMemory(const uint8_t EraseCommand, const uint32_t Address) { /* Wait until the NVM controller is no longer busy */ if (!(NVMTarget_WaitWhileNVMControllerBusy())) @@ -233,7 +306,7 @@ bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address) NVMTarget_SendNVMRegAddress(NVM_REG_CMD); PDITarget_SendByte(EraseCommand); - /* Chip erase is handled seperately, since it's procedure is different to other erase types */ + /* Chip erase is handled separately, since it's procedure is different to other erase types */ if (EraseCommand == NVM_CMD_CHIPERASE) { /* Set CMDEX bit in NVM CTRLA register to start the chip erase */