X-Git-Url: http://git.linex4red.de/pub/USBasp.git/blobdiff_plain/7e5966c1a88bf670c2f4962e8a52fcfc3528e82a..66482341573c035e4c90cee32b89fb7f59068e40:/Projects/AVRISP/Lib/PDIProtocol.c?ds=inline

diff --git a/Projects/AVRISP/Lib/PDIProtocol.c b/Projects/AVRISP/Lib/PDIProtocol.c
index 28bd54071..ecd2fe9c3 100644
--- a/Projects/AVRISP/Lib/PDIProtocol.c
+++ b/Projects/AVRISP/Lib/PDIProtocol.c
@@ -106,28 +106,20 @@ static void PDIProtocol_EnterXPROGMode(void)
 	PDITarget_EnableTargetPDI();
 	
 	/* Store the RESET key into the RESET PDI register to keep the XMEGA in reset */
-	PDITarget_SendByte(PDI_CMD_STCS | PD_RESET_REG);	
+	PDITarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG);	
 	PDITarget_SendByte(PDI_RESET_KEY);
 
 	/* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */
 	PDITarget_SendByte(PDI_CMD_KEY);	
-	for (uint8_t i = 0; i < sizeof(PDI_NVMENABLE_KEY); i++)
-	  PDITarget_SendByte(PDI_NVMENABLE_KEY[i]);
+	for (uint8_t i = sizeof(PDI_NVMENABLE_KEY); i > 0; i--)
+	  PDITarget_SendByte(PDI_NVMENABLE_KEY[i - 1]);
 
-	/* Poll the STATUS register to check to see if NVM access has been enabled */
-	uint8_t NVMAttemptsRemaining = 200;
-	while (NVMAttemptsRemaining--)
-	{
-		_delay_ms(1);
-		PDITarget_SendByte(PDI_CMD_LDCS | PD_STATUS_REG);
-
-		if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
-		  break;
-	}
+	/* Wait until the NVM bus becomes active */
+	bool NVMBusEnabled = PDITarget_WaitWhileNVMBusBusy();
 	
 	Endpoint_Write_Byte(CMD_XPROG);
 	Endpoint_Write_Byte(XPRG_CMD_ENTER_PROGMODE);
-	Endpoint_Write_Byte(NVMAttemptsRemaining ? XPRG_ERR_OK : XPRG_ERR_FAILED);
+	Endpoint_Write_Byte(NVMBusEnabled ? XPRG_ERR_OK : XPRG_ERR_FAILED);
 	Endpoint_ClearIN();
 }
 
@@ -140,7 +132,7 @@ static void PDIProtocol_LeaveXPROGMode(void)
 	Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
 	
 	/* Clear the RESET key into the RESET PDI register to allow the XMEGA to run */
-	PDITarget_SendByte(PDI_CMD_STCS | PD_RESET_REG);	
+	PDITarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG);	
 	PDITarget_SendByte(0x00);
 
 	PDITarget_DisableTargetPDI();
@@ -226,7 +218,14 @@ static void PDIProtocol_ReadMemory(void)
 	Endpoint_ClearOUT();
 	Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
 	
-	// TODO: Send read command here via PDI protocol
+	if (ReadMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_USERSIG)
+	{
+		PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_1BYTE << 2));
+		PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_CMD);
+		PDITarget_SendByte(NVM_CMD_READUSERSIG);
+
+		
+	}
 	
 	Endpoint_Write_Byte(CMD_XPROG);
 	Endpoint_Write_Byte(XPRG_CMD_READ_MEM);
@@ -241,15 +240,46 @@ static void PDIProtocol_ReadMemory(void)
 static void PDIProtocol_ReadCRC(void)
 {
 	uint8_t ReturnStatus = XPRG_ERR_OK;
-
-	uint8_t CRCType = Endpoint_Read_Byte();
 	
+	struct
+	{
+		uint8_t CRCType;
+	} ReadCRC_XPROG_Params;
+	
+	Endpoint_Read_Stream_LE(&ReadCRC_XPROG_Params, sizeof(ReadCRC_XPROG_Params));
 	Endpoint_ClearOUT();
 	Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
 	
 	uint32_t MemoryCRC = 0;
+	uint8_t  CRCReadCommand;
+
+	if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_APP)
+	  CRCReadCommand = NVM_CMD_APPCRC;
+	else if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_BOOT)
+	  CRCReadCommand = NVM_CMD_BOOTCRC;
+	else
+	  CRCReadCommand = NVM_CMD_FLASHCRC;
+	
+	/* Set the NVM command to the correct CRC read command */
+	PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_1BYTE << 2));
+	PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_CMD);
+	PDITarget_SendByte(CRCReadCommand);
+
+	/* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
+	PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_1BYTE << 2));
+	PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_CTRLA);
+	PDITarget_SendByte(1 << 0);
+
+	/* Wait until the NVM bus and controller is no longer busy */
+	PDITarget_WaitWhileNVMBusBusy();
+	PDITarget_WaitWhileNVMControllerBusy();
 	
-	// TODO: Read device CRC for desired memory via PDI protocol
+	/* Read the three byte generated CRC value */
+	PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_3BYTES << 2));
+	PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_DAT0);
+	MemoryCRC  = PDITarget_ReceiveByte();
+	MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);
+	MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 	
 	Endpoint_Write_Byte(CMD_XPROG);
 	Endpoint_Write_Byte(XPRG_CMD_CRC);