X-Git-Url: http://git.linex4red.de/pub/USBasp.git/blobdiff_plain/7e5966c1a88bf670c2f4962e8a52fcfc3528e82a..32b7762325829c6e7a4168bb7db5084a34673f20:/Projects/AVRISP/Lib/PDITarget.c

diff --git a/Projects/AVRISP/Lib/PDITarget.c b/Projects/AVRISP/Lib/PDITarget.c
index d012a1beb..7fa48e6aa 100644
--- a/Projects/AVRISP/Lib/PDITarget.c
+++ b/Projects/AVRISP/Lib/PDITarget.c
@@ -38,66 +38,103 @@
 #define  INCLUDE_FROM_PDITARGET_C
 #include "PDITarget.h"
 
-#if !defined(PDI_VIA_HARDWARE_USART)
 volatile bool     IsSending;
-volatile uint16_t DataBits;
-volatile uint8_t  BitCount;
+
+#if !defined(PDI_VIA_HARDWARE_USART)
+volatile uint16_t SoftUSART_Data;
+volatile uint8_t  SoftUSART_BitCount;
 
 ISR(TIMER0_COMPA_vect, ISR_BLOCK)
 {
-	BITBANG_PDICLOCK_PORT ^= BITBANG_PDICLOCK_MASK;
+	/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
+	BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;
 
 	/* If not sending or receiving, just exit */
-	if (!(BitCount))
+	if (!(SoftUSART_BitCount))
 	  return;
-	
+
 	/* Check to see if the current clock state is on the rising or falling edge */
 	bool IsRisingEdge = (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK);
 
 	if (IsSending && !IsRisingEdge)
 	{
-		if (DataBits & 0x01)
-		  BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
+		if (SoftUSART_Data & 0x01)
+		  BITBANG_PDIDATA_PORT |=  BITBANG_PDIDATA_MASK;
 		else
-		  BITBANG_PDIDATA_PORT |=  BITBANG_PDIDATA_MASK;		  
+		  BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;		  
 
-		DataBits >>= 1;
-		BitCount--;
+		SoftUSART_Data >>= 1;
+		SoftUSART_BitCount--;
 	}
 	else if (!IsSending && IsRisingEdge)
 	{
 		/* Wait for the start bit when receiving */
-		if ((BitCount == BITS_IN_FRAME) && (BITBANG_PDIDATA_PORT & BITBANG_PDIDATA_MASK))
+		if ((SoftUSART_BitCount == BITS_IN_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
 		  return;
 	
-		if (BITBANG_PDIDATA_PORT & BITBANG_PDIDATA_MASK)
-		  DataBits |= (1 << (BITS_IN_FRAME - 1));
+		if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
+		  SoftUSART_Data |= (1 << BITS_IN_FRAME);
 
-		DataBits >>= 1;
-		BitCount--;
+		SoftUSART_Data >>= 1;
+		SoftUSART_BitCount--;
 	}
 }
+#endif
 
 void PDITarget_EnableTargetPDI(void)
 {
+#if defined(PDI_VIA_HARDWARE_USART)
+	/* Set Tx and XCK as outputs, Rx as input */
+	DDRD |=  (1 << 5) | (1 << 3);
+	DDRD &= ~(1 << 2);
+	
+	/* Set DATA line high for at least 90ns to disable /RESET functionality */
+	PORTD |= (1 << 3);
+	asm volatile ("NOP"::);
+	asm volatile ("NOP"::);
+	
+	/* Set up the synchronous USART for XMEGA communications - 
+	   8 data bits, even parity, 2 stop bits */
+	UBRR1  = 10;
+	UCSR1B = (1 << TXEN1);
+	UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
+
+	/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
+	PDITarget_SendBreak();
+	PDITarget_SendBreak();
+#else
 	/* Set DATA and CLOCK lines to outputs */
 	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
 	BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
 	
-	/* Set DATA line high for 90ns to disable /RESET functionality */
+	/* Set DATA line high for at least 90ns to disable /RESET functionality */
 	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
 	asm volatile ("NOP"::);
 	asm volatile ("NOP"::);
 
-	/* Fire timer compare ISR every 160 cycles */
-	OCR0A   = 20;
+	/* Fire timer compare ISR every 50 cycles to manage the software USART */
+	OCR0A   = 50;
 	TCCR0A  = (1 << WGM01);
-	TCCR0B  = (1 << CS01);
+	TCCR0B  = (1 << CS00);
 	TIMSK0  = (1 << OCIE0A);
+	
+	PDITarget_SendBreak();
+	PDITarget_SendBreak();
+#endif
 }
 
 void PDITarget_DisableTargetPDI(void)
 {
+#if defined(PDI_VIA_HARDWARE_USART)
+	/* Turn off receiver and transmitter of the USART, clear settings */
+	UCSR1A |= (1 << TXC1) | (1 << RXC1);
+	UCSR1B  = 0;
+	UCSR1C  = 0;
+
+	/* Set all USART lines as input, tristate */
+	DDRD  &= ~((1 << 5) | (1 << 3));
+	PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
+#else
 	/* Set DATA and CLOCK lines to inputs */
 	BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;
 	BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;
@@ -107,125 +144,171 @@ void PDITarget_DisableTargetPDI(void)
 	BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
 
 	TCCR0B  = 0;
+#endif
 }
 
 void PDITarget_SendByte(uint8_t Byte)
 {
-	bool IsOddBitsSet = false;
+#if defined(PDI_VIA_HARDWARE_USART)
+	/* Switch to Tx mode if currently in Rx mode */
+	if (!(IsSending))
+	{
+		PORTD  |=  (1 << 3);
+		DDRD   |=  (1 << 3);
+
+		UCSR1B &= ~(1 << RXEN1);
+		UCSR1B |=  (1 << TXEN1);
+		
+		IsSending = true;
+	}
 	
-	/* Compute Even parity bit */
-	for (uint8_t i = 0; i < 8; i++)
+	/* Wait until there is space in the hardware Tx buffer before writing */
+	while (!(UCSR1A & (1 << UDRE1)));
+	UDR1 = Byte;
+#else
+	/* Switch to Tx mode if currently in Rx mode */
+	if (!(IsSending))
 	{
-		if (Byte & (1 << i))
-		  IsOddBitsSet = !(IsOddBitsSet);
+		BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
+		BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
+
+		IsSending = true;
 	}
 
-	/* Data shifted out LSB first, START DATA PARITY STOP STOP */
-	DataBits  = ((uint16_t)IsOddBitsSet << 10) | ((uint16_t)Byte << 1) | (1 << 0);
+	bool    EvenParityBit = false;
+	uint8_t ParityData    = Byte;
 
-	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
-	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
+	/* Compute Even parity bit */
+	for (uint8_t i = 0; i < 8; i++)
+	{
+		EvenParityBit ^= ParityData & 0x01;
+		ParityData    >>= 1;
+	}
 
-	IsSending = true;
-	BitCount  = BITS_IN_FRAME;
-	while (BitCount);
+	while (SoftUSART_BitCount);
 
-	BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
-	BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
+	/* Data shifted out LSB first, START DATA PARITY STOP STOP */
+	SoftUSART_Data     = ((uint16_t)EvenParityBit << 9) | ((uint16_t)Byte << 1) | (1 << 10) | (1 << 11);
+	SoftUSART_BitCount = BITS_IN_FRAME;
+#endif
 }
 
 uint8_t PDITarget_ReceiveByte(void)
 {
-	IsSending = false;
-	BitCount  = BITS_IN_FRAME;
-	while (BitCount);
+#if defined(PDI_VIA_HARDWARE_USART)
+	/* Switch to Rx mode if currently in Tx mode */
+	if (IsSending)
+	{
+		while (!(UCSR1A & (1 << TXC1)));
+		UCSR1A |=  (1 << TXC1);
 
-	return (DataBits >> 1);
-}
+		UCSR1B &= ~(1 << TXEN1);
+		UCSR1B |=  (1 << RXEN1);
 
-void PDITarget_SendBreak(void)
-{
-	DataBits  = 0;
+		DDRD   &= ~(1 << 3);
+		PORTD  &= ~(1 << 3);
+		
+		IsSending = false;
+	}
 
-	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
-	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
+	/* Wait until a byte has been received before reading */
+	while (!(UCSR1A & (1 << RXC1)));
+	return UDR1;
+#else
+	/* Switch to Rx mode if currently in Tx mode */
+	if (IsSending)
+	{
+		while (SoftUSART_BitCount);
 
-	IsSending = true;
-	BitCount  = BITS_IN_FRAME;
-	while (BitCount);
+		BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
+		BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
 
-	BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
-	BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
-}
-#else
-void PDITarget_EnableTargetPDI(void)
-{
-	/* Set Tx and XCK as outputs, Rx as input */
-	DDRD |=  (1 << 5) | (1 << 3);
-	DDRD &= ~(1 << 2);
-	
-	/* Set DATA line high for 90ns to disable /RESET functionality */
-	PORTD |= (1 << 3);
-	asm volatile ("NOP"::);
-	asm volatile ("NOP"::);
-	
-	/* Set up the synchronous USART for XMEGA communications - 
-	   8 data bits, even parity, 2 stop bits */
-	UBRR1  = 10;
-	UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
+		IsSending = false;
+	}
 
-	/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
-	PDITarget_SendBreak();
-	PDITarget_SendBreak();
+	/* Wait until a byte has been received before reading */
+	SoftUSART_BitCount = BITS_IN_FRAME;
+	while (SoftUSART_BitCount);
+	
+	/* Throw away the start, parity and stop bits to leave only the data */
+	return (uint8_t)(SoftUSART_Data >> 1);
+#endif
 }
 
-void PDITarget_DisableTargetPDI(void)
+void PDITarget_SendBreak(void)
 {
-	/* Turn of receiver and transmitter of the USART, clear settings */
-	UCSR1B = 0;
-	UCSR1C = 0;
+#if defined(PDI_VIA_HARDWARE_USART)
+	/* Switch to Tx mode if currently in Rx mode */
+	if (!(IsSending))
+	{
+		PORTD  |=  (1 << 3);
+		DDRD   |=  (1 << 3);
 
-	/* Set all USART lines as input, tristate */
-	DDRD  &= ~((1 << 5) | (1 << 3));
-	PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
-}
+		UCSR1B &= ~(1 << RXEN1);
+		UCSR1B |=  (1 << TXEN1);
+		
+		IsSending = true;
+	}
 
-void PDITarget_SendByte(uint8_t Byte)
-{
-	UCSR1B &= ~(1 << RXEN1);
-	UCSR1B |=  (1 << TXEN1);
+	/* Need to do nothing for a full frame to send a BREAK */
+	for (uint8_t i = 0; i <= BITS_IN_FRAME; i++)
+	{
+		/* Wait for a full cycle of the clock */
+		while (PIND & (1 << 5));
+		while (!(PIND & (1 << 5)));
+	}
+#else
+	/* Switch to Tx mode if currently in Rx mode */
+	if (!(IsSending))
+	{
+		BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
+		BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
 
-	UDR1 = Byte;
+		IsSending = true;
+	}
+	
+	while (SoftUSART_BitCount);
+
+	/* Need to do nothing for a full frame to send a BREAK */
+	SoftUSART_Data     = 0x0FFF;
+	SoftUSART_BitCount = BITS_IN_FRAME;
+#endif
+}
 
-	while (!(UCSR1A & (1 << TXC1)));
-	UCSR1A |=  (1 << TXC1);
+void PDITarget_SendAddress(uint32_t Address)
+{
+	PDITarget_SendByte(Address >> 24);
+	PDITarget_SendByte(Address >> 26);
+	PDITarget_SendByte(Address >> 8);
+	PDITarget_SendByte(Address &  0xFF);
 }
 
-uint8_t PDITarget_ReceiveByte(void)
+bool PDITarget_WaitWhileNVMBusBusy(void)
 {
-	UCSR1B &= ~(1 << TXEN1);
-	UCSR1B |=  (1 << RXEN1);
+	uint8_t AttemptsRemaining = 255;
 
-	while (!(UCSR1A & (1 << RXC1)));
-	UCSR1A |=  (1 << RXC1);
+	/* Poll the STATUS register to check to see if NVM access has been enabled */
+	while (AttemptsRemaining--)
+	{
+		PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
+		if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
+		  return true;
+	}
 	
-	return UDR1;
+	return false;
 }
 
-void PDITarget_SendBreak(void)
+void PDITarget_WaitWhileNVMControllerBusy(void)
 {
-	UCSR1B &= ~(1 << RXEN1);
-	UCSR1B |=  (1 << TXEN1);
-
-	for (uint8_t i = 0; i <= BITS_IN_FRAME; i++)
+	/* Poll the NVM STATUS register to check to see if NVM controller is busy */
+	for (;;)
 	{
-		/* Wait for rising edge of clock */
-		while (PIND & (1 << 5));
+		PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_1BYTE << 2));
+		PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_STATUS);
 		
-		/* Wait for falling edge of clock */
-		while (!(PIND & (1 << 5)));
+		if (!(PDITarget_ReceiveByte() & (1 << 7)))
+		  return;
 	}
 }
-#endif
 
 #endif