X-Git-Url: http://git.linex4red.de/pub/USBasp.git/blobdiff_plain/3bf760ad7d8bcc06c9145121786f3644995fae87..a8b66f318dda3cc18dfcedaa3af3d01ab68b82e8:/Projects/XPLAINBridge/Lib/SoftUART.c?ds=inline diff --git a/Projects/XPLAINBridge/Lib/SoftUART.c b/Projects/XPLAINBridge/Lib/SoftUART.c index 5de365930..7667bfa31 100644 --- a/Projects/XPLAINBridge/Lib/SoftUART.c +++ b/Projects/XPLAINBridge/Lib/SoftUART.c @@ -67,11 +67,11 @@ void SoftUART_Init(void) SoftUART_SetBaud(9600); /* Setup reception timer compare ISR */ - TIMSK2 = (1 << ICIE2); + TIMSK1 = (1 << OCIE1A); /* Setup transmission timer compare ISR and start the timer */ - TIMSK3 = (1 << ICIE3); - TCCR3B = ((1 << CS30) | (1 << WGM33) | (1 << WGM32)); + TIMSK3 = (1 << OCIE3A); + TCCR3B = ((1 << CS30) | (1 << WGM32)); } /** ISR to detect the start of a bit being sent to the software UART. */ @@ -81,7 +81,7 @@ ISR(INT0_vect, ISR_BLOCK) RX_BitsRemaining = 8; /* Reset the bit reception timer */ - TCNT2 = 0; + TCNT1 = 0; /* Check to see that the pin is still low (prevents glitches from starting a frame reception) */ if (!(SRXPIN & (1 << SRX))) @@ -90,12 +90,12 @@ ISR(INT0_vect, ISR_BLOCK) EIMSK = 0; /* Start the reception timer */ - TCCR2B = ((1 << CS20) | (1 << WGM23) | (1 << WGM22)); + TCCR1B = ((1 << CS10) | (1 << WGM12)); } } /** ISR to manage the reception of bits to the software UART. */ -ISR(TIMER2_CAPT_vect, ISR_BLOCK) +ISR(TIMER1_COMPA_vect, ISR_BLOCK) { /* Cache the current RX pin value for later checking */ uint8_t SRX_Cached = (SRXPIN & (1 << SRX)); @@ -114,7 +114,7 @@ ISR(TIMER2_CAPT_vect, ISR_BLOCK) else { /* Disable the reception timer as all data has now been received, re-enable start bit detection ISR */ - TCCR2B = 0; + TCCR1B = 0; EIFR = (1 << INTF0); EIMSK = (1 << INT0); @@ -125,7 +125,7 @@ ISR(TIMER2_CAPT_vect, ISR_BLOCK) } /** ISR to manage the transmission of bits via the software UART. */ -ISR(TIMER3_CAPT_vect, ISR_BLOCK) +ISR(TIMER3_COMPA_vect, ISR_BLOCK) { /* Check if transmission has finished */ if (TX_BitsRemaining)