* drivers. When promted, direct your OS to install Atmel's AVRISP-MKII drivers provided with AVRStudio.\r
*\r
* Note that this design currently has several limitations:\r
- * - Minimum target clock speed of 500KHz due to hardware SPI used\r
+ * - Minimum ISP target clock speed of 500KHz due to hardware SPI used\r
* - No reversed/shorted target connector detection and notification\r
*\r
- * On AVR models with an ADC converter, ACC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be\r
+ * On AVR models with an ADC converter, AVCC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be\r
* set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models\r
* without an ADC converter, VTARGET will report at a fixed 5V level.\r
*\r
- * Connections to the device are simple:\r
+ * When compiled for the XPLAIN board target, this will automatically configure itself for the correct connections to the\r
+ * XPLAIN's XMEGA AVR, and will enable only PDI programming support.\r
+ *\r
+ *\r
+ * Connections to the device for SPI programming (when enabled):\r
*\r
* <table>\r
* <tr>\r
* <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n\r
* <b><sup>2</sup></b> <i>See \ref SSec_Options section</i>\r
*\r
+ *\r
+ * Connections to the device for PDI programming (when enabled):\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <td><b>Programmer Pin:</b></td>\r
+ * <td><b>Target Device Pin:</b></td>\r
+ * <td><b>PDI 6 Pin Layout:</b></td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>MISO</td>\r
+ * <td>DATA</td>\r
+ * <td>1</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>ADCx <b><sup>1</sup></b></td>\r
+ * <td>VTARGET</td>\r
+ * <td>2</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>N/A</td>\r
+ * <td>N/A</td>\r
+ * <td>3</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>N/A</td>\r
+ * <td>N/A</td>\r
+ * <td>4</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>PORTx.y <b><sup>2</sup></b></td>\r
+ * <td>CLOCK</td>\r
+ * <td>5</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>GND</td>\r
+ * <td>GND</td>\r
+ * <td>6</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
* \section SSec_Options Project Options\r
*\r
* The following defines can be found in this demo, which can control the demo behaviour when defined, or changed in value.\r
* <tr>\r
* <td>RESET_LINE_PORT</td>\r
* <td>Makefile CDEFS</td>\r
- * <td>PORT register for the programmer's target RESET line.</td>\r
+ * <td>PORT register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>\r
* </tr>\r
* <tr>\r
* <td>RESET_LINE_DDR</td>\r
* <td>Makefile CDEFS</td>\r
- * <td>DDR register for the programmer's target RESET line.</td>\r
+ * <td>DDR register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>\r
* </tr>\r
* <tr>\r
* <td>RESET_LINE_MASK</td>\r
* <td>Makefile CDEFS</td>\r
* <td>Mask for the programmer's target RESET line on the chosen port. <b>Must not be the AVR's /SS pin</b>, as the\r
* target pins are tri-stated when not in use, and low signals on the /SS pin will force SPI slave mode when the\r
- * pin is configured as an input.</td>\r
+ * pin is configured as an input. When in PDI programming mode, this is the target clock pin.\r
+ * <i>Ignored when compiled for the XPLAIN board.</i></td>\r
* </tr>\r
* <tr>\r
* <td>VTARGET_ADC_CHANNEL</td>\r
* <td>Makefile CDEFS</td>\r
* <td>ADC channel number (on supported AVRs) to use for VTARGET level detection.</td> \r
* </tr>\r
+ * <tr>\r
+ * <td>ENABLE_ISP_PROTOCOL</td>\r
+ * <td>Makefile CDEFS</td>\r
+ * <td>Define to enable SPI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td> \r
+ * </tr>\r
+ * <tr>\r
+ * <td>ENABLE_PDI_PROTOCOL</td>\r
+ * <td>Makefile CDEFS</td>\r
+ * <td>Define to enable XMEGA PDI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td> \r
+ * </tr>\r
* </table>\r
*/\r