\r
/* Set up the synchronous USART for XMEGA communications - \r
8 data bits, even parity, 2 stop bits */\r
- UBRR1 = (F_CPU / 1000000UL);\r
+ UBRR1 = (F_CPU / 500000UL);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
#else\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
\r
- /* Set up the synchronous USART for XMEGA communications - \r
+ /* Set up the synchronous USART for TINY communications - \r
8 data bits, even parity, 2 stop bits */\r
- UBRR1 = (F_CPU / 1000000UL);\r
+ UBRR1 = (F_CPU / 500000UL);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
#else\r
XPROGTarget_SetRxMode();\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
+ /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
+ PORTD |= (1 << 5);\r
+ _delay_ms(1);\r
+\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
UCSR1B = 0;\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
+ /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
+ BITBANG_PDICLOCK_PORT |= BITBANG_PDICLOCK_MASK;\r
+ _delay_ms(1);\r
+\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;\r