Make sure that long reads are aborted early if the connection times out while waiting...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index f1bb45a..e75adbe 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -53,7 +53,7 @@ volatile uint16_t           SoftUSART_Data;
 ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
-       BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+       BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;\r
 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
@@ -80,10 +80,6 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
        }\r
        else\r
        {\r
-               /* If not sending or receiving, just exit */\r
-               if (!(SoftUSART_BitCount))\r
-                 return;\r
-\r
                /* If at falling clock edge and we are in receive mode, abort */\r
                if (!IsSending)\r
                  return;\r
@@ -103,7 +99,7 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
 ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
-       BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
+       BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;\r
 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
@@ -160,9 +156,8 @@ void XPROGTarget_EnableTargetPDI(void)
        PORTD |= (1 << 3);\r
        _delay_us(1);\r
        \r
-       /* Set up the synchronous USART for XMEGA communications - \r
-          8 data bits, even parity, 2 stop bits */\r
-       UBRR1  = (F_CPU / 500000UL);\r
+       /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */\r
+       UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r
@@ -175,10 +170,9 @@ void XPROGTarget_EnableTargetPDI(void)
        _delay_us(1);\r
 \r
        /* Fire timer compare channel A ISR to manage the software USART */\r
-       OCR1A   = BITS_BETWEEN_USART_CLOCKS;\r
-       OCR1B   = BITS_BETWEEN_USART_CLOCKS;\r
-       TCCR1B  = (1 << WGM12) | (1 << CS10);\r
-       TIMSK1  = (1 << OCIE1A);\r
+       OCR1A  = BITS_BETWEEN_USART_CLOCKS;\r
+       TCCR1B = (1 << WGM12) | (1 << CS10);\r
+       TIMSK1 = (1 << OCIE1A);\r
 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
@@ -201,9 +195,8 @@ void XPROGTarget_EnableTargetTPI(void)
        DDRD |=  (1 << 5) | (1 << 3);\r
        DDRD &= ~(1 << 2);\r
                \r
-       /* Set up the synchronous USART for TINY communications - \r
-          8 data bits, even parity, 2 stop bits */\r
-       UBRR1  = (F_CPU / 500000UL);\r
+       /* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */\r
+       UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r
@@ -215,9 +208,9 @@ void XPROGTarget_EnableTargetTPI(void)
        BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
 \r
        /* Fire timer capture channel ISR to manage the software USART */\r
-       ICR1    = BITS_BETWEEN_USART_CLOCKS;\r
-       TCCR1B  = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
-       TIMSK1  = (1 << ICIE1);\r
+       ICR1   = BITS_BETWEEN_USART_CLOCKS;\r
+       TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
+       TIMSK1 = (1 << ICIE1);\r
 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
@@ -232,26 +225,18 @@ void XPROGTarget_DisableTargetPDI(void)
        XPROGTarget_SetRxMode();\r
 \r
 #if defined(XPROG_VIA_HARDWARE_USART)\r
-       /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
-       PORTD |= (1 << 5);\r
-       _delay_ms(1);\r
-\r
        /* Turn off receiver and transmitter of the USART, clear settings */\r
-       UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
+       UCSR1A  = ((1 << TXC1) | (1 << RXC1));\r
        UCSR1B  = 0;\r
        UCSR1C  = 0;\r
 \r
-       /* Set all USART lines as input, tristate */\r
+       /* Tristate all pins */\r
        DDRD  &= ~((1 << 5) | (1 << 3));\r
        PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
 #else\r
        /* Turn off software USART management timer */\r
        TCCR1B = 0;\r
 \r
-       /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
-       BITBANG_PDICLOCK_PORT |= BITBANG_PDICLOCK_MASK;\r
-       _delay_ms(1);\r
-\r
        /* Set DATA and CLOCK lines to inputs */\r
        BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;\r
@@ -353,6 +338,9 @@ uint8_t XPROGTarget_ReceiveByte(void)
                }       \r
        }\r
        \r
+       if (TimeoutMSRemaining)\r
+         TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
+\r
        return UDR1;\r
 #else\r
        /* Wait until a byte has been received before reading */\r
@@ -414,8 +402,15 @@ static void XPROGTarget_SetTxMode(void)
                \r
        IsSending = true;\r
 #else\r
-       while (SoftUSART_BitCount);\r
-\r
+       while (SoftUSART_BitCount && TimeoutMSRemaining)\r
+       {       \r
+               if (TIFR0 & (1 << OCF0A))\r
+               {\r
+                       TIFR0 |= (1 << OCF0A);\r
+                       TimeoutMSRemaining--;\r
+               }\r
+       }\r
+       \r
        /* Wait for a full cycle of the clock */\r
        SoftUSART_Data     = 0x0001;\r
        SoftUSART_BitCount = 1;\r
@@ -448,28 +443,46 @@ static void XPROGTarget_SetRxMode(void)
        DDRD   &= ~(1 << 3);\r
        PORTD  &= ~(1 << 3);\r
 #else\r
-       while (SoftUSART_BitCount);\r
+       while (SoftUSART_BitCount && TimeoutMSRemaining)\r
+       {       \r
+               if (TIFR0 & (1 << OCF0A))\r
+               {\r
+                       TIFR0 |= (1 << OCF0A);\r
+                       TimeoutMSRemaining--;\r
+               }\r
+       }\r
 \r
        if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
        {\r
                BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;\r
                BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
+\r
+               /* Wait until DATA line has been pulled up to idle by the target */\r
+               while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)\r
+               {\r
+                       /* Manage software timeout */\r
+                       if (TIFR0 & (1 << OCF0A))\r
+                       {\r
+                               TIFR0 |= (1 << OCF0A);\r
+                               TimeoutMSRemaining--;\r
+                       }\r
+               }\r
        }\r
        else\r
        {\r
                BITBANG_TPIDATA_DDR  &= ~BITBANG_TPIDATA_MASK;\r
-               BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;  \r
-       }\r
-       \r
-       /* Wait until DATA line has been pulled up to idle by the target */\r
-       while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)\r
-       {\r
-               /* Manage software timeout */\r
-               if (TIFR0 & (1 << OCF0A))\r
+               BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
+\r
+               /* Wait until DATA line has been pulled up to idle by the target */\r
+               while (!(BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK) && TimeoutMSRemaining)\r
                {\r
-                       TIFR0 |= (1 << OCF0A);\r
-                       TimeoutMSRemaining--;\r
-               }\r
+                       /* Manage software timeout */\r
+                       if (TIFR0 & (1 << OCF0A))\r
+                       {\r
+                               TIFR0 |= (1 << OCF0A);\r
+                               TimeoutMSRemaining--;\r
+                       }\r
+               }       \r
        }       \r
 #endif\r
 \r