Complete combining of PDI and TPI target communication code files, stub out TINY...

[pub/USBasp.git] / Projects / AVRISP / Lib / XPROG / XMEGANVM.c

diff --git a/Projects/AVRISP/Lib/XPROG/XMEGANVM.c b/Projects/AVRISP/Lib/XPROG/XMEGANVM.c
index dffa62d..6280f60 100644 (file)
--- a/Projects/AVRISP/Lib/XPROG/XMEGANVM.c
+++ b/Projects/AVRISP/Lib/XPROG/XMEGANVM.c
@@ -58,10 +58,40 @@ void XMEGANVM_SendNVMRegAddress(const uint8_t Register)
 void XMEGANVM_SendAddress(const uint32_t AbsoluteAddress)\r
 {\r
        /* Send the given 32-bit address to the target, LSB first */\r
-       PDITarget_SendByte(AbsoluteAddress &  0xFF);\r
-       PDITarget_SendByte(AbsoluteAddress >> 8);\r
-       PDITarget_SendByte(AbsoluteAddress >> 16);\r
-       PDITarget_SendByte(AbsoluteAddress >> 24);\r
+       XPROGTarget_SendByte(AbsoluteAddress &  0xFF);\r
+       XPROGTarget_SendByte(AbsoluteAddress >> 8);\r
+       XPROGTarget_SendByte(AbsoluteAddress >> 16);\r
+       XPROGTarget_SendByte(AbsoluteAddress >> 24);\r
+}\r
+\r
+/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC\r
+ *  calculation.\r
+ *\r
+ *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise\r
+ */\r
+bool XMEGANVM_WaitWhileNVMBusBusy(void)\r
+{\r
+       TCNT0 = 0;\r
+       TIFR0 = (1 << OCF1A);\r
+                       \r
+       uint8_t TimeoutMS = XMEGA_NVM_BUSY_TIMEOUT_MS;\r
+       \r
+       /* Poll the STATUS register to check to see if NVM access has been enabled */\r
+       while (TimeoutMS)\r
+       {\r
+               /* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */\r
+               XPROGTarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
+               if (XPROGTarget_ReceiveByte() & PDI_STATUS_NVM)\r
+                 return true;\r
+\r
+               if (TIFR0 & (1 << OCF1A))\r
+               {\r
+                       TIFR0 = (1 << OCF1A);\r
+                       TimeoutMS--;\r
+               }\r
+       }\r
+       \r
+       return false;\r
 }\r
 \r
 /** Waits while the target's NVM controller is busy performing an operation, exiting if the\r
@@ -80,11 +110,11 @@ bool XMEGANVM_WaitWhileNVMControllerBusy(void)
        while (TimeoutMS)\r
        {\r
                /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
-               PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_STATUS);\r
                \r
                /* Check to see if the BUSY flag is still set */\r
-               if (!(PDITarget_ReceiveByte() & (1 << 7)))\r
+               if (!(XPROGTarget_ReceiveByte() & (1 << 7)))\r
                  return true;\r
 \r
                if (TIFR0 & (1 << OCF1A))\r
@@ -111,17 +141,17 @@ bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)
          return false;\r
          \r
        /* Set the NVM command to the correct CRC read command */\r
-       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-       PDITarget_SendByte(CRCCommand);\r
+       XPROGTarget_SendByte(CRCCommand);\r
 \r
        /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */\r
-       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);\r
-       PDITarget_SendByte(1 << 0);\r
+       XPROGTarget_SendByte(1 << 0);\r
 \r
        /* Wait until the NVM bus is ready again */\r
-       if (!(PDITarget_WaitWhileNVMBusBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMBusBusy()))\r
          return false;\r
 \r
        /* Wait until the NVM controller is no longer busy */\r
@@ -131,19 +161,19 @@ bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)
        *CRCDest = 0;\r
        \r
        /* Read the first generated CRC byte value */\r
-       PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT0);\r
-       *CRCDest  = PDITarget_ReceiveByte();\r
+       *CRCDest  = XPROGTarget_ReceiveByte();\r
 \r
        /* Read the second generated CRC byte value */\r
-       PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT1);\r
-       *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
+       *CRCDest |= ((uint16_t)XPROGTarget_ReceiveByte() << 8);\r
 \r
        /* Read the third generated CRC byte value */\r
-       PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT2);\r
-       *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
+       *CRCDest |= ((uint32_t)XPROGTarget_ReceiveByte() << 16);\r
        \r
        return true;\r
 }\r
@@ -163,22 +193,22 @@ bool XMEGANVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const
          return false;\r
        \r
        /* Send the READNVM command to the NVM controller for reading of an arbitrary location */\r
-       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-       PDITarget_SendByte(XMEGA_NVM_CMD_READNVM);\r
+       XPROGTarget_SendByte(XMEGA_NVM_CMD_READNVM);\r
 \r
        /* Load the PDI pointer register with the start address we want to read from */\r
-       PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
+       XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
        XMEGANVM_SendAddress(ReadAddress);\r
 \r
        /* Send the REPEAT command with the specified number of bytes to read */\r
-       PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
-       PDITarget_SendByte(ReadSize - 1);\r
+       XPROGTarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+       XPROGTarget_SendByte(ReadSize - 1);\r
                \r
        /* Send a LD command with indirect access and postincrement to read out the bytes */\r
-       PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
+       XPROGTarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
        for (uint16_t i = 0; i < ReadSize; i++)\r
-         *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+         *(ReadBuffer++) = XPROGTarget_ReceiveByte();\r
        \r
        return true;\r
 }\r
@@ -198,14 +228,14 @@ bool XMEGANVM_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAd
          return false;\r
 \r
        /* Send the memory write command to the target */\r
-       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-       PDITarget_SendByte(WriteCommand);\r
+       XPROGTarget_SendByte(WriteCommand);\r
        \r
        /* Send new memory byte to the memory to the target */\r
-       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendAddress(WriteAddress);\r
-       PDITarget_SendByte(*(WriteBuffer++));\r
+       XPROGTarget_SendByte(*(WriteBuffer++));\r
        \r
        return true;\r
 }\r
@@ -233,14 +263,14 @@ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t Eras
                  return false;\r
 \r
                /* Send the memory buffer erase command to the target */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-               PDITarget_SendByte(EraseBuffCommand);\r
+               XPROGTarget_SendByte(EraseBuffCommand);\r
 \r
                /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);\r
-               PDITarget_SendByte(1 << 0);\r
+               XPROGTarget_SendByte(1 << 0);\r
        }\r
 \r
        if (WriteSize)\r
@@ -250,22 +280,22 @@ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t Eras
                  return false;\r
 \r
                /* Send the memory buffer write command to the target */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-               PDITarget_SendByte(WriteBuffCommand);\r
+               XPROGTarget_SendByte(WriteBuffCommand);\r
 \r
                /* Load the PDI pointer register with the start address we want to write to */\r
-               PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
+               XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
                XMEGANVM_SendAddress(WriteAddress);\r
 \r
                /* Send the REPEAT command with the specified number of bytes to write */\r
-               PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
-               PDITarget_SendByte(WriteSize - 1);\r
+               XPROGTarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+               XPROGTarget_SendByte(WriteSize - 1);\r
                        \r
                /* Send a ST command with indirect access and postincrement to write the bytes */\r
-               PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
+               XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
                for (uint16_t i = 0; i < WriteSize; i++)\r
-                 PDITarget_SendByte(*(WriteBuffer++));\r
+                 XPROGTarget_SendByte(*(WriteBuffer++));\r
        }\r
        \r
        if (PageMode & XPRG_PAGEMODE_WRITE)\r
@@ -275,14 +305,14 @@ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t Eras
                  return false;\r
 \r
                /* Send the memory write command to the target */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-               PDITarget_SendByte(WritePageCommand);\r
+               XPROGTarget_SendByte(WritePageCommand);\r
                \r
                /* Send the address of the first page location to write the memory page */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendAddress(WriteAddress);\r
-               PDITarget_SendByte(0x00);\r
+               XPROGTarget_SendByte(0x00);\r
        }\r
 \r
        return true;\r
@@ -302,28 +332,28 @@ bool XMEGANVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)
          return false;\r
          \r
        /* Send the memory erase command to the target */\r
-       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);\r
-       PDITarget_SendByte(EraseCommand);\r
+       XPROGTarget_SendByte(EraseCommand);\r
        \r
        /* Chip erase is handled separately, since it's procedure is different to other erase types */\r
        if (EraseCommand == XMEGA_NVM_CMD_CHIPERASE)\r
        {\r
                /* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);\r
-               PDITarget_SendByte(1 << 0);             \r
+               XPROGTarget_SendByte(1 << 0);           \r
        }\r
        else\r
        {\r
                /* Other erase modes just need us to address a byte within the target memory space */\r
-               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
                XMEGANVM_SendAddress(Address);  \r
-               PDITarget_SendByte(0x00);\r
+               XPROGTarget_SendByte(0x00);\r
        }\r
        \r
        /* Wait until the NVM bus is ready again */\r
-       if (!(PDITarget_WaitWhileNVMBusBusy()))\r
+       if (!(XMEGANVM_WaitWhileNVMBusBusy()))\r
          return false;\r
          \r
        return true;\r