* two bits of the 6-bit address are shifted left once */\r
XPROGTarget_SendByte(TPI_CMD_SIN | ((Address & 0x30) << 1) | (Address & 0x0F));\r
}\r
* two bits of the 6-bit address are shifted left once */\r
XPROGTarget_SendByte(TPI_CMD_SIN | ((Address & 0x30) << 1) | (Address & 0x0F));\r
}\r
{\r
/* The TPI command for writing to the I/O space uses wierd addressing, where the I/O address's upper\r
* two bits of the 6-bit address are shifted left once */\r
{\r
/* The TPI command for writing to the I/O space uses wierd addressing, where the I/O address's upper\r
* two bits of the 6-bit address are shifted left once */\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
while (TimeoutMSRemaining)\r
{\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
while (TimeoutMSRemaining)\r
{\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(TINYNVM_WaitWhileNVMControllerBusy()))\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(TINYNVM_WaitWhileNVMControllerBusy()))\r
-bool TINYNVM_WriteMemory(const uint32_t WriteAddress, const uint8_t* WriteBuffer, uint16_t WriteLength)\r
+bool TINYNVM_WriteMemory(const uint16_t WriteAddress, const uint8_t* WriteBuffer, uint16_t WriteLength)\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(TINYNVM_WaitWhileNVMControllerBusy()))\r
{\r
/* Wait until the NVM controller is no longer busy */\r
if (!(TINYNVM_WaitWhileNVMControllerBusy()))\r