*/\r
static void TINYNVM_SendWriteNVMRegister(const uint8_t Address)\r
{\r
- /* The TPI command for writing to the I/O space uses weird addressing, where the I/O address's upper\r
+ /* The TPI command for reading from the I/O space uses strange addressing, where the I/O address's upper\r
* two bits of the 6-bit address are shifted left once */\r
XPROGTarget_SendByte(TPI_CMD_SOUT | ((Address & 0x30) << 1) | (Address & 0x0F));\r
}\r
bool TINYNVM_WaitWhileNVMBusBusy(void)\r
{\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
- uint8_t TimeoutMSRemaining = 100;\r
while (TimeoutMSRemaining)\r
{\r
/* Send the SLDCS command to read the TPI STATUS register to see the NVM bus is active */\r
XPROGTarget_SendByte(TPI_CMD_SLDCS | TPI_STATUS_REG);\r
if (XPROGTarget_ReceiveByte() & TPI_STATUS_NVM)\r
- return true;\r
+ {\r
+ TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
+ return true;\r
+ }\r
\r
/* Manage software timeout */\r
if (TIFR0 & (1 << OCF0A))\r
bool TINYNVM_WaitWhileNVMControllerBusy(void)\r
{\r
/* Poll the STATUS register to check to see if NVM access has been enabled */\r
- uint8_t TimeoutMSRemaining = 100;\r
while (TimeoutMSRemaining)\r
{\r
/* Send the SIN command to read the TPI STATUS register to see the NVM bus is busy */\r
\r
/* Check to see if the BUSY flag is still set */\r
if (!(XPROGTarget_ReceiveByte() & (1 << 7)))\r
- return true;\r
+ {\r
+ TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
+ return true;\r
+ }\r
\r
/* Manage software timeout */\r
if (TIFR0 & (1 << OCF0A))\r