- OCR2B = TCNT2 + 1; // force first compare
- TCCR2A = (1 << COM2B1) | (1 << COM2B0); // T1 mode 0
- TCCR2B = (1 << FOC2B) | (1 << CS21); // CLK/8, T1 mode 0
- TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
- EICRA = (1 << ISC01); // -ve edge
- EIMSK = (1 << INT0); // enable INT0 interrupt
-
- stx_count = 0; // nothing to send
- srx_done = false; // nothing received
- STXPORT |= (1 << STX); // TX output
- STXDDR |= (1 << STX); // TX output
- SRXPORT |= (1 << SRX); // pullup on INT0
+ /* Set TX pin to output high, enable RX pullup */
+ STXPORT |= (1 << STX);
+ STXDDR |= (1 << STX);
+ SRXPORT |= (1 << SRX);
+
+ /* Enable INT0 for the detection of incomming start bits that signal the start of a byte */
+ EICRA = (1 << ISC01);
+ EIMSK = (1 << INT0);
+
+ /* Ensure that when the timer is enabled the transmission ISR runs immediately */
+ OCR1B = TCNT1 + 1;
+
+ /* Start timer 1 with transmission channel force-enabled so that it will immediatly fire */
+ TCCR1C = (1 << FOC1B);
+ TIMSK1 = (1 << OCIE1B);
+ TCCR1B = (1 << CS10);