Added memory erase handling to the PDI protocol in the AVRISP project.

[pub/USBasp.git] / Projects / AVRISP / Lib / NVMTarget.c

diff --git a/Projects/AVRISP/Lib/NVMTarget.c b/Projects/AVRISP/Lib/NVMTarget.c
index fee432c..a23ccf2 100644 (file)
--- a/Projects/AVRISP/Lib/NVMTarget.c
+++ b/Projects/AVRISP/Lib/NVMTarget.c
@@ -137,4 +137,31 @@ void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t Re
        }\r
 }\r
 \r
+void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)\r
+{\r
+       NVMTarget_WaitWhileNVMControllerBusy();\r
+\r
+       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+       PDITarget_SendByte(EraseCommand);\r
+       \r
+       if (EraseCommand == NVM_CMD_CHIPERASE)\r
+       {\r
+               /* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
+               PDITarget_SendByte(1 << 0);             \r
+       }\r
+       else\r
+       {\r
+               /* Other erase modes just need us to address a byte within the target memory space */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendAddress(Address); \r
+               PDITarget_SendByte(0x00);\r
+       }\r
+       \r
+       NVMTarget_WaitWhileNVMBusBusy();\r
+       NVMTarget_WaitWhileNVMControllerBusy();\r
+}\r
+\r
 #endif\r