Ooops - TeensyHID bootloader makefile should use a 16MHz FCPU, not 8MHz.

[pub/USBasp.git] / Projects / AVRISP / Lib / NVMTarget.c

diff --git a/Projects/AVRISP/Lib/NVMTarget.c b/Projects/AVRISP/Lib/NVMTarget.c
index fee432c..adf213b 100644 (file)
--- a/Projects/AVRISP/Lib/NVMTarget.c
+++ b/Projects/AVRISP/Lib/NVMTarget.c
@@ -38,103 +38,295 @@
 \r
 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)\r
 \r
 \r
 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)\r
 \r

-void NVMTarget_SendNVMRegAddress(uint8_t Register)\r
+/** Sends the given NVM register address to the target.\r
+ *\r
+ *  \param[in] Register  NVM register whose absolute address is to be sent\r
+ */\r
+void NVMTarget_SendNVMRegAddress(const uint8_t Register)\r

 {\r
 {\r

+       /* Determine the absolute register address from the NVM base memory address and the NVM register address */\r

        uint32_t Address = XPROG_Param_NVMBase | Register;\r
 \r
        uint32_t Address = XPROG_Param_NVMBase | Register;\r
 \r

-       PDITarget_SendByte(Address &  0xFF);\r
-       PDITarget_SendByte(Address >> 8);\r
-       PDITarget_SendByte(Address >> 16);\r
-       PDITarget_SendByte(Address >> 24);\r
+       /* Send the calculated 32-bit address to the target, LSB first */\r
+       NVMTarget_SendAddress(Address);\r

 }\r
 \r
 }\r
 \r

-void NVMTarget_SendAddress(uint32_t AbsoluteAddress)\r
+/** Sends the given 32-bit absolute address to the target.\r
+ *\r
+ *  \param[in] AbsoluteAddress  Absolute address to send to the target\r
+ */\r
+void NVMTarget_SendAddress(const uint32_t AbsoluteAddress)\r

 {\r
 {\r

+       /* Send the given 32-bit address to the target, LSB first */\r

        PDITarget_SendByte(AbsoluteAddress &  0xFF);\r
        PDITarget_SendByte(AbsoluteAddress >> 8);\r
        PDITarget_SendByte(AbsoluteAddress >> 16);\r
        PDITarget_SendByte(AbsoluteAddress >> 24);\r
 }\r
 \r
        PDITarget_SendByte(AbsoluteAddress &  0xFF);\r
        PDITarget_SendByte(AbsoluteAddress >> 8);\r
        PDITarget_SendByte(AbsoluteAddress >> 16);\r
        PDITarget_SendByte(AbsoluteAddress >> 24);\r
 }\r
 \r

-bool NVMTarget_WaitWhileNVMBusBusy(void)\r
+/** Waits while the target's NVM controller is busy performing an operation, exiting if the\r
+ *  timeout period expires.\r
+ *\r
+ *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise\r
+ */\r
+bool NVMTarget_WaitWhileNVMControllerBusy(void)\r

 {\r
 {\r

-       uint8_t AttemptsRemaining = 255;\r
-\r
-       /* Poll the STATUS register to check to see if NVM access has been enabled */\r
-       while (AttemptsRemaining--)\r
-       {\r
-               PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
-               if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
-                 return true;\r
-       }\r
+       TCNT0 = 0;\r
+       TIFR0 = (1 << OCF1A);\r
+                       \r
+       uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS;\r

        \r
        \r

-       return false;\r
-}\r
-\r
-void NVMTarget_WaitWhileNVMControllerBusy(void)\r
-{\r

        /* Poll the NVM STATUS register while the NVM controller is busy */\r
        /* Poll the NVM STATUS register while the NVM controller is busy */\r

-       for (;;)\r
+       while (TimeoutMS)\r

        {\r
        {\r

+               /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r

                PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
                NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
                \r
                PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
                NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
                \r

+               /* Check to see if the BUSY flag is still set */\r

                if (!(PDITarget_ReceiveByte() & (1 << 7)))\r
                if (!(PDITarget_ReceiveByte() & (1 << 7)))\r

-                 return;\r
+                 return true;\r
+\r
+               if (TIFR0 & (1 << OCF1A))\r
+               {\r
+                       TIFR0 = (1 << OCF1A);\r
+                       TimeoutMS--;\r
+               }\r

        }\r
        }\r

+       \r
+       return false;\r

 }\r
 \r
 }\r
 \r

-uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)\r
+/** Retrieves the CRC value of the given memory space.\r
+ *\r
+ *  \param[in]  CRCCommand  NVM CRC command to issue to the target\r
+ *  \param[out] CRCDest     CRC Destination when read from the target\r
+ *\r
+ *  \return Boolean true if the command sequence complete successfully\r
+ */\r
+bool NVMTarget_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest)\r

 {\r
 {\r

-       uint32_t MemoryCRC;\r
-\r
-       NVMTarget_WaitWhileNVMControllerBusy();\r
-\r
+       /* Wait until the NVM controller is no longer busy */\r
+       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+         return false;\r
+         \r

        /* Set the NVM command to the correct CRC read command */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
        /* Set the NVM command to the correct CRC read command */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r

-       PDITarget_SendByte(MemoryCommand);\r
+       PDITarget_SendByte(CRCCommand);\r

 \r
        /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
        PDITarget_SendByte(1 << 0);\r
 \r
 \r
        /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */\r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
        PDITarget_SendByte(1 << 0);\r
 \r

-       /* Wait until the NVM bus and controller is no longer busy */\r
-       NVMTarget_WaitWhileNVMBusBusy();\r
-       NVMTarget_WaitWhileNVMControllerBusy();\r
+       /* Wait until the NVM bus is ready again */\r
+       if (!(PDITarget_WaitWhileNVMBusBusy()))\r
+         return false;\r
+\r
+       /* Wait until the NVM controller is no longer busy */\r
+       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+         return false;\r
+       \r
+       *CRCDest = 0;\r

        \r
        \r

-       /* Read the three bytes generated CRC value */\r
+       /* Read the first generated CRC byte value */\r

        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);\r

-       MemoryCRC  = PDITarget_ReceiveByte();\r
+       *CRCDest  = PDITarget_ReceiveByte();\r

 \r
 \r

+       /* Read the second generated CRC byte value */\r

        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);\r

-       MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
+       *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r

 \r
 \r

+       /* Read the third generated CRC byte value */\r

        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);\r
        PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);\r

-       MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
+       *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r

        \r
        \r

-       return MemoryCRC;\r
+       return true;\r

 }\r
 \r
 }\r
 \r

-void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)\r
+/** Reads memory from the target's memory spaces.\r
+ *\r
+ *  \param[in]  ReadAddress  Start address to read from within the target's address space\r
+ *  \param[out] ReadBuffer   Buffer to store read data into\r
+ *  \param[in]  ReadSize     Number of bytes to read\r
+ *\r
+ *  \return Boolean true if the command sequence complete successfully\r
+ */\r
+bool NVMTarget_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, const uint16_t ReadSize)\r

 {\r
 {\r

-       NVMTarget_WaitWhileNVMControllerBusy();\r
-\r
+       /* Wait until the NVM controller is no longer busy */\r
+       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+         return false;\r
+       \r
+       /* Send the READNVM command to the NVM controller for reading of an arbitrary location */\r

        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
        PDITarget_SendByte(NVM_CMD_READNVM);\r
 \r
        PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
        NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
        PDITarget_SendByte(NVM_CMD_READNVM);\r
 \r

-       /* TODO: Optimize via REPEAT and buffer orientated commands */\r
+       /* Load the PDI pointer register with the start address we want to read from */\r
+       PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
+       NVMTarget_SendAddress(ReadAddress);\r
+\r
+       /* Send the REPEAT command with the specified number of bytes to read */\r
+       PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+       PDITarget_SendByte(ReadSize - 1);\r
+               \r
+       /* Send a LD command with indirect access and postincrement to read out the bytes */\r
+       PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r

        for (uint16_t i = 0; i < ReadSize; i++)\r
        for (uint16_t i = 0; i < ReadSize; i++)\r

+         *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+       \r
+       return true;\r
+}\r
+\r
+/** Writes byte addressed memory to the target's memory spaces.\r
+ *\r
+ *  \param[in]  WriteCommand  Command to send to the device to write each memory byte\r
+ *  \param[in]  WriteAddress  Start address to write to within the target's address space\r
+ *  \param[in]  WriteBuffer   Buffer to source data from\r
+ *\r
+ *  \return Boolean true if the command sequence complete successfully\r
+ */\r
+bool NVMTarget_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t* WriteBuffer)\r
+{\r
+       /* Wait until the NVM controller is no longer busy */\r
+       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+         return false;\r
+\r
+       /* Send the memory write command to the target */\r
+       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+       PDITarget_SendByte(WriteCommand);\r
+       \r
+       /* Send new memory byte to the memory to the target */\r
+       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       NVMTarget_SendAddress(WriteAddress);\r
+       PDITarget_SendByte(*(WriteBuffer++));\r
+       \r
+       return true;\r
+}\r
+\r
+/** Writes page addressed memory to the target's memory spaces.\r
+ *\r
+ *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer\r
+ *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer\r
+ *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory\r
+ *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page\r
+ *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space\r
+ *  \param[in]  WriteBuffer       Buffer to source data from\r
+ *  \param[in]  WriteSize         Number of bytes to write\r
+ *\r
+ *  \return Boolean true if the command sequence complete successfully\r
+ */\r
+bool NVMTarget_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand,\r
+                               const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress,\r
+                               const uint8_t* WriteBuffer, const uint16_t WriteSize)\r
+{\r
+       if (PageMode & XPRG_PAGEMODE_ERASE)\r

        {\r
        {\r

-               PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
-               NVMTarget_SendAddress(ReadAddress++);\r
-               *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+               /* Wait until the NVM controller is no longer busy */\r
+               if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+                 return false;\r
+\r
+               /* Send the memory buffer erase command to the target */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+               PDITarget_SendByte(EraseBuffCommand);\r
+\r
+               /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
+               PDITarget_SendByte(1 << 0);\r
+       }\r
+\r
+       if (WriteSize)\r
+       {\r
+               /* Wait until the NVM controller is no longer busy */\r
+               if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+                 return false;\r
+\r
+               /* Send the memory buffer write command to the target */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+               PDITarget_SendByte(WriteBuffCommand);\r
+\r
+               /* Load the PDI pointer register with the start address we want to write to */\r
+               PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);\r
+               NVMTarget_SendAddress(WriteAddress);\r
+\r
+               /* Send the REPEAT command with the specified number of bytes to write */\r
+               PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);\r
+               PDITarget_SendByte(WriteSize - 1);\r
+                       \r
+               /* Send a ST command with indirect access and postincrement to write the bytes */\r
+               PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
+               for (uint16_t i = 0; i < WriteSize; i++)\r
+                 PDITarget_SendByte(*(WriteBuffer++));\r

        }\r
        }\r

+       \r
+       if (PageMode & XPRG_PAGEMODE_WRITE)\r
+       {\r
+               /* Wait until the NVM controller is no longer busy */\r
+               if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+                 return false;\r
+\r
+               /* Send the memory write command to the target */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+               PDITarget_SendByte(WritePageCommand);\r
+               \r
+               /* Send the address of the first page location to write the memory page */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendAddress(WriteAddress);\r
+               PDITarget_SendByte(0x00);\r
+       }\r
+\r
+       return true;\r
+}\r
+\r
+/** Erases a specific memory space of the target.\r
+ *\r
+ *  \param[in] EraseCommand  NVM erase command to send to the device\r
+ *  \param[in] Address  Address inside the memory space to erase\r
+ *\r
+ *  \return Boolean true if the command sequence complete successfully\r
+ */\r
+bool NVMTarget_EraseMemory(const uint8_t EraseCommand, const uint32_t Address)\r
+{\r
+       /* Wait until the NVM controller is no longer busy */\r
+       if (!(NVMTarget_WaitWhileNVMControllerBusy()))\r
+         return false;\r
+         \r
+       /* Send the memory erase command to the target */\r
+       PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+       NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
+       PDITarget_SendByte(EraseCommand);\r
+       \r
+       /* Chip erase is handled separately, since it's procedure is different to other erase types */\r
+       if (EraseCommand == NVM_CMD_CHIPERASE)\r
+       {\r
+               /* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);\r
+               PDITarget_SendByte(1 << 0);             \r
+       }\r
+       else\r
+       {\r
+               /* Other erase modes just need us to address a byte within the target memory space */\r
+               PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
+               NVMTarget_SendAddress(Address); \r
+               PDITarget_SendByte(0x00);\r
+       }\r
+       \r
+       /* Wait until the NVM bus is ready again */\r
+       if (!(PDITarget_WaitWhileNVMBusBusy()))\r
+         return false;\r
+         \r
+       return true;\r

 }\r
 \r
 #endif\r
 }\r
 \r
 #endif\r