ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
- BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+ BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
/* Wait for the start bit when receiving */\r
if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
return;\r
- \r
+\r
/* Shift in the bit one less than the frame size in position, so that the start bit will eventually\r
* be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */\r
if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; \r
\r
SoftUSART_Data >>= 1;\r
- SoftUSART_BitCount--;\r
+ SoftUSART_BitCount--; \r
}\r
}\r
\r
ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
- BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
+ BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
\r
/* Set DATA line high for at least 90ns to disable /RESET functionality */\r
PORTD |= (1 << 3);\r
- _delay_ms(1);\r
+ _delay_us(1);\r
\r
/* Set up the synchronous USART for XMEGA communications - \r
8 data bits, even parity, 2 stop bits */\r
- UBRR1 = (F_CPU / 500000UL);\r
+ UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
#else\r
\r
/* Set DATA line high for at least 90ns to disable /RESET functionality */\r
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- _delay_ms(1);\r
+ _delay_us(1);\r
\r
/* Fire timer compare channel A ISR to manage the software USART */\r
OCR1A = BITS_BETWEEN_USART_CLOCKS;\r
+ OCR1B = BITS_BETWEEN_USART_CLOCKS;\r
TCCR1B = (1 << WGM12) | (1 << CS10);\r
TIMSK1 = (1 << OCIE1A);\r
#endif\r
/* Set /RESET line low for at least 400ns to enable TPI functionality */\r
AUX_LINE_DDR |= AUX_LINE_MASK;\r
AUX_LINE_PORT &= ~AUX_LINE_MASK;\r
- _delay_ms(1);\r
+ _delay_us(1);\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
\r
/* Set up the synchronous USART for TINY communications - \r
8 data bits, even parity, 2 stop bits */\r
- UBRR1 = (F_CPU / 500000UL);\r
+ UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);\r
UCSR1B = (1 << TXEN1);\r
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
#else\r
XPROGTarget_SetRxMode();\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
- /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
- PORTD |= (1 << 5);\r
- _delay_ms(1);\r
-\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
- UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
+ UCSR1A = ((1 << TXC1) | (1 << RXC1));\r
UCSR1B = 0;\r
UCSR1C = 0;\r
\r
- /* Set all USART lines as input, tristate */\r
+ /* Tristate all pins */\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
- /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
- BITBANG_PDICLOCK_PORT |= BITBANG_PDICLOCK_MASK;\r
- _delay_ms(1);\r
+ /* Turn off software USART management timer */\r
+ TCCR1B = 0;\r
\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
\r
/* Tristate DATA and CLOCK lines */\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;\r
+ BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK; \r
#endif\r
}\r
\r
DDRD &= ~((1 << 5) | (1 << 3));\r
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
#else\r
+ /* Turn off software USART management timer */\r
+ TCCR1B = 0;\r
+\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait until a byte has been received before reading */\r
- while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining);\r
+ while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining)\r
+ {\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
+ {\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
+ } \r
+ }\r
+ \r
return UDR1;\r
#else\r
/* Wait until a byte has been received before reading */\r
SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
- while (SoftUSART_BitCount && TimeoutMSRemaining);\r
+ while (SoftUSART_BitCount && TimeoutMSRemaining)\r
+ {\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
+ {\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
+ }\r
+ }\r
+\r
+ if (TimeoutMSRemaining)\r
+ TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
\r
/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */\r
return (uint8_t)SoftUSART_Data;\r
}\r
\r
/* Wait until DATA line has been pulled up to idle by the target */\r
- while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining);\r
+ while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)\r
+ {\r
+ /* Manage software timeout */\r
+ if (TIFR0 & (1 << OCF0A))\r
+ {\r
+ TIFR0 |= (1 << OCF0A);\r
+ TimeoutMSRemaining--;\r
+ }\r
+ } \r
#endif\r
\r
+ if (TimeoutMSRemaining)\r
+ TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
+\r
IsSending = false;\r
}\r
\r