ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
/* Wait for the start bit when receiving */\r
if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
return;\r
/* Wait for the start bit when receiving */\r
if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))\r
return;\r
if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)\r
((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
\r
/* If not sending or receiving, just exit */\r
if (!(SoftUSART_BitCount))\r
if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)\r
((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)\r
((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));\r
\r
- /* Set up the synchronous USART for XMEGA communications - \r
- 8 data bits, even parity, 2 stop bits */\r
- UBRR1 = (F_CPU / 1000000UL);\r
+ /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */\r
+ UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);\r
/* Set DATA line high for at least 90ns to disable /RESET functionality */\r
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
/* Set DATA line high for at least 90ns to disable /RESET functionality */\r
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- OCR1A = BITS_BETWEEN_USART_CLOCKS;\r
- TCCR1B = (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << OCIE1A);\r
+ OCR1A = BITS_BETWEEN_USART_CLOCKS;\r
+ TCCR1B = (1 << WGM12) | (1 << CS10);\r
+ TIMSK1 = (1 << OCIE1A);\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
DDRD |= (1 << 5) | (1 << 3);\r
DDRD &= ~(1 << 2);\r
\r
- /* Set up the synchronous USART for XMEGA communications - \r
- 8 data bits, even parity, 2 stop bits */\r
- UBRR1 = (F_CPU / 1000000UL);\r
+ /* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */\r
+ UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);\r
- /* Fire timer capture channel B ISR to manage the software USART */\r
- OCR1B = BITS_BETWEEN_USART_CLOCKS;\r
- TCCR1B = (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << OCIE1B);\r
+ /* Fire timer capture channel ISR to manage the software USART */\r
+ ICR1 = BITS_BETWEEN_USART_CLOCKS;\r
+ TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
+ TIMSK1 = (1 << ICIE1);\r
/** Disables the target's PDI interface, exits programming mode and starts the target's application. */\r
void XPROGTarget_DisableTargetPDI(void)\r
{\r
/** Disables the target's PDI interface, exits programming mode and starts the target's application. */\r
void XPROGTarget_DisableTargetPDI(void)\r
{\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;\r
\r
/* Tristate DATA and CLOCK lines */\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;\r
\r
/* Tristate DATA and CLOCK lines */\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
#endif\r
}\r
\r
/** Disables the target's TPI interface, exits programming mode and starts the target's application. */\r
void XPROGTarget_DisableTargetTPI(void)\r
{\r
#endif\r
}\r
\r
/** Disables the target's TPI interface, exits programming mode and starts the target's application. */\r
void XPROGTarget_DisableTargetTPI(void)\r
{\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Turn off receiver and transmitter of the USART, clear settings */\r
UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
/* Set DATA and CLOCK lines to inputs */\r
BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;\r
BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;\r
uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));\r
\r
/* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */\r
uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));\r
\r
/* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait until a byte has been received before reading */\r
while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining);\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Wait until a byte has been received before reading */\r
while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining);\r
return UDR1;\r
#else\r
/* Wait until a byte has been received before reading */\r
SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
while (SoftUSART_BitCount && TimeoutMSRemaining);\r
\r
return UDR1;\r
#else\r
/* Wait until a byte has been received before reading */\r
SoftUSART_BitCount = BITS_IN_USART_FRAME;\r
while (SoftUSART_BitCount && TimeoutMSRemaining);\r
\r
/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */\r
return (uint8_t)SoftUSART_Data;\r
#endif\r
/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */\r
return (uint8_t)SoftUSART_Data;\r
#endif\r
/* Wait for a full cycle of the clock */\r
SoftUSART_Data = 0x0001;\r
SoftUSART_BitCount = 1;\r
/* Wait for a full cycle of the clock */\r
SoftUSART_Data = 0x0001;\r
SoftUSART_BitCount = 1;\r
\r
if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
{\r
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
\r
if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
{\r
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;\r
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
- BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK; \r
- }\r
- \r
- /* Wait until DATA line has been pulled up to idle by the target */\r
- while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining);\r
+ BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
+\r
+ /* Wait until DATA line has been pulled up to idle by the target */\r
+ while (!(BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK) && TimeoutMSRemaining);\r
+ } \r